• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A non-volatile resistive memory cell comprising a Metal-Insulator-Metal stack comprising two electrodes and a multilayer insulator, positioned between said two electrodes, comprising a thin oxide layer for resistive transition and a gap reservoir layer. of oxygen characterized in that the stack comprises from bottom to top: the lower electrode comprising a metal layer M1, the insulation comprising a stoichiometric metal oxide layer I2 and a layer of stoichiometric metal oxide I2p forming said layer an oxygen vacancy reservoir, the upper electrode comprising a metal oxide layer I3 and a metal layer M4, so that the oxygen vacancy reservoir layer is interposed between two stoichiometric I2 and I3 metal oxide layers; . The invention will find application in the field possibly in all the applications already covered by existing non-volatile memories; in particular, memories of Flash type. It can also replace traditional static memory or SRAM, static random access memory. The invention will also find its application for the production of memory structures of the neuromorphic type or for CBRAM memories for the acronym "Conductive Bridge Ramdom Access Memory".
    公开号:FR3031416A1
    申请号:FR1550049
    申请日:2015-01-06
    公开日:2016-07-08
    发明作者:Remy Gassilloud；Mathieu Bernard
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] TECHNICAL FIELD The present invention generally relates to non-volatile memories with resistive elements. It more particularly describes a resistive non-volatile memory cell and its manufacturing method.
    [0002] The invention will find its application possibly in all the applications already covered by the existing non-volatile memories; in particular, memories of Flash type. Because of their access time and their ease of writing, non-volatile memories with resistive elements can also replace the static traditional memory or SRAM, the static random access memory.
    [0003] The invention will also find its application for the production of memory structures of the neuromorphic type or for CBRAM memories for the acronym "Conductive Bridge Ramdom Access Memory" or in nanoelectronic devices based on the principle of transitions Metal / insulation also called "Mott insulator", such as for example Mott selectors, Mott transistors, devices including photo-induced Mott transitions. STATE OF THE ART The resistive element memories use a material that can switch reversibly between at least two stable states having different electrical resistances. Resistive memories are generally referred to as RRAM, the acronym for "resistive random access memory", that is, "resistive memory with random access". Among the various types of resistive memories existing those whose basic material is a dielectric, normally insulating, are more particularly considered. These memories designated by the term OxRAM use metal oxides (Ox) as dielectric material whose resistance can be controlled in a reversible manner. These memories implement an operating mode in which at least one conductive filament can be formed between two electrodes separated by the oxide after application of a sufficiently large voltage therebetween. Once the filament has been formed, a low resistance state, generally referred to as LRS, of the English "low resistance state" is obtained. This state can be reversed by a so-called "RESET" operation, in order to put the memory in a second high resistance state or HRS of the English "high resistance state", operation during which the filament or filaments are broken. Once the filament has been formed a first time so-called "SET" operation can reset the memory to a low resistance state or LRS by reforming at least one filament. In situ situational observation of filamentation in an asymmetric Ta205-xiTa02-x bila yer structure Gyeong-Su Park, Nature Communications 4, (2013) 2382, a MIM stack whose memory layer is composed of a metal oxide at Tantalum base, monolayer or bilayer Ta0x / Ta205. The Ta0x film, substoichiometric in oxygen and a reservoir of vacancies, provides the necessary gaps for the formation of the conductive filament in Ta205 making it possible to modulate the resistance of the latter.
    [0004] These non-volatile resistive memory structures have a reservoir of oxygen vacancies located in contact with the electrodes. This requires the use of electrodes insensitive to oxygen movements / gaps including electrodes made of noble materials. However, the use of noble electrodes strongly limits the use of such a stack in an integration with the standard of microelectronics where only a certain number of metals, not including noble metals, have shown their immunities -vis the operation of a transistor. In addition, a contact between a reservoir of oxygen vacancies and a non-noble electrode may induce a variation of the amount of oxygen in the oxygen vacancy reservoir as a function of time or during the cycling of the memory cell. result in increased variability from one device to another. There is therefore the need to provide a memory cell which has a reliability in terms of cycling and retention time function. SUMMARY OF THE INVENTION The present invention proposes for this purpose a resistive non-volatile memory cell comprising a Metal-Insulator-Metal type stack with a lower electrode and an upper electrode and in which the insulation is a multilayer comprising a layer of a stoichiometric metal oxide and a stoichiometric metal oxide layer forming an oxygen vacancy reservoir layer and wherein the metal layer forming the upper electrode comprises a stoichiometric metal oxide layer below said metal layer. This arrangement makes it possible to place the oxygen vacancy reservoir layer between two stoichiometric metal oxide layers removing the contact between said gap reservoir layer and the electrodes. In this way the amount of oxygen vacancies in the reservoir is stable over time and cycling of the memory. Advantageously, the selection of materials for the electrodes extends outside the noble metals which allows integration of the memory cell according to the invention to the standard of microelectronics in a transistor. Advantageously, the electrodes are non-noble metals.
    [0005] Advantageously, the metals M1 of the lower electrode M2 of the multilayer insulator and M3 of the stoichiometric metal oxide layer are chosen so that the metal M3 reduces the stoichiometric metal oxide 12 of the insulator but not a stoichiometric metal oxide 11 potentially present on the surface of the metal layer forming the lower electrode.
    [0006] Advantageously, the free formation enthalpy DG3 of the stoichiometric metal oxide 13 by oxidation of a metal M3 is greater in absolute value than the free formation enthalpy DG2 of the stoichiometric metal oxide 12 by oxidation of a metal M2 . Advantageously, the free formation enthalpy DG 1 of the stoichiometric metal oxide 11 by oxidation of a metal M 1 is greater than or equal in absolute value to the free formation enthalpy DG3 of the stoichiometric metal oxide 13 by oxidation of a metal M3. According to another aspect, the invention relates to a method of manufacturing a memory cell according to any one of the preceding claims comprising the following successive steps of depositing a metal layer M1 to form the lower electrode, depositing a metal oxide layer 12, depositing a metal layer M3, reacting the metal layer M3 with the stoichiometric metal oxide 12 forming a stoichiometric oxide 12p and a metal oxide 13, depositing a metal layer M4.
    [0007] According to another aspect, the invention relates to a microelectronic device characterized in that it comprises a memory cell as described above. Advantageously, the device comprises a cavity in which the memory cell is at least partially arranged. This provision makes it possible by confinement effect to overcome the impact of the exogenous oxygen provided by the successive steps during the manufacture of such a device and in particular during the deposition of interconnection oxide. This makes it possible to consider locating the filament in a well-defined and preferably centered region of the stack, which leads to a reduction in the potential for forming the filament Vf by constricting the current lines passing through the stack. This integration also makes it possible to reduce the variability of the on-state of the device.
    [0008] According to another aspect, the invention relates to a method of manufacturing a device as described above comprising the following successive steps: - Conformal deposition of a stoichiometric metal oxide layer 12 in the cavity, - Deposit of a metal layer M3 in the cavity, - Reaction of the metal layer M3 with the stoichiometric metal oxide 12 forming a stoichiometric oxide 12p and a stoichiometric metal oxide 13, - Deposition of at least one metal layer M4 in the cavity.
    [0009] BRIEF DESCRIPTION OF THE FIGURES The objects, objects, as well as the features and advantages of the invention will emerge more clearly from the detailed description of an embodiment of the latter which is illustrated by the accompanying figures in which: Figure 1: Diagram of a memory cell according to the invention. 2: Curve illustrating the oxygen profile in each of the layers of the stack of a memory cell according to the invention. Figures 3 to 9 show a memory cell according to the invention arranged at least partially in a cavity of a microelectronic device.
    [0010] 3 shows the memory cell according to a first embodiment partially arranged in the cavity before the reaction of the metal layer M3 on the stoichiometric metal oxide layer 12. FIG. 4 represents the memory cell of FIG. metal M3 reacted on the stoichiometric metal oxide layer 12 to form the stoichiometric metal oxide layer 13 and the stoichiometric metal oxide layer 12p Figure 5: represents the memory cell of FIG. filament and current lines Figures 6 and 7 show the memory cell partially arranged in a cavity according to a second embodiment before and after reaction of the metal layer M3 on the stoichiometric metal oxide layer 12. FIGS. : represent the memory cell according to a third embodiment where the memory element is entirely arranged in s a cavity of a microelectronic device.
    [0011] The accompanying drawings are given by way of example and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily at the scale of practical applications. In particular, the relative thicknesses of the different layers and films are not representative of reality.
    [0012] DETAILED DESCRIPTION OF THE INVENTION Before proceeding to a detailed review of embodiments of the invention, are set forth below optional features that may optionally be used in combination or alternatively. It will first be recalled that the invention relates to a resistive non-volatile memory cell comprising a stack comprising two electrodes and a multi-layer insulator, placed between said two electrodes, comprising an oxide layer allowing a resistive transition and a layer oxygen deficiency tank system characterized in that the stack comprises from bottom to top: - a lower electrode comprising a metal layer M1, - an insulator comprising a stoichiometric metal oxide layer 12 and a metal oxide layer under stoichiometric 12p forming said oxygen vacancy reservoir layer - an upper electrode comprising a stoichiometric metal oxide layer 13 and a metal layer M4, so that the oxygen vacancy reservoir layer is interposed between two layers of oxygen stoichiometric metal oxides 12 and 13. Advantageously, metals M2 and M3 respectively to form the isolan 12 and 12p and to form the stoichiometric metal oxide layer 13 are chosen so that the formation free enthalpy DG3 of the stoichiometric metal oxide 13 by oxidation of the metal M3 is greater in absolute value than the free enthalpy of formation DG2 of the stoichiometric metal oxide 12 by oxidation of the metal M2. Advantageously, the lower electrode comprises, above the metal layer M1, a metal oxide layer 11 of M1. Advantageously, the metals M1 and M3 are chosen so that the free formation enthalpy DG1 of the oxide 11 by oxidation of a metal M1 is greater than or equal in absolute value to the free formation enthalpy DG3 of the oxide 13 by oxidation of an M3 metal. Advantageously, the metal M1 is chosen so that the free formation enthalpy DG1 of the oxide 11 by oxidation of a metal M1 is greater than or equal in absolute value to the free formation enthalpy DG of the reaction 2Cu + O2 -> 2CuO.
    [0013] Advantageously, the metals M1 and M4 are chosen from a non-noble metal other than Pd, Ag, Ir, Pt, Au, or a pure metal or a binary or ternary metal alloy, or an alloy based on nitride or carbide or silicide or conductive metal oxide.
    [0014] Advantageously, the metals M1 and M4 are chosen from TiN, TaN, TiAlN, TaAlN. Advantageously, the lower electrode and the upper electrode are symmetrical in the stack. Advantageously, the stoichiometric metal oxide layer 11 of M1 is chosen from TiO2 or TiON or Al2O3. Advantageously, the stoichiometric oxide layer 12 is formed from a metal M2 chosen from columns III, IV, V, of the periodic table, or Al or Si, or lanthanides. Advantageously, the stoichiometric oxide layer 12 is chosen from HfO 2, ZrO 2, TiO 2, Al 2 O 3, Ta 2 O 5, Nb 2 O 5, V 2 O 5, La 2 O 4, Gd 2 O 3, Lu 2 O 3, HfSiO, HfZrO, STO. Advantageously, the stoichiometric oxide layer 12 of a metal M2 has a thickness of 1 to 50 nm. Advantageously, the metal oxide layer 13 is formed from a metal M3 selected from a pure metal or a binary or ternary metal alloy. Advantageously, the metal M3 is selected from Si, Ti, Zr, Hf, Al, Ta, Nb, V, and the alloys in a mixture of these elements, for example TiAl, TaAl. Advantageously, the stack comprises from bottom to top: Ti N / TiO 2 / Ta 2 O 5 / TaO x / TiO 2 / Ti N, or Ti N / TiO 2 / Ta 2 O 5 / TaO x / N b 2 O 5 / Ti N, or TiN / TiO 2 N 2 O 5 / V0x / Nb 2 O 5 / TiN, or TiN / TiO2N205 / V0x / Ta205 / TiN Another object of the invention is a method of manufacturing a memory cell as described above comprising the following successive steps: depositing a metal layer Ml to form a lower electrode, - Deposition of a stoichiometric metal oxide layer 12, - Deposition of a metal layer M3, - Reaction of the metal layer M3 with the metal oxide 12 forming a stoichiometric oxide 12p and a stoichiometric metal oxide 13, - Deposition of a metal layer M4.
    [0015] Advantageously, the deposition of the metal layer M3 is carried out by flash vapor deposition.
    [0016] Advantageously, the metal layer M3 is deposited on a thickness of 0.1 to 2 nm. Advantageously, the stoichiometric metal oxide layer 12 is deposited chemically.
    [0017] Advantageously, the stoichiometric metal oxide layer 12 is treated with plasma or by plasma nitriding. Advantageously, the stoichiometric metal oxide layer 12 is implanted with aluminum. Another object of the invention is a microelectronic device characterized in that it comprises a memory cell as described above. Advantageously, the device comprises a cavity in which the memory cell is at least partially arranged. Advantageously, the lower electrode of the memory cell is arranged below and outside the cavity.
    [0018] Advantageously, the lower electrode of the memory cell is arranged in the cavity. Advantageously, the device comprises a plurality of interconnection level and a plurality of connection plug between the levels, each plug comprising a cavity in which at least a memory cell as described above is at least partially arranged. Another object of the invention is a method of manufacturing a device as described above comprising the following successive steps: - Conformal deposition of a stoichiometric metal oxide layer 12 in the cavity, - Deposit of a M3 metal layer in the cavity, - Reaction of the metal layer M3 with stoichiometric metal oxide 12 forming a stoichiometric oxide 12p and a stoichiometric metal oxide 13, - Deposition of at least one metal layer M4 in the cavity.
    [0019] Advantageously, the method comprises the conformal deposition of a metal layer M1 in the cavity to form the lower electrode before the deposition of the stoichiometric metal oxide layer 12. Advantageously, the method comprises the deposition of a metal layer M5 for plug the cavity.
    [0020] Advantageously, the deposition of the metal layer M3 is carried out by flash vapor deposition.
    [0021] Advantageously, the metal layer M3 is deposited on a thickness of 0.1 to 2 nm. Advantageously, the stoichiometric metal oxide layer 12 is deposited chemically.
    [0022] Advantageously, the stoichiometric metal oxide layer 12 is treated with plasma or by plasma nitriding. Advantageously, the stoichiometric metal oxide layer 12 is implanted with aluminum. It will be noted that the relative characteristics stated above, in particular those relating to the stacking of the memory cell and to the arrangement of the memory cell in the cavity, although advantageously advantageous in synergy when they are combined, can be exploited independently of each other and still confer certain technical advantages. It is specified that in the context of the present invention, the term "over", "overcomes" or "underlying" or their equivalents do not necessarily mean "in contact with". For example, the deposition of a first layer on a second layer does not necessarily mean that the two layers are in direct contact with one another, but that means that the first layer at least partially covers the second layer. being either directly in contact with it or separated from it by another layer or another element. The terms "layer" and "film" are used as synonyms. The term "thin layer", a layer whose thickness varies from a few atomic layers to a few microns. By microelectronic device is meant any type of device made with microelectronics means. These devices include, in addition, devices with a purely electronic purpose, micromechanical or electromechanical devices (MEMS, NEMS, etc.) as well as optical or optoelectronic devices (MOEMS, etc.). The memory cell according to the invention is a stack of metal-insulator-metal (MIM) type layers, more specifically of the Metal-Oxide-Metal (MOM) type. The memory cell is a nonvolatile memory with resistance change. Resistive Random Access Memory (RRAM) relies on the change of resistance of an active material, more precisely in the sub-category of OxRRAM (Oxide RRAM) the active material is an oxide forming an insulator 2. The two layers on both sides of the insulator 2 are electrodes 1, 3.
    [0023] The stack according to a preferred embodiment of the invention is shown in Figure 1. The stack comprises from bottom to top: a metal layer M1, optionally a metal oxide layer 11, a stoichiometric metal oxide layer 12, a stoichiometric metal oxide layer 12p, a stoichiometric metal oxide layer 13 and a metal layer M4. A lower electrode 1 also called "bottom electrode" in English comprises the metal layer M1 and potentially over a metal oxide layer 11. The metal layer M1 is formed by a non-noble metal. Noble means a metal that does not spontaneously oxidize in the air. According to the invention, the noble metals are silver (Ag), Iridium (Ir), Platinum (Pt), gold (Au) and palladium (Pd). The metal layer M1 may be a pure metal or a binary or ternary metal alloy such as, for example, TiAl, TaAl, TiAlN, TaAlY or else an alloy based on nitride, or carbide, or silicide, or on conductive metal oxide, preferentially TiN, TaN. The metal oxide 11 is an oxide that can be formed during the manufacturing process of the memory cell. The metal of the metal layer M1 can be oxidized by the air in contact, or by a stoichiometric metal oxide 12 described hereinafter. Alternatively, the metal layer M1 can also be intentionally oxidized to form the metal oxide 11. According to yet another possibility, the metal oxide 11 is deposited, for example to form a selector or diode non-linear resistance. For example, the metal oxide 11 is TiO 2 or TiON. An insulator 2 advantageously comprises at least two layers of materials also called a multilayer, the insulator 2 is preferably a bilayer. The bi-layer comprises a stoichiometric metal oxide layer 12 and a stoichiometric metal oxide layer 12p. The term stoichiometric is understood as the proportion of elements in a crude formula. A stoichiometric layer according to the invention has a proportion of oxygen less than the stoichiometric proportion of the compound. The stoichiometric metal oxide 12 constitutes the active layer having a resistive variation as a function of an applied voltage. The stoichiometric metal oxide 12p is a reservoir layer of oxygen vacancies. This layer is an oxide having a lesser amount of oxygen than the stoichiometric oxide. This oxygen deficiency is defined as oxygen deficiency. The more oxygen deficient the material, the more conductive it is. This layer 12p of oxygen vacancy reserve makes it possible to facilitate the resistivity variations of the oxide layer 12. In fact, the two layers 12 and 12p interact during the SET and RESET phases so as to allow the formation of the filaments conductors between the two electrodes 1 and 3.
    [0024] The stoichiometric metal oxide layer 12 is advantageously a thin layer. The stoichiometric metal oxide 12 is a metal stoichiometric oxide. This oxide 12 is chosen from columns III, IV, V, of the Periodic Table, or Aluminum (Al) or Silicon (Si), or a lanthanide, for example HfO 2, ZrO 2, TiO 2, Al 2 O 3, Ta 2 O 5, Nb 2 O 5, La204, Gd203, Lu203, or ternary compounds HfSiO, HfZrO, STO. The stoichiometric metal oxide 12 is preferably Ta 2 O 5. Preferably, the stoichiometric metal oxide layer 12 is deposited chemically. Advantageously its thickness is between mm and 50 nm. According to one possibility, the stoichiometric metal oxide 12 is plasma treated. This type of treatment makes it possible to modulate the final thickness L and / or the oxygen depletion profile of the stoichiometric metal oxide layer 12p. For example, treatments of the plasma nitriding type (radio-frequency plasma or microwave N2) with nitrogen or nitriding in a reducing atmosphere typically in a hydrogenated atmosphere N2 + H2.
    [0025] Alternatively, the stoichiometric metal oxide layer 12 is processed by implantation. The implantation can be made directly in the layer 12 or through the stoichiometric metal oxide layer 13 and the stoichiometric metal oxide layer 12p. This implantation treatment makes it possible to promote the formation of conductive filaments between the lower electrode 1 and the upper electrode 3 of the stack of the memory cell. For example, an aluminum implantation can be performed. The metal oxide 12p is a sub stoichiometric oxide. This oxide 12p is not voluntarily deposited but comes from a reaction with a metal M3 deposited on top of the stoichiometric metal oxide 12.
    [0026] The metal M3 is preferably a pure metal or a binary or ternary metal alloy, for example TiAl, TaAl, preferably pure titanium (Ti). According to a preferred embodiment, the metal M3 is deposited by flash vapor deposition (PVD flash). The term "flash" corresponds to the control over a very short time, advantageously of the order of one second, the deposit of a film of some Angstroam. Preferably, the deposited metal layer M3 has a thickness of 0.1 μm to 2 nm. The control of this time makes it possible very advantageously to deposit very precisely the quantity of metal M3 desired so as to be able to modulate the depth of oxygen depletion in the stoichiometric metal oxide layer 12 and the final thickness L of the metal oxide layer. under stoichiometric 12p.
    [0027] The flash time will make it possible to define the final thickness of the stoichiometric metal oxide 13. The type of metal deposition M3 influences the overall resistivity of the memory cell. According to one embodiment, the flash deposit makes it possible to form localized islands, also called dots, nanodots or nanocrystals, making it possible to locally reduce the stoichiometric metal oxide layer 12, and thus make it possible to locate the conductive filaments 4 in the layer of stoichiometric metal oxide 12. The deposited metal M3 is no longer present as a metal in the finalized memory cell. The metal M3 is configured to react with the stoichiometric metal oxide layer 12. This reaction leads to a partial reduction of the stoichiometric metal oxide 12 to a stoichiometric metal oxide 12p and to the oxidation of the M3 metal to a protective layer. Stoichiometric metal oxide 13. As a preferred example, the metal M3 is pure titanium which reacts with the stoichiometric metal oxide 12, Ta2O5, to form the stoichiometric metal oxide 13, TiO2, and the stoichiometric metal oxide. 12p, Ta02. This reaction can according to one possibility be activated thermally. Advantageously, the reduction of the oxide 12 by the metal M3 is possible if the free formation enthalpy (DG3) of the reaction M3 + O2-> 13 is greater in absolute value than the free formation enthalpy (DG2) of the reaction M2 + 02-> 12. This can be summarized by DG3 I> I DG2 I. An Elligham chart can typically be used to predict the direction of the reactions. The amount of metal M3 deposited is very small compared to the thickness of 12 so as not to consume the entire stoichiometric metal oxide 12 without being able to obtain the oxygen depletion profile referred to in the metal oxide under stoichiometric 12p .
    [0028] According to one embodiment the metal M3 reduces the stoichiometric metal oxide layer 12, but not an oxide layer 11 possibly present on the surface of the metal layer M1. Therefore it is advantageous for the free formation enthalpy (DG 1) of the reaction M 1 + O 2 -> 11 to be greater than or equal in absolute value to the free enthalpy (DG3) for forming the reaction M3 + O2. -> 13 that is to say I DG 1 I DG3 I or I DG 1 I DG (2Cu + 02-> 2CuO) I that is to say the free enthalpy DG 1 formation of oxide 11 by oxidation of a metal M1 is greater than or equal in absolute value to the free formation enthalpy DG of the reaction 2Cu + 02-> 2CuO. An upper electrode 3 also called "top electrode" in English comprises the metal layer M4 and a stoichiometric metal oxide layer 13. The metal oxide layer 13 forms an insulating layer for isolating the metal layer M4 partially forming the upper electrode 3 of the stoichiometric metal oxide layer 12p constituting the oxygen vacancy reservoir layer. The presence of this insulating layer 13 eliminates noble electrodes not likely to be oxidized.
    [0029] The metal layer M4 is formed by a non-noble metal. Noble means a metal that does not spontaneously oxidize in the air. According to the invention, the noble metals are silver (Ag), Iridium (Ir), Platinum (Pt), gold (Au) and palladium (Pd). The metal layer M4 may be a pure metal or a binary or ternary metal alloy such as for example TiN, TaN, TiAlN, TaAlN or else an alloy based on nitride, or carbide, or silicide, or oxide conductive metal, preferably TiN, TaN. According to a preferred embodiment, the lower electrode 1 and the upper electrode 3 are symmetrical. Symmetrical means that the two electrodes 1 and 3 are of the same thickness, the same properties, the same materials.
    [0030] According to a preferred example, the stack of the memory cell consists of TiN / TiO 2 / Ta 2 O 5 / TaO x / TiO 2 / TiN, or TiN / TiO 2 / Ta 2 O 5 / TaO x / Nb 2 O 5 / TiN, or TiN / TiO 2 A / 205 / V0x / Nb 2 O 5 / TiN, or TiN / TiO 2 / V 2 O 5 / V0x / Ta 2 O 5 / TiN According to the invention, an oxygen profile as illustrated in FIG. 2 is particularly sought after. It can be seen in this figure that the stoichiometric metal oxide layer 12p has an oxygen depletion relative to the other stoichiometric metal oxide layers 11, 12 and 13 of the stack. The thickness of the stoichiometric metal oxide 12 is noted 12, and the thickness of the depletion profile is small. The depletion profile is characterized by 112 <L12. The present invention also relates to a method of manufacturing a memory cell as described above. Such a method comprises a series of successive steps including the deposition of the metal layer M1, then the deposition of the stoichiometric metal oxide 12 and then the deposition of a metal layer M3 and then the formation of the stoichiometric metal oxide layer 13 and the stoichiometric metal layer 12p by reaction between the metal M3 and the stoichiometric oxide 12, then the deposition of a metal layer M4.
    [0031] The reaction between the metal layer M3 and the stoichiometric metal oxide 12 is advantageously controlled by the choice of metals M1, M2 and M3. Advantageously, the free formation enthalpy (DG3) of the reaction M3 + O2-> 13 is greater in absolute value than the free formation enthalpy (DG2) of the reaction M2 + 02-> 12. It is advantageous for the free formation enthalpy (DG1) of the reaction M1 + 02 -> 11 to be greater than or equal in absolute value to the free enthalpy (DG3) for forming the reaction M3 + O2-> 13. Advantageously, the metal layer M3 reduces the stoichiometric metal oxide layer 12, but not a stoichiometric oxide layer 11 possibly present on the surface of the metal layer M1. A memory cell according to the invention can be integrated into various microelectronic devices ranging from portable data storage devices to neuromorphic memory structures. The integration of the active films of a memory cell according to the invention as described above, is currently done in the Back-End lines of microelectronic devices using memory cells, at a metal level Mi, the index i being an integer that represents the number of interconnect levels in a device. These films are deposited in planar on the surface of a plug. Then, an etching step makes it possible to define the final size of the memory cell. Finally, a new plug is created on the upper level (Mi + 1) and connects the upper electrode of the memory cell. The formation of a plug requires the deposition of an oxide at low temperature, the etching of a hole aligned with the upper electrode, and the deposition in this hole of a contact metal, typically TiN / VV or Ta / TaN / Cu. The deposition of the low temperature oxide brings exogenous oxygen into contact with the memory cell and causes a deterioration of the properties of the cell. Document US2014 / 0197368 discloses the possibility of limiting the impact of the exogenous oxygen brought about by the deposition step of the low temperature oxide by depositing a conformal SiN film by CVD after the etching of the element. planar deposited memory This film makes it possible to "seal" the sides of the memory cell. This type of oxygen capping with SiN is widely used for CMOS transistors. However, with the reduction in size of the devices, this SiN film also undergoes a thickness reduction in order to follow the overall geometry of the devices. For example, in the lines of the Mi levels, the thickness of the level represents approximately 2 to 3 times the width of the plug. This is to respect a reasonable ratio aspect for the plugs to ensure an optimal filling of the CVD chemical plugs. The minimum thickness of the SiN film proposed in this document is 20 nm. In the case where the memory element has a size of the order or less than 40 nm, it can be seen that a film of 20 nm represents approximately 1/3 of the height of the level Mi. Or, below a With a certain thickness of SiN of about 20 nm, the SiO2 plasma deposition process impacts the underlying films. Indeed, the treatment plasma used in-situ during the deposition of the inter-plug insulator is physically penetrating and type 0 * species can pass through the SiN protective film. There is therefore the need to propose a technology that makes it possible to limit the impact of the exogenous oxygen brought about by the deposition step of the low temperature oxide during the formation of a plug.
    [0032] According to another aspect of the invention, the memory cell as described above can be arranged at least partially in a cavity 6 also called "via". Advantageously, the invention will also find application for microelectronic and nanoelectronic devices comprising a plurality of interconnection levels and a plurality of connection plugs between the levels. Each plug comprises a cavity 6. According to the invention, the cavity 6 has a width 8 of opening less than 180 nm, preferably equal to or less than 65 nm. The cavity 6 is formed in chemically deposited 5iO 2 oxide to form an interconnect plug opening on a lower level connection line Mi-1. According to a first embodiment illustrated in FIGS. 3 to 7, the stack of the memory cell is partially arranged in the cavity 6. The connecting line 7 of the lower level Mi-1 forms the metal layer M1 and possibly its layer of stoichiometric metal oxide 11. This is possible when the connecting line 7 is Al, Ta, TaN or TiN. The stoichiometric metal oxide layer 11 is then in Al 2 O 3, TiO 2, TiON, Ta 2 O 5, TaO N. The metal layer M1 of the lower electrode 1 and optionally the stoichiometric metal oxide layer 11 are arranged outside and under the cavity. Underlay means that the metal layer M1 is present before the formation of the cavity, and outside is understood to mean that the metal layer M1 is of greater length than the width of the cavity 6. The cavity 6 comprises bottom up, the insulator 2 comprising the stoichiometric metal oxide layer 12 and the stoichiometric metal oxide layer 12p forming said oxygen vacancy reservoir layer and then the stoichiometric metal oxide layer 13 and the metal layer M4.
    [0033] According to this stack, the stoichiometric metal oxide layer 11 is advantageously present to maintain the sub-stoichiometric metal oxide layer 12p in contact with stoichiometric metal oxide layers 11, 12 and 13.
    [0034] According to a second embodiment illustrated in FIGS. 8 and 9, the stack of the memory cell is entirely arranged in the cavity 6. The connection line 7 of the lower level Mi-1 does not form the metal layer M1. This is particularly the case when the connection line 7 is made of a material that is not adapted to the properties necessary for forming a lower electrode 1. The metal layer Ml of the lower electrode 1 and optionally the stoichiometric metal oxide layer 11 are arranged in In this embodiment, it is noted that the insulator 2 formed at least by the stoichiometric metal oxide layer 12 conforms ensures the electrical insulation between the metal layers M1 and M4. The metal layer M1 then acts as a barrier intended to limit the diffusion of the material of the connection line 7 in the memory cell. The method of manufacturing a memory cell comprises the steps described below. The formation of a cavity 6 opening on a connection line 7 of lower level Mi-1. Optionally, the conformal deposition of a metal layer M1 in the cavity 6. Optionally, the conformal deposition or the formation of a stoichiometric metal oxide layer 11 in contact with the metal layer M1. The conformal deposition of a stoichiometric metal oxide layer 12. Advantageously, the deposition of the stoichiometric metal oxide layer 12 is carried out by chemical vapor deposition (CVD acronym). The term "compliant deposition" is understood to mean that the deposition is carried out in the bottom and on the walls of the cavity 6. The deposition of a layer of metal M3 at the bottom of the cavity, preferably deposited by physical flash vapor deposition (PVD acronym), by example flash Ti, Al, Zr, Hf, Si, Ta, Nb, V. The method comprises a step of capping the cavity 6. At least one metal layer M4 is deposited in the cavity 6. The metal layer M4 is advantageously impermeable to oxygen such as for example Co, Ni, Cu. The deposits of the metal layers M1 and M4 are advantageously made as for the stack illustrated in FIG. 1. The reaction of the metal layer M3 on the stoichiometric metal oxide 12 results in the formation of the sub-stoichiometric oxide 12p located around, more precisely in the immediate vicinity of the stoichiometric metal oxide layer 13. This reaction can be assisted by annealing typically aligned with Back End annealing at about 400 ° C. In this embodiment, the exogenous oxygen-sensitive layer 12p is buried in the cavity bottom 6, protected from oxidation by insulating layers: the residual stoichiometric metal oxide 12 (ie unreacted) and the stoichiometric metal oxide 13 and the metal layer M4. According to the invention, the method comprises a step of de-contact plugs of the same level comprising a chemical mechanical polishing (acronym CMP). During the deposition of the stoichiometric metal oxide 12 and metal M4 layers, the material potentially remains outside the cavity 6. This material can cause conduction between the different cavities 6 of the level in the device. Advantageously, the stoichiometric metal oxide layer 12 has a width L of between 2 and 20 nm. This width L is understood as the dimension separating the walls of the cavity 6 from the stoichiometric metal oxide layer 13. Advantageously, the stoichiometric metal oxide layer 13 has a width 1 of between 10 and 40 nm, preferably 25 nm. For example, for a 45 nm cavity, width L of the stoichiometric metal oxide layer 12 is 10 nm and width 1 of the stoichiometric metal oxide layer 13 is 25 nm. This stacking arrangement makes it possible to confine / locate the filament of gaps under the stoichiometric metal oxide layer 13 of width I. In addition, the current lines are located in a limited area increasing local heating. This constriction of the current lines makes it possible to reduce the formation potential of the filament Vf. The formation potential Vf is advantageously less than 3V and preferably of the order of 2V thus allowing integration of the memory cell according to the invention into CMOS devices. The invention also has the advantage of reducing the variability of the on state, Ron, of the memory cell.
    [0035] According to another possibility, the capping of the cavity can be achieved by stacking several layers. As illustrated in FIGS. 6 to 9, two metal layers M4 and M5 are deposited in the cavity 6 to close it. The metal layer M4 may be TiN or TaN. The metal layer M5 is an oxygen impermeable metal such as cobalt, nickel or copper. In this arrangement, the manufacturing method comprises a step of disconnecting the metal layers M1 and M5, advantageously by CMP. This stack of the memory cell at least partially in a cavity can be applied to the field of CBRam memories in which the modulation of the resistance of the insulator 2 is carried out by a filament, for example copper, in the case where the metal layer M4 is Copper. This type of memory can be used to create memory structures of the neuromorphic type.
    [0036] REFERENCES 1. Lower electrode 2. Insulator 3. Upper electrode 4. Filament 5. Current lines 6. Cavity 7. Connection line 8. Opening width of the cavity M 1. Metal layer 11. Metal oxide layer 12. Stoichiometric metal oxide layer 12p. Sub stoichiometric metal oxide layer 13. M4 stoichiometric metal oxide layer. Metal oxide layer 1_12p. Final thickness of the stoichiometric oxide layer 12p 112p Thickness of the depletion profile I. Width of the stoichiometric metal oxide layer 13 L. Width of the stoichiometric metal oxide layer 12
    权利要求:
    Claims (28)
    [0001]
    REVENDICATIONS1. A non-volatile resistive memory cell comprising a stack comprising two electrodes (1, 3) and a multi-layer insulator (2), placed between said two electrodes (1, 3), comprising an oxide layer allowing a resistive transition and a layer oxygen deficiency tank system characterized in that the stack comprises from bottom to top: - a lower electrode (1) comprising a metal layer M1, the insulation (2) comprising a stoichiometric metal oxide layer 12 and a stoichiometric metal oxide layer 12p forming said oxygen vacancy reservoir layer; an upper electrode (3) comprising a stoichiometric metal oxide layer 13 and a metal layer M4, so that the reservoir layer of vacu Oxygen is interposed between two stoichiometric metal oxide layers 12 and 13.
    [0002]
    2. The memory cell according to claim 1, wherein metals M2 and M3 are chosen so that the free formation enthalpy DG3 of the stoichiometric metal oxide 13 by oxidation of the metal M3 is greater in absolute value than the free enthalpy of the metal. DG2 formation of the stoichiometric metal oxide 12 by oxidation of the M2 metal.
    [0003]
    A memory cell according to any preceding claim wherein the lower electrode (1) comprises above the metal layer M1, a stoichiometric metal oxide layer 11 of M1.
    [0004]
    4. Memory cell according to the preceding claim wherein metals M1 and M3 are chosen such that the free formation enthalpy DG1 of the stoichiometric metal oxide 11 by oxidation of the metal M1 is greater than or equal in absolute value to the DG3 free formation enthalpy of the stoichiometric metal oxide 13 by oxidation of the M3 metal.
    [0005]
    5. A memory cell according to any one of the preceding claims wherein the metal layers M1 and M4 are formed by at least one of a non-noble metal other than Pd, Ag, Ir, Pt, Au,
    [0006]
    6. Memory cell according to the preceding claim wherein the metals of the metal layers M1 and M4 are a pure metal or a binary or ternary metal alloy, or an alloy based on nitride or carbide or silicide or conductive metal oxide .
    [0007]
    7. Memory cell according to any one of the preceding claims wherein the metals M1 and M4 are selected from TiN, TaN, TiAIN, TaAIN.
    [0008]
    Memory cell according to any of the preceding claims wherein the lower electrode (1) and the upper electrode (3) are symmetrical in the stack.
    [0009]
    The memory cell of any preceding claim in combination of claim 3 wherein the stoichiometric metal oxide layer 11 of the metal layer M1 is selected from TiO2 or TiON or Al2O3. 10
    [0010]
    A memory cell according to any one of the preceding claims in combination of claim 3 wherein the stoichiometric oxide layer 12 of a metal M2 is selected from columns 111, IV, V, of the periodic table, or Al or If, or lanthanides.
    [0011]
    11. Memory cell according to the preceding claim wherein the stoichiometric oxide layer 12 is selected from HfO2, ZrO2, TiO2, Al2O3, Ta2O5, Nb2O5, V205, La2O4, Gd2O3, Lu2O3, HfSiO, HfZrO, STO.
    [0012]
    12. The memory cell as claimed in claim 1, wherein the stoichiometric oxide layer 12 of a metal M2 has a thickness of 1 to 50 nm. 20
    [0013]
    13. The memory cell according to any one of the preceding claims wherein the metal M3 forming the metal oxide layer 13 is a pure metal or a binary or ternary metal alloy.
    [0014]
    14. Memory cell according to the preceding claim wherein the metal M3 is selected from Si, Ti, Zr, Hf, Al, Ta, Nb, V, and the alloys in a mixture these elements for example TiAl, TaAl.
    [0015]
    15. A memory cell according to any one of the preceding claims wherein the stack comprises from bottom to top: TiN / TiO2fTa205 / Ta0x / Ti02 / TiN.
    [0016]
    16. Microelectronic device characterized in that it comprises a memory cell according to any one of the preceding claims.
    [0017]
    17. Microelectronic device according to the preceding claim comprising a cavity (6) in which is at least partially arranged the memory cell.
    [0018]
    18. Device according to the preceding claim wherein the lower electrode (1) of the memory cell is arranged below and outside the cavity 35 (6).
    [0019]
    19. Device according to claim 17 wherein the lower electrode (1) of the memory cell is arranged in the cavity (6).
    [0020]
    20. Apparatus according to any one of the four preceding claims comprising a plurality of interconnection level and a plurality of connection plug between the levels, each plug comprising a cavity (6) in which at least a memory cell is at least partially arranged. any of claims 1 to 15.
    [0021]
    21. A method of manufacturing a memory cell according to any one of claims 1 to 15 comprising the following successive steps: depositing a metal layer M1 to form the lower electrode (1), depositing a layer of stoichiometric metal oxide 12, deposition of a metal layer M3, - reaction of the metal layer M3 with the stoichiometric metal oxide 12 forming a stoichiometric oxide 12p and a stoichiometric metal oxide 13, deposition of a metal layer M4.
    [0022]
    22. Method according to the preceding claim wherein the deposition of the metal layer M3 is carried out by flash vapor deposition.
    [0023]
    23. Method according to any one of the two preceding claims wherein the metal layer M3 is deposited to a thickness of 0.1 to 2 nm.
    [0024]
    24. A method according to any of the three preceding claims wherein the stoichiometric metal oxide layer 12 is deposited chemically.
    [0025]
    25. A process according to any one of the preceding claims wherein the stoichiometric metal oxide layer 12 is plasma treated or by plasma nitriding.
    [0026]
    26. A method according to any one of the preceding claims wherein the stoichiometric metal oxide layer 12 is implanted with aluminum.
    [0027]
    27. A method of manufacturing a device according to any one of claims 17 to 20, comprising the following successive steps: Conformal deposition of a stoichiometric metal oxide layer 12 in the cavity (6), deposition of a layer M3 metal in the cavity (6), Reaction of the metal layer M3 with the stoichiometric metal oxide 12 forming a stoichiometric oxide 12p and a stoichiometric metal oxide 13, - Deposition of at least one metal layer M4 in the cavity (6 ).
    [0028]
    28. The method according to the preceding claim comprising, prior to the step of depositing the stoichiometric metal oxide layer 12, a deposition step conforming a metal layer M1 in the cavity (6) to form the lower electrode (1). .
    类似技术:
    公开号 | 公开日 | 专利标题
    EP3043396B1|2018-06-06|Resistive non-volatile memory cell and method for manufacturing same
    US9385164B2|2016-07-05|Method of making a resistive random access memory device with metal-doped resistive switching layer
    US9570682B2|2017-02-14|Semiconductor memory device and method of manufacturing the same
    US8956939B2|2015-02-17|Method of making a resistive random access memory device
    EP2209139B1|2014-12-17|Non-volatile memory element and non-volatile semiconductor device using the non-volatile memory element
    KR100913395B1|2009-08-21|Memory devices and method for fabricating the same
    US8445883B2|2013-05-21|Nonvolatile semiconductor memory device and manufacturing method thereof
    US8686390B2|2014-04-01|Nonvolatile memory element having a variable resistance layer whose resistance value changes according to an applied electric signal
    KR101127236B1|2012-03-29|Method for fabricating resistance memory device
    WO2010064446A1|2010-06-10|Nonvolatile memory element and nonvolatile memory device
    JP5340508B1|2013-11-13|Resistance variable nonvolatile memory device and manufacturing method thereof
    JP4795485B2|2011-10-19|Nonvolatile memory element and manufacturing method thereof
    US9520562B2|2016-12-13|Method of making a resistive random access memory
    JP2010251352A|2010-11-04|Nonvolatile storage element and method of manufacturing the same
    EP2652808B1|2020-10-21|Memristive element and electronic memory based on such elements
    JP2010212541A|2010-09-24|Nonvolatile memory device and method of manufacturing the same
    JP5232935B2|2013-07-10|Method for manufacturing variable resistance element
    KR101925448B1|2018-12-05|Resistance variable memory device and method for fabricating the same
    KR20100104015A|2010-09-29|Resistive memory device
    CN107403822A|2017-11-28|Resistive random access internal memory and its manufacture method
    EP3965177A1|2022-03-09|Resistive memory with switching zone between two dielectric regions with different dielectric dopings and/or constants
    KR20110020886A|2011-03-03|Method for fabricating resistance memory device
    WO2020249699A1|2020-12-17|Method for manufacturing an oxram resistive memory cell
    FR3097368A1|2020-12-18|PROCESS FOR DETERMINING A PARAMETER FOR THE MANUFACTURING OF A RESISTIVE LIVE MEMORY CELL
    FR3002070A1|2014-08-15|METHOD FOR PRE-PROGRAMMING A PHASE CHANGE MEMORY CELL AND PHASE CHANGE MEMORY CELL
    同族专利:
    公开号 | 公开日
    EP3043396A1|2016-07-13|
    FR3031416B1|2018-09-07|
    EP3043396B1|2018-06-06|
    US9768379B2|2017-09-19|
    US20160197271A1|2016-07-07|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20120032132A1|2010-08-06|2012-02-09|Samsung Electronics Co., Ltd.|Nonvolatile Memory Elements And Memory Devices Including The Same|
    US20130146829A1|2011-12-12|2013-06-13|Samsung Electronics Co., Ltd.|Resistive random access memory devices and methods of manufacturing the same|
    US7791925B2|2008-10-31|2010-09-07|Seagate Technology, Llc|Structures for resistive random access memory cells|
    CN101960595B|2009-02-04|2012-11-14|松下电器产业株式会社|Non-volatile memory element|
    KR101744758B1|2010-08-31|2017-06-09|삼성전자 주식회사|Nonvolatile memory element and memory device including the same|
    US9680093B2|2011-09-16|2017-06-13|Panasonic Intellectual Property Management Co., Ltd.|Nonvolatile memory element, nonvolatile memory device, nonvolatile memory element manufacturing method, and nonvolatile memory device manufacturing method|
    JP2014103326A|2012-11-21|2014-06-05|Panasonic Corp|Nonvolatile memory element and manufacturing method thereof|
    US9680095B2|2013-03-13|2017-06-13|Macronix International Co., Ltd.|Resistive RAM and fabrication method|
    CN106030801B|2014-03-25|2020-09-15|英特尔公司|Techniques for forming non-planar resistive memory cells|US9754665B2|2016-01-29|2017-09-05|Sandisk Technologies Llc|Vacancy-modulated conductive oxide resistive RAM device including an interfacial oxygen source layer|
    US9887351B1|2016-09-30|2018-02-06|International Business Machines Corporation|Multivalent oxide cap for analog switching resistive memory|
    KR20180079137A|2016-12-31|2018-07-10|에스케이하이닉스 주식회사|Resistive memory device and method of fabricating the same|
    US10497752B1|2018-05-11|2019-12-03|International Business Machines Corporation|Resistive random-access memory array with reduced switching resistance variability|
    US10727407B2|2018-08-08|2020-07-28|International Business Machines Corporation|Resistive switching memory with replacement metal electrode|
    法律状态:
    2016-01-28| PLFP| Fee payment|Year of fee payment: 2 |
    2016-07-08| PLSC| Publication of the preliminary search report|Effective date: 20160708 |
    2017-01-30| PLFP| Fee payment|Year of fee payment: 3 |
    2018-01-26| PLFP| Fee payment|Year of fee payment: 4 |
    2019-01-30| PLFP| Fee payment|Year of fee payment: 5 |
    2020-10-16| ST| Notification of lapse|Effective date: 20200910 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1550049A|FR3031416B1|2015-01-06|2015-01-06|RESISTIVE NON-VOLATILE MEMORY CELL AND METHOD OF MANUFACTURING THE SAME|FR1550049A| FR3031416B1|2015-01-06|2015-01-06|RESISTIVE NON-VOLATILE MEMORY CELL AND METHOD OF MANUFACTURING THE SAME|
    EP16150341.2A| EP3043396B1|2015-01-06|2016-01-06|Resistive non-volatile memory cell and method for manufacturing same|
    US14/989,300| US9768379B2|2015-01-06|2016-01-06|Non volatile resistive memory cell and its method of making|
    [返回顶部]