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    • 专利摘要:
    The invention relates to a two-phase asynchronous transmission circuit for transmitting data on a wired interface (316, 320) according to a two-phase asynchronous protocol, the transmission circuit comprising: N data output lines, where N is an integer greater than or equal to 3, the transmission circuit being capable of transmitting N unique data symbols, each of the output lines being associated with a corresponding one of the N data symbols, and the transmission circuit being adapted to transmit each of the data symbols by applying a voltage transition to the corresponding output line, regardless of the voltage state of the other output lines.
    公开号:FR3031255A1
    申请号:FR1550288
    申请日:2015-01-14
    公开日:2016-07-01
    发明作者:Pontes Julian Hilgemberg；Pascal Vivet
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] TECHNICAL FIELD The present description relates to the field of asynchronous communications, and in particular a two-phase asynchronous transmission circuit, a two-phase asynchronous receive circuit and an asynchronous data link. PRIOR ART The design of a fully synchronous system on a chip becomes a difficult task, particularly for advanced technologies and 3D designs. Indeed, local and global variability causes time constraints to become an overwhelming task. The Globally Synchronous Asynchronous Synchronous (GALS) design style offers a useful alternative over a fully synchronous approach, since it provides improved robustness with respect to local and inter-chip variability. For example, asynchronous communications may be implemented using Nearly Non-Delayed (QDI) protocols, which have the advantage of being almost free of time constraints. In view of its similarities with standard binary signals, the use of four-phase QDI coding is often a preferred choice for communications on a chip. A four-phase asynchronous protocol involves implementing, for each data symbol to be transmitted, a handshake protocol involving four transmission phases.
    [0002] One difficulty is that the use of four-phase asynchronous protocols for off-chip communications and 3D interfaces tends to introduce unacceptable interface delays, and leads to high dynamic power consumption.
    [0003] Two-phase transmission protocols offer an interesting alternative to four-phase protocols for off-chip communications. However, existing two-phase transmission protocols tend to be complex to implement.
    [0004] There is therefore a need in the art for an asynchronous protocol for data communications with relatively low interface delays, low dynamic power consumption, and / or relatively high data throughput. There is also a need for relatively simple and compact circuits for implementing such an asynchronous protocol. SUMMARY An object of embodiments of the present disclosure is to at least partially solve one or more needs of the interior art. In one aspect, a two-phase asynchronous transmit circuit is provided for transmitting data over a wired interface according to a two-phase asynchronous protocol, the transmission circuit comprising: N data output lines, where N is a an integer greater than or equal to 3, the transmission circuit being capable of transmitting N unique data symbols, each of the output lines being associated with the corresponding one of the N data symbols, and the transmission circuit being adapted to transmitting each of the data symbols 3031255 B13783 3 by applying a voltage transition to the corresponding output line, regardless of the voltage state of the other output lines. In another aspect, there is provided a four-phase to two-phase asynchronous protocol converter, comprising: the aforementioned transmission circuit; and N data input lines, each of the input lines being associated with a corresponding one of N data symbols, the transmission circuit being adapted to generate each symbol to be transmitted by detecting a first logic state on the input signal. a corresponding one of the N data input lines. In another aspect, there is provided a four-phase to two-phase asynchronous protocol converter comprising: a transmission circuit comprising: N data output lines, where N is an integer greater than or equal to 2, the circuit of the transmission being capable of transmitting N unique data symbols, each of the output lines being associated with the corresponding one of the N data symbols, and the transmitting circuit being adapted to transmit each of the data symbols by applying a transition voltage at the corresponding output line; and N data input lines, each of the input lines being associated with a corresponding one of the N data symbols, the transmission circuit being adapted to generate each symbol to be transmitted by detecting a first logic state on the a corresponding one of the N data input lines, and the transmission circuit comprising, for each of the N lines of input data, a logic circuit having an input coupled to the corresponding data input line and adapted to generate a transition on its output in response to an active edge of the input data line, the active edge corresponding to either a falling edge or a rising edge. According to one embodiment, each logic circuit comprises a synchronous flip-flop and the input of the logic circuit is a clock input of the synchronous flip-flop coupled to the corresponding input data line; and the output of the synchronous flip-flop is coupled to a data input of the synchronous flip-flop via an inverter, the output of the synchronous flip-flop being connected to one of the output lines.
    [0005] According to one embodiment, the four-phase to two-phase converter further comprises: a two-phase acknowledgment input line for receiving a two-phase acknowledgment signal indicating that a symbol of data was successfully received, the two-phase acknowledgment signal including a voltage transition on the two-phase acknowledgment input line; a four-phase acknowledgment output line for transmitting a four-phase acknowledgment signal indicating that the data symbol has been received successfully; and a four-phase acknowledgment generating circuit adapted to generate the four-phase acknowledgment signal on the basis of the two-phase acknowledgment signal. According to one embodiment, the four-phase acknowledgment signal comprises, in response to the receipt of each data symbol, applying a second voltage state to the acknowledgment output line. in four phases, and in response to receiving a separator by the four-phase to two-phase converter, applying the first voltage state to the four-phase acknowledgment output line, and the circuit of the four-phase acknowledgment generation is adapted to apply the second voltage state to the four-phase acknowledgment output line when an active edge is detected on one of the N data lines of input, and apply the first voltage state to the four-phase acknowledgment output line when a transition is detected on one of the N data output lines and an input line of acknowledgment of receipt at two phases. According to one embodiment, the four-phase acknowledgment generating circuit comprises a first OR EXCLUSIVE gate adapted to apply the EXCLUSIVE OR function to the N data output lines, and a second EXCLUSIVE OR gate having an input coupled to the output of the first EXCLUSIVE OR and another input coupled to the two-phase acknowledgment input line. According to one embodiment, the four-phase acknowledgment generating circuit further comprises a NOR gate having N inputs coupled respectively to the N input lines, and an asymmetric gate C having a first input coupled to a output of the NOR gate and a second input coupled to an output of the second through an inverter, the gate adapted to generate a rising edge on four-phase acknowledgment by mounting on the outputs of the NOR gate to generate a falling edge on the four-phase receive line in response to an output of the NOR gate. In another aspect, there is provided an asymmetric OR-EXCLUSIVE OR gate circuit being the edge-to-edge and inverter-outgoing output line, and asynchronous two-phase asynchronous receive edge-down output output for receiving encoded data according to a two-phase asynchronous protocol, the receiving circuit comprising: N data input lines, where N is an integer greater than or equal to 3, wherein the receiving circuit is capable of receiving N data symbols unique, each of the data input lines being associated with a corresponding one of the N data symbols, and wherein the receiving circuit is adapted to generate each data symbol by detecting a voltage transition on the corresponding one data input lines regardless of the voltage state of the other data input lines. In another aspect, there is provided a two-phase to four-phase asynchronous protocol converter, comprising: the aforementioned receiving circuit; and N data output lines, each of the data output lines being associated with a corresponding one of the N data symbols, the receiving circuit being adapted to transmit each data symbol by applying a first logic state to the corresponding one of the data output lines. According to one embodiment, the two-phase to four-phase converter further comprises a four-phase acknowledgment input line for receiving a four-phase acknowledgment signal indicating that a data symbol has been successfully received, the four-phase acknowledgment signal comprising, in response to the receipt of each data symbol, applying a second logic state to the acknowledgment input line. in four phases, and in response to the transmission of a separator by the receiving circuit, applying a first logic state to the four-phase acknowledgment output line.
    [0006] In another aspect, there is provided a two-to-four phase converter comprising: a receive circuit for receiving data encoded according to a two-phase asynchronous protocol, the receiving circuit comprising: N data input lines, wherein N is an integer greater than or equal to 2, wherein the receiving circuit is capable of receiving N unique data symbols, each of the data input lines being associated with a corresponding one of the N data symbols, and wherein the receiving circuit is adapted to generate each data symbol by detecting a voltage transition on a corresponding one of the data input lines; and N data output lines, each of the data output lines being associated with a corresponding one of the N data symbols, the receiving circuit being adapted to transmit each data symbol by applying a first logic state to the a corresponding data output lines; the receiving circuit comprising, for each data input line: a first asynchronous flip-flop having an input coupled to the data input line; a second asynchronous flip-flop having an input coupled to an output of the first asynchronous flip-flop; and a logic gate coupled to the asynchronous acknowledgment asynchronous acknowledgment are activated by a first four-phase receive and are activated by a second four-phase receive. and at an output of the generate a symbol of the first flip-flops logic state of the signal the second latches logical state of the signal 7 output of the first asynchronous flip-flop second asynchronous flip-flop and adapted to data. According to one embodiment, according to one embodiment, the two-phase to four-phase converter further comprises: a two-phase acknowledgment output line for transmitting a two-phase acknowledgment signal indicating that a data symbol has been received successfully, the two-phase acknowledgment signal comprising a voltage transition on the two-phase acknowledgment output line; and a two-phase acknowledgment generation circuit adapted to generate the two-phase acknowledgment signal by detecting a transition on the output of one of the second asynchronous flip-flops.
    [0007] In another aspect, there is provided a data link comprising: the aforementioned two-phase transmission circuit; the aforementioned two-phase receiver circuit; and a wired interface comprising N lines interconnecting the N output lines of the two-phase transmit circuit with the N 25 input lines of the two-phase receive circuit. According to one embodiment, the wired interface comprises a via 3D. Brief Description of the Drawings The above-mentioned and other features and advantages will become apparent with the following detailed description of embodiments given by way of illustration and not limitation, with reference to the accompanying drawings, in which: FIG. 1 is a 3D view at the system level according to a description mode; Fig. 2 is a sectional view of an interconnection embodiment of the present perspective view schematically illustrating a 3D architecture comprising two integrated circuits stacked description; the figure given according to a description; FIG. 1 an embodiment of the present invention 3 diagrammatically illustrates an embodiment link of the present 4A is a state diagram representing an example of a four-phase asynchronous protocol on two data lines according to an example embodiment; Fig. 4B is a state diagranute showing an exemplary asynchronous protocol encoded by two-phase transitions on two data lines according to an exemplary embodiment; Figure 5A schematically illustrates a four-phase to two-phase asynchronous protocol converter according to an exemplary embodiment of the present disclosure; FIG. 5B schematically illustrates a two-phase to four-phase asynchronous protocol converter according to an exemplary embodiment of the present description; Fig. 6A is a table showing a four-phase asynchronous protocol using four data lines according to an exemplary embodiment of the present disclosure; Fig. 6B is a table showing a two-phase asynchronous protocol using four data lines according to an exemplary embodiment of the present description; Figure 7A schematically illustrates an asynchronous four-phase to two-phase protocol converter according to an exemplary embodiment of the present disclosure. Fig. 7B is a timing chart showing signals in the converter of Fig. 7A according to an exemplary embodiment; FIG. 8A schematically illustrates a two-phase to four-phase asynchronous protocol converter according to an exemplary embodiment of the present disclosure; and Fig. 8B is a timing chart showing signals in the converter of Fig. 8A according to an exemplary embodiment. DETAILED DESCRIPTION Fig. 1 is a sectional view schematically illustrating a system level 3D interconnection using 3D technology. In the example of FIG. 1, there are three integrated circuits 102, 104 and 106 interconnected by a silicon interposer 108. Each of the integrated circuits 102 to 106 may use different voltage levels and / or different operating frequencies and it can be designed with different technologies. The integrated circuits 102 to 106 are for example coupled to the silicon interposer 108 by micro-pads 110. The interposer 108 comprises for example an interconnection level 111 and a silicon layer 112 through which one or more vias Silicon vias (Through Silicon Vias - TSV) 114 are formed. Each of the TSVs 114 is connected to a corresponding flip chip lug 116, which is itself connected to a box substrate 118. The box substrate 118 is, for example, furthermore coupled by balls 120 of a BGA (bail grid array - array of beads) to a motherboard 25 or the like. The micro-pads 110, the TSV 114 and the flip-chip pads 116 of the interposer 108 provide 3D interfaces between the integrated circuits 102, 104 and 106 and / or with other circuits. However, there is a difficulty in that these elements introduce propagation delays. Further, the interposer 108 may comprise test logic and / or micro-buffer cells (not shown in FIG. 1) including buffers, ESD circuitry and / or This further adds propagation delays to the signals transmitted to or from the integrated circuits 102, 104, 106. FIG. 2 illustrates an exemplary 3D circuit design comprising an integrated circuit 202 superimposed on An integrated circuit 204. Each of the integrated circuits 202, 204 comprises, for example, a network on chip (NoC) comprising an interconnection bus gate 206, with a router 208 at each point of intersection between the buses 206. Each router 208 is for example coupled to a corresponding processing device 210 provided on each integrated circuit 202, 204. At least some of the interconnection routers 208 of the integrated circuit 202 are coupled, by the 3D interoperability intermediary 212, comprising, for example, TSVs, to interconnection routers 208 of the integrated circuit 204.
    [0008] Here again, the 3D interfaces 212 of the embodiment of FIG. 2 introduce, for example, propagation delays. Therefore, although at least some of the bus-on-chip communications 206 of each integrated circuit 202 204 may be realized using a four-phase asynchronous protocol, the use of such a protocol on the 3D interfaces 212 is likely to lead to unacceptable propagation delays and thus low data throughput and high dynamic power consumption.
    [0009] FIG. 3 schematically illustrates a data link 300 which is for example used for communications between the interposer 108 and the integrated circuits 102, 104 and 106 in FIG. 1, and / or between the integrated circuits 202 or 204 of FIG. 2.
    [0010] The data link 300 includes circuits 302 and 304 which communicate with each other using an asynchronous two-phase transient coding protocol. The circuit 302 includes, for example, a protocol conversion circuit 306 coupled to input lines 308 for receiving data symbols transmitted according to a four-phase asynchronous protocol. For example, although not shown in FIG. 3, the signals on the input lines 308 are provided by another transmission interface that uses the four-phase asynchronous protocol. Circuit 306 includes a four-phase to two-phase asynchronous protocol converter 310 having inputs coupled to lines 308 and providing, on output lines 312, data symbols encoded according to a two-phase asynchronous protocol. The lines 312 are for example coupled via an interface circuit 314, comprising for example buffers, ESD protection circuits and / or level shifters, to a wired interface 316. The interface Wired 316 includes, for example, a 3D interface, such as a TSV, or another type of 2D or 3D connection. The circuit 302 also receives on lines 318 data symbols transmitted according to the two-phase asynchronous protocol. The lines 318 are for example coupled to another wired interface 320 between the circuits 302 and 304 via another interface circuit 322. The lines 318 are supplied to a two-phase to four-phase asynchronous protocol converter. 324, which provides, on output lines 326, data symbols encoded according to the four-phase asynchronous protocol. For example, the output lines 326 are coupled to another transmission interface that uses the four-phase asynchronous protocol. The circuit 304 comprises for example the same elements as the circuit 302, which are noted with the same numerical references and which will not be described again in detail. However, the converter 310 in the circuit 304 has its output lines 312 coupled to the wired interface 320, for example via the 3D interface circuit 314, and the converter 324 in the circuit 304 has its input lines 318 coupled to the wired interface 316, for example via the 3D interface circuit 322. FIG. 4A is a state diagram illustrating an example of a four-phase asynchronous protocol based on FIG. on two lines of data, which we will call AO and Al, and a single acknowledgment wire. There are three states, a state 00 in which the two lines AO and Al are at a low logic level, a state 01 in which the line A1 is at the logic low level and the line AO is at the logic high level, and a state 10 in which the Al line is at the logic high level and the AO line is at the logic low level. From the initial state 00, in a first phase, a binary "0" is transmitted by changing to the state 01, in other words by bringing the line AO to a logic high level, or a "1" Binary is transmitted to state 10, in other words by bringing line Al to a logic high level. In a second phase, an acknowledgment signal ACK is received, which in a third phase causes a return to state 00, bringing the two lines A0 and A1 to a logic low level. This corresponds to a separator separating the transmission of consecutive data symbols. In the fourth phase, another acknowledgment signal ACK is received, which means that a new data symbol can be transmitted.
    [0011] Thus, according to the four-phase asynchronous protocol, the data is encoded in a manner that is very similar to standard binary signals. Each line is associated with one of the data symbols, in this example a "0" and a "1". A logical high state on each line is used to represent each data symbol. FIG. 4B is a state diagram illustrating an example of a two-phase asynchronous protocol, which will be referred to herein as two-phase transient encoding asynchronous protocol. The example of Figure 4B is based on two lines of data, which will again be called AO and A1, and a single acknowledgment wire. There are four states, a state 00 in which the two lines AO and Al are at a low logic level, a state 01 in which the line A1 is at a low logic level and the line AO is at a logic high level, a state 10 in which the line A1 is at a logic high level and the line AO is at a low logic level, and a state 11 in which the two lines are at a logic high level. From an initial state, the data symbol "0" is encoded by a voltage transition on the line A0, and the data symbol "1" is encoded by a voltage transition on the line A1, independently of the state of the other line. As used herein, the term voltage transition refers to a transition from a low logic level to a high logic level or from a high logic level to a low logic level. Thus, starting in state 00, in a first phase, a binary "0" is transmitted by changing to state 01, in other words by bringing the line AO to a logic high level, or a "1". Binary is transmitted to state 10, in other words by bringing line A1 to a logic high level. In a second phase, an acknowledgment signal ACK is received. A new data symbol can then be transmitted. For example, from state 01, a binary "1" is transmitted to state 11, in other words by bringing line Al 25 to a logic high level, or a binary "0" is transmitted back to state 00, in other words by bringing the line AO to a logic low level. From state 11, a binary "1" is transmitted to state 01, in other words by bringing the line A1 to a logic low, or a binary "0" is transmitted 30 by passing in the state 10, in other words by bringing the line AO to a logic low level. From state 10, a binary "1" is transmitted to state 00, in other words by bringing the line A1 to a low logic level, or a binary "0" is transmitted by passing to state 11, in other words by bringing line AO to a logic high level.
    [0012] Thus, the two-phase asynchronous protocol is similar to the four-phase asynchronous protocol, in that each line is once again associated with one of the data symbols. However, the data symbol is selected by a transition rather than a logical high level on a given line. FIG. 5A schematically illustrates the inputs and outputs of the four-phase to two-phase converter 310 of FIG. 3 in more detail according to an example in which the input lines 308 comprise four data lines referenced A0, A1, A2 and A3 and an acknowledgment line ACK, and the output lines 312 comprise four data lines referenced to AO ', A1', A2 ', and A3', and an acknowledgment line ACK '.
    [0013] Figure 5B schematically illustrates the inputs and outputs of the two-phase to four-phase converter 324 of Figure 3 in more detail according to an example in which the input lines 318 comprise four data lines referenced AO ', A1', A2. and A3 'and a reception acknowledgment line ACK', and the output lines 326 comprise four data lines referenced A0, A1, A2, and A3, and an acknowledgment line ACK. Figure 6A is a table showing the four-phase asynchronous protocol of Figure 4A adapted for the four data lines A0, A1, A2 and A3 of Figures 5A and 5B. There are, for example, four unique data symbols denoted "0", "1", "2", "3", which respectively correspond for example to the binary values 00, 01, 10 and 11. Each symbol "0" to " 3 "is associated with a corresponding one of the lines A0 to A3, so that a logical high level on a given line transmits the corresponding data symbol. Fig. 6B is a table showing the two-phase asynchronous protocol of Fig. 4B adapted to the four data lines AO ', A1', A2 ', and A3' of Figs. 5A and 5B.
    [0014] Each symbol "0" to "3" is associated with a corresponding one of the lines AO 'to A3' so that a voltage transition on a given line transmits the corresponding data symbol, independently of the state of tension of the other lines. Although the examples of FIGS. 5A, 5B, 6A and 6B involve four data lines for four-phase signals and for two-phase signals, in other embodiments there could be N data lines used for transmit the data symbols of each protocol, where N is for example an integer greater than or equal to 2, and in some embodiments is an integer greater than or equal to 3. Figure 7A schematically illustrates the converter from four phases to two phases 310 of Figure 5A in more detail according to an exemplary embodiment.
    [0015] The data line AO receives a 4ph data signal 0 and is coupled to a clock input of a synchronous flip-flop 702. The synchronous flip-flop 702 has its Q output 704 coupled to the data line AO 'of the two-phase protocol . The output 704 is also coupled, through an inverter 706, to the data input of the synchronous flip-flop 702. The data line A1 receives a 4ph data signal l and is coupled to a clock input. synchronous flip-flop 708. Synchronous flip-flop 708 has its input Q 710 coupled to data line A1 'of the two-phase protocol. The output 710 is also coupled, via an inverter 712, to the data input of the synchronous flip-flop 708. The data line A2 receives a 4ph_data_2 signal and is coupled to a clock input of synchronous flip-flop 714. Synchronous flip-flop 714 has its output Q716 coupled to data line A2 'of the two-phase protocol. The output 716 is also coupled, via an inverter 718, to the data input of the synchronous flip-flop 714. The data line A3 receives a 4ph data signal _3 and is coupled to a clock input d a synchronous flip-flop 720.
    [0016] Synchronous flip-flop 720 has its output Q 722 coupled to data line A3 'of the two-phase protocol. The output 722 is also coupled, through an inverter 724, to the data input of the synchronous flip-flop 720. The converter 310 also includes a four-phase acknowledgment generation circuit 726, which provides the 4ph ack out acknowledgment signal to the four-phase side on the ACK line, and receives a 2ph_ack_in acknowledgment signal from the two-phase side on the ACK 'line. The circuit 726 generates the acknowledgment signal 4ph_ack out on the basis of the 4ph data signals O to 4ph_data_3 present on the lines AO to A3 and on the basis of the signals 2phdat__0 to 2ph_data_3 present on the lines A0 'to A3'. For example, the data lines AO-A3 are coupled to corresponding inputs of a four-input NOR gate 728, which has its output coupled to an input of an asymmetric gate 730, also known as circuit or gate of Müller. The lines A0 'to A3' are for example coupled to corresponding inputs of a four-input EXCLUSIVE OR gate 732, the output of which is coupled to one of two inputs of an EXCLUSIVE OR gate 734. The other Gate 734 input is coupled to the ACK line. The output of the EXCLUSIVE OR gate 734 is coupled through an inverter 736 to the second input of the asymmetric gate 730. The EXCLUSIVE OR gate described herein with two or more inputs 25 has the function of generating a voltage transition on their output in response to detecting a voltage transition on any of their inputs. Asymmetric door C 730 for example has an asymmetrical descent. For example, it has the following truth table for the input A from the NOR gate 728, the input B from the inverter 736, and the output Z, Zn_1 meaning that the output of the gate C remains unchanged: 3031255 B13783 17 ABZ 1 1 1 1 0 Zn-1 0 1 0 0 0 0 It is assumed that the 4phdata signals 1 to 4phdata3 are initially low and that the input A of the asymmetric gate C is initially at logic level 1. It is also assumed that the 2ph_ack_in signal is initially low. In addition, the Q output of each synchronous flip-flop 702, 708, 714 and 720 is initially low, for example by the activation of a reset signal (not shown in FIG. 7A) supplied to the synchronous flip-flops. Thus, the output of the EXCLUSIVE OR gate 732 is initially low and the B input of the asymmetric gate C is initially high. In addition, the output signal 4ph_ack_out of the gate C 730 is thus initially high (A and B becoming high). The means for initializing the circuit are not shown in the figures, but will be readily conceived by those skilled in the art. Thus the output of the gate C 730, which is initially at a logic high value, will be brought to a low logical level if one of the lines AO to A3 goes to a logic high level. The output of the gate C will then be brought back to the high state if all the lines A0 to A3 are at a low logic level and if the input B returns to a high level in response to a transition if one goes describe it below. The operation to be described further producing on line ACK 'as the circuit of FIG. 7A goes into detail with reference to the timing diagram of FIG. 7B for an example in which the data symbol "0" is transmitted. It will be apparent to those skilled in the art that the operation will be similar for the transmission of the other data symbols.
    [0017] Figure 7B illustrates the 4phdata_0 and 4phackout signals of the four-phase protocol, and the 2phdata0 and 2ph_ack_in signals of the two-phase protocol. The sequence is started by a rising edge 740 of the 4ph data signal 0. Thus the synchronous flip-flop 702 will be triggered by this rising edge, triggering a transition 742 of the 2ph data signal O on the data line A0 '. The transition on the data line A0 causes the output of the NOR gate 728 to go low, thereby bringing the output of the gate C 730 low as represented by a falling edge 744. of the 4ph_ack_out signal. In addition, the data transition 742 will also, some time after, cause a transition 746 in the acknowledgment signal 2ph_ack_in on the line ACK ', which will cause a transition on the input B of the gate C 730, which will become high again. In addition, the falling edge 744 of the acknowledgment signal 4ph_ack out will cause the transmitter circuit to bring the 4ph data signal 0 low, as represented by a falling edge 748. This corresponds to a separator transmitted on the data lines AO to A3, which causes the output of the NOR gate 728 to go high. The combination of these events will cause the two inputs of gate C 730 to go high, thereby causing the acknowledgment signal 4phackout to go high, as represented by a front. amount 750. The circuit is then ready to receive a next data symbol. Figure 8A schematically illustrates the two-phase to four-phase converter 324 of Figure 5B in more detail according to an exemplary embodiment. The data line AO 'receives a 2ph data signal _0 and is coupled to a data input of an asynchronous latch 802. The output 804 of the asynchronous flip-flop 802 is coupled to a data input of another asynchronous flip-flop 3031255 B13783 19 806, which has its output 808 coupled to an input of an EXCLUSIVE OR gate with two inputs 810. The other input of the EXCLUSIVE OR gate 810 is coupled to the output 804 of the asynchronous flip-flop 802. EXCLUSIVE OR gate output 810 is coupled to the four-phase protocol AO data line. The data line Al 'receives a signal 2ph_data_1 and is coupled to a data input of an asynchronous flip-flop 812. The output 814 of the asynchronous flip-flop 812 is coupled to a data input of another asynchronous flip-flop 816, which has Its output 818 coupled to an input of an EXCLUSIVE OR gate with two inputs 820. The other input of the EXCLUSIVE OR gate 820 is coupled to the output 814 of the asynchronous flip-flop 812. The output of the EXCLUSIVE OR gate 820 is coupled to the Al data line of the four-phase protocol.
    [0018] The data line A2 'receives a 2ph_data_2 signal and is coupled to a data input of an asynchronous flip-flop 822. The output 824 of the asynchronous flip-flop 822 is coupled to a data input of another asynchronous flip-flop 826, which at its output 828 coupled to an input of a two-input EXCLUSIVE OR gate 830. The other input of the EXCLUSIVE OR gate 830 is coupled to the output 824 of an asynchronous flip-flop 822. The output of the EXCLUSIVE OR gate 830 is coupled to the data line A2 of the four-phase protocol. The data line A3 'receives a signal 2ph_data_3 and is coupled to a data input of an asynchronous flip-flop 832. The output 834 of the asynchronous flip-flop 832 is coupled to a data input of another asynchronous flip-flop 836, which at its output 838 coupled to an input of an EXCLUSIVE OR gate with two inputs 840. The other input of the EXCLUSIVE OR gate 840 is coupled to the output 834 of the asynchronous flip-flop 832. The output of the EXCLUSIVE OR gate 840 is coupled to the A3 data line of the four-phase protocol. In the converter 324, the acknowledgment signal 2ph_ack_out on the line ACK 'is generated by an EXCLUSIVE OR gate 842 having four inputs respectively coupled to the outputs 808, 818, 828 and 838 of the asynchronous flip-flops 806, 816. In addition, the acknowledgment signal 4ph ack in provided by the four-phase protocol on the ACK line is coupled to an activation input of each of the asynchronous latches 802, 812, 822 and 832 , each being activated by a logic high value of this signal, and an activation input of each of the asynchronous latches 806, 816, 826 and 836, each being activated by a low logic value of this signal. Thus, the two asynchronous flip-flops associated with each data line are arranged in a master-slave configuration in which data will be locked by the first asynchronous flip-flop when the 4ph_ack_in signal is high, and then locked by the second asynchronous flip-flop when the 4ph_ack_in signal. is low.
    [0019] The operation of the circuit of Fig. 8A will now be described in more detail with reference to Fig. 8B for an example in which the data symbol "0" is transmitted. It will be apparent to those skilled in the art that the operation will be similar for the transmission of the other data symbols. FIG. 8B is a timing diagram illustrating the 2ph data 0 and 2ph_ ack out signals of the two-phase protocol, and the 4ph data _0 and 4ph ack_in signals of the four-phase protocol. Initially, the acknowledgment signal 4ph_ ack in is at a logic high level, so that the asynchronous latches 802, 812, 822, and 832 are enabled, while the asynchronous latches 806, 816, 826, and 836 maintain, on their outputs, their previous state. The sequence is initiated by a transition 850 of the signal of 2ph data 0. This causes a transition on the output 804 of the asynchronous flip-flop 802, triggering, shortly thereafter, a rising edge 852 of the 4ph data signal 0. this data symbol has been received on the four-phase side, the acknowledgment signal 4phackin will be brought to the low state, as represented by a falling edge 854. This will cause the activation of the asynchronous flip-flops 806, 816, 826 and 836 while the input stages 802, 812, 822 and 832 are deactivated, so that the output of the asynchronous flip-flop 806 will be equal to its input, and the output of the EXCLUSIVE OR gate 810 will go low, as represented by a falling edge 856 of the 4ph_data_0 signal. In addition, the transition on the output of the asynchronous latches 808 will cause a transition of the 2ph_ack_out signal on the output of the EXCLUSIVE OR gate 842, referenced 858. In addition, the falling edge 856 of the 4ph data signal 0 will cause a certain time later, the transition back to the high state of the acknowledgment signal 4ph_ack in, as represented by a rising edge 860, thereby again activating the asynchronous latches 802, 812, 822 and 832, to be ready to receive a next data symbol. An advantage of the asynchronous two-phase transition coding protocol described herein, with a number of N data lines advantageously equal to 3 or more, is that it provides a relatively high throughput and a relatively low dynamic power consumption per second. compared to a four-phase asynchronous protocol. Another advantage is that by using such an asynchronous protocol for communications between integrated circuits, the problem of synchronization between the circuits will be considerably reduced. In addition, an advantage of the circuitry of Figs. 7A and 8A for conversion between two-phase and four-phase protocols is that these circuits are compact with relatively few gates and thus relatively low power consumption. With the description thus made of at least one illustrative embodiment, various alterations, modifications and improvements will be apparent to those skilled in the art. For example, although in Figs. 7A and 8A there have been described embodiments in which there are four lines of data, how these circuits could be adapted to any number of data lines and to a number of data lines. 22 corresponding data symbols will be apparent to those skilled in the art. Furthermore, it will be apparent to one skilled in the art that the application of the two-phase asynchronous protocol to a 3D interface is merely an example, and that it could be applied to a wide range of interfaces for which delay of propagation is relative high.
    权利要求:
    Claims (15)
    [0001]
    REVENDICATIONS1. A two-phase asynchronous transmit circuit for transmitting data on a wired interface (316, 320) according to a two-phase asynchronous protocol, the transmission circuit comprising: N data output lines (A0 'to A3'), where N is an integer greater than or equal to 3, the transmission circuit being capable of transmitting N unique data symbols ("0" to 11 311 each of the output lines being associated with a corresponding one of the N data symbols , and the transmitting circuit being adapted to transmit each of the data symbols by applying a voltage transition to the corresponding output line, regardless of the voltage state of the other output lines.
    [0002]
    An asynchronous four-phase to two-phase protocol converter comprising: the transmitting circuit of claim 1; and N data input lines (A0 to A3), each of the input lines being associated with a corresponding one of N data symbols ("0" to "3"), the transmission circuit being adapted to generating each symbol to be transmitted by detecting a first logic state on a corresponding one of the N data input lines.
    [0003]
    The four-phase to two-phase converter according to claim 2, wherein the transmitting circuit comprises, for each of the N lines of input data, a logic circuit (702, 708, 714, 720) having a coupled input at the corresponding data input line and adapted to generate a transition on its output in response to an active edge of the input data line, the active edge corresponding to either a falling edge or a rising edge.
    [0004]
    The four-phase to two-phase converter according to claim 3, wherein each logic circuit comprises a synchronous flip-flop (702, 708, 714, 720), and wherein said input of the logic circuit is a clock input. the synchronous flip-flop coupled to the corresponding input data line; and the output of the synchronous flip-flop is coupled to a data input of the synchronous flip-flop via an inverter (706, 712, 718, 724), the output of the synchronous flip-flop being connected to one of the exit lines.
    [0005]
    The four-phase to two-phase converter according to any one of claims 2 to 4, further comprises a two-phase acknowledgment input (ACK ') line for receiving an acknowledgment signal. two-phase signal indicating that a data symbol has been successfully received, the two-phase acknowledgment signal comprising a voltage transition on the two-phase acknowledgment input line (ACK ') ; a four-phase acknowledgment (ACK) output line for issuing a four-phase acknowledgment signal indicating that the data symbol has been successfully received; and a four-phase acknowledgment generating circuit (726) adapted to generate the four-phase acknowledgment signal on the basis of the two-phase acknowledgment signal. 25
    [0006]
    The four-phase to two-phase converter according to claim 5 in its dependence on claim 3, wherein the four-phase acknowledgment signal comprises, in response to the receipt of each data symbol, the application of a second voltage state on the four-phase acknowledgment output (ACK) line, and in response to the receipt of a separator by the four-phase to two-phase converter, the application of the first state in the four-phase acknowledgment output (ACK) output line, and wherein the four-phase acknowledgment generation circuit (726) is adapted to apply the second voltage state on the four-phase acknowledgment (ACK) output line when an active edge is detected on one of the N input data lines, and applying the first voltage state on the output line 5 acknowledgment of receipt at four phases when a transition is detected on one of the N data output lines and on the two-phase acknowledgment input line (ACK ').
    [0007]
    The four-phase to two-phase converter according to claim 5 or 6, wherein the four-phase acknowledgment generating circuit (726) comprises a first EXCLUSIVE OR gate (732) adapted to apply the EXCLUSIVE OR function. at the N data output lines and a second EXCLUSIVE OR gate (734) having an input coupled to the output of the first EXCLUSIVE OR gate (732) and another input coupled to the acknowledgment input line at two phases (ACK ').
    [0008]
    The four-phase to two-phase converter according to claim 7, wherein the four-phase acknowledgment generating circuit (726) further comprises a NOR gate (728) having N inputs coupled to the N lines, respectively. input, and an asymmetric gate C (730) having a first input coupled to an output of the NOR gate (728) and a second input coupled to an output of the second EXCLUSIVE OR gate (734) via an inverter 25 (736), wherein the asymmetric gate 730 is adapted to generate a rising edge on the four-phase acknowledgment output (ACK) line in response to rising edges on the outputs of the gate NO OR (728) and the inverter (736), and generating a falling edge on the four-phase acknowledgment output (ACK) line in response to a falling edge on the output of the NO gate OR (728).
    [0009]
    9. A two-phase asynchronous receive circuit for receiving data encoded according to a two-phase asynchronous protocol, the receiving circuit comprising: N data input lines (A0 'to A3'), where N is a an integer greater than or equal to 3, wherein the receiving circuit is capable of receiving N unique data symbols, each of the data input lines being associated with the corresponding one of the N data symbols, and wherein the circuit The receiver is adapted to generate each data symbol by detecting a voltage transition on a corresponding one of the data input lines regardless of the voltage state of the other data input lines. 10
    [0010]
    A two-phase to four-phase asynchronous protocol converter, comprising: the receiving circuit of claim 9; and N data output lines (A0 to A3), each of the data output lines being associated with a corresponding one of the N data symbols, the receiving circuit being adapted to transmit each data symbol by applying a first logical state on a corresponding one of the data output lines.
    [0011]
    The two-phase to four-phase asynchronous protocol converter of claim 10, further comprising a four-phase acknowledgment (ACK) input line for receiving a four-phase acknowledgment signal indicating that the data symbol has been successfully received, wherein the four-phase acknowledgment signal comprises, in response to the receipt of each data symbol, applying a second logic state to the d-line. 4-phase acknowledgment (ACK) input, and in response to the transmission of a separator by the receiving circuit, applying a first logic state to the acknowledgment output line four-phase (ACK).
    [0012]
    The two-phase to four-phase converter according to claim 10 or 11, comprising for each data input line: a first asynchronous flip-flop (802, 812, 822, 832) having an input coupled to the input line of data ; A second asynchronous flip-flop (806, 816, 826, 836) having an input coupled to an output of the first asynchronous flip-flop; a logic gate (810, 820, 830, 840) coupled to the output of the first asynchronous flip-flop and to an output of the second asynchronous flip-flop and adapted to generate a data symbol, the first asynchronous flip-flops being activated by a first state The logic of the four-phase acknowledgment signal and the second asynchronous flip-flops are activated by a second logic state of the four-phase acknowledgment signal.
    [0013]
    The two-phase to four-phase converter according to claim 12, further comprising: a two-phase acknowledgment output line (ACK ') for transmitting a two-phase acknowledgment signal indicating that a data symbol has been received successfully, the two-phase acknowledgment signal comprising a voltage transition on the two-phase acknowledgment output line (ACK '); and a two-phase acknowledgment generating circuit (842) adapted to generate the two-phase acknowledgment signal by detecting a transition on the output of one of the second asynchronous flip-flops.
    [0014]
    A data link comprising: the two-phase transmission circuit of claim 1; the two-phase receiver circuit of claim 9; and a wired interface (316, 320) comprising N lines interconnecting the N output lines of the two-phase transmit circuit with the N input lines of the two-phase receive circuit.
    [0015]
    The data transmission link of claim 14, wherein the wired interface (316,320) comprises a 3D via (114,212).
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    同族专利:
    公开号 | 公开日
    FR3031254A1|2016-07-01|
    US20160188522A1|2016-06-30|
    FR3031255B1|2018-04-27|
    US9921992B2|2018-03-20|
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1463384A|FR3031254A1|2014-12-29|2014-12-29|
    FR1463384|2014-12-29|EP15202821.3A| EP3041143B1|2014-12-29|2015-12-28|Asynchronous data link|
    US14/981,478| US9921992B2|2014-12-29|2015-12-28|Asynchronous data link|
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