• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates to a high-resistivity semiconductor semiconductor substrate comprising: - a trapping layer (30); a dielectric layer (40) disposed on the trapping layer (30); a semiconductor layer (50) disposed on the dielectric layer (40); the substrate being characterized in that the trapping layer (30) comprises a defect density greater than a predetermined defect density, the predetermined defect density is the defect density beyond which the electrical resistivity of the trapping layer (30) is essentially temperature independent.
    公开号:FR3029682A1
    申请号:FR1402801
    申请日:2014-12-04
    公开日:2016-06-10
    发明作者:Oleg Konochuk；Didier Landru；Christophe Figuet
    申请人:Soitec SA；
    IPC主号:
    专利说明:

    [0001] FIELD OF THE INVENTION The present invention relates to a high-resistivity semiconductor substrate and its method of manufacture. BACKGROUND OF THE INVENTION A high resistivity semiconductor substrate 1 known from the state of the art, and illustrated in FIG. 1, comprises: a support substrate 2; a trapping layer 3 disposed on the support substrate 2; a dielectric layer 4 disposed on the trapping layer 3; a semiconductor layer 5 disposed on the dielectric layer 4. The support substrate 2 may have a resistivity of the order of 1 kOhm.cm, see 3 kOhm.cm. The trapping layer 3 may comprise undoped polycrystalline silicon.
    [0002] Such substrates are particularly useful for the manufacture of radio frequency (RF) devices such as antenna switches, power amplifiers, switches. Indeed, it is known to those skilled in the art that the performances of the RF devices are degraded by the insertion losses, the crosstalk between neighboring devices ("cross talk" according to the English terminology), as well as the harmonics of second generation. The combination of a support substrate 2 having a resistivity of the order of 1 kOhm.cm and a trapping layer 3 according to the state of the art reduces the performance degradation of the RF devices.
    [0003] In this respect, those skilled in the art will find a review of the performance of the RF devices manufactured on the high-resistivity semiconductor substrate known from the state of the art in "Silicon-on-insulator (SOI) Technology, Manufacture and Applications". , points 10.7 and 10.8, Oleg Kononchuk and Bich-Yen Nguyen, Woodhead Publishing.
    [0004] RF devices have features that are governed not only by their architecture, but also by the capacity of the semiconductor high resistivity substrate on which they are manufactured to attenuate insertion losses, crosstalk between neighboring devices, and the second generation harmonics. Various tests exist to determine the ability of a high-resistivity semi-conductor substrate to mitigate performance degradation of RF devices. The method of coplanar waveguides ("CPW") is generally used to evaluate the attenuation of second-generation harmonics. C. Roda Neve et al., "Impact of neutron irradiation on the RF properties of oxidized high-resistivity silicon substrates with and without a rich passivation layer", Microelectronic Reliability, 50 (2011), 326-331. RODA], describes the technical and geometric characteristics of CPW generally used for such characterizations. Thus, such CPWs applied to the high-resistivity semiconductor substrates known from the state of the art show that for an input signal with a power of -15 dBm, second-generation harmonics with a power of -80 dBm are produced at room temperature, ie 20 ° C. Moreover, the same method at a temperature of 125 ° C. produces second-generation harmonics with a power of -70 dBm. However, these high resistivity semiconductor substrates are unsatisfactory. Indeed, the RF devices are capable of producing a heating of the high-resistivity semiconductor substrate on which they are manufactured, and the performance degradation associated with said heating is excessive. In addition, new RF devices developed for 4G (or LTE) also require the provision of high resistivity semiconductor substrates with higher attenuation of second generation harmonics.
    [0005] Indeed, it is now necessary to obtain a performance of -100 dBm for the second generation harmonics according to the planar waveguide method, not only at 20 ° C but also up to 125 ° C.
    [0006] In particular, the high-resistivity semiconductor substrate known from the state of the art is today, and comprising from its rear face towards its front face, a silicon substrate with a resistivity equal to 5 kOhm.cm, a layer 2 micron thick polycrystalline silicon, a 2000A thick silicon dioxide layer, and a 700A thick silicon layer do not have the characteristics necessary to appreciably mitigate the degradation of RF devices designed for 4G. A solution to improve the performance of the RF devices would then be to use a support substrate 2 in silicon of very high resistivity, typically 20 kOhm.cm. However, such support substrates are not commercially available. An object of the invention is to design a high resistivity semiconductor substrate to limit the degradation of the performance of RF devices in case of heating of said devices.
    [0007] Another object of the invention is also to provide a high resistivity semiconductor substrate for manufacturing RF devices developed for 4G. BRIEF DESCRIPTION OF THE INVENTION The present invention aims at solving in whole or in part the problems above and comprises a high resistivity semiconductor substrate comprising: a trapping layer; a dielectric layer disposed on the trapping layer; A semiconductor layer disposed on the dielectric layer; The substrate being remarkable in that the trapping layer comprises a defect density greater than a predetermined defect density, the predetermined defect density is the defect density beyond which the electrical resistivity of the trapping layer is 5 essentially temperature independent. The resistivity of the trapping layer is essentially temperature independent and is understood to mean the electrical resistivity having a variation of less than 10% as a function of temperature. Thus, such a substrate makes it possible to limit the degradation of the performance of RF devices in the event of heating of said devices. Indeed, since the electrical resistivity of the trapping layer is essentially independent of temperature, the RF devices that are manufactured on the high-resistivity semiconductor substrates will not suffer degradation of their performance in case of heating.
    [0008] According to one embodiment, the trapping layer has a resistivity at 20 ° C. of greater than 5 kOhm.cm, preferably greater than 10 kOhm.cm. Thus, it is possible to manufacture high resistivity semiconductor substrates compatible with RF devices designed for 4G.
    [0009] Indeed, the resistivity greater than 5 kOhm.cm of the trapping layer makes it possible to attenuate the second-generation harmonics at -100 dBm (according to the geometric characteristics of [RODA] CPWs) as required for the RF devices designed. for 4G. Furthermore, it is not necessary, unlike the high-resistivity semiconductor substrates known from the prior art, to use a support substrate having a high resistivity. According to one embodiment, the difference in coefficient of thermal expansion of the trapping layer and the support substrate is less than 5 ppm / K between 100 ° C and 1200 ° C.
    [0010] Thus, a difference in thermal expansion coefficient of the trapping layer and the support substrate of less than 5 ppm / K between 100 ° C and 3029682 at 1200 ° C makes it possible to manufacture RF devices according to manufacturing methods involving annealing. heat up to 1200 ° C. By ppm, we mean parts per million. According to one embodiment, the trapping layer comprises microstructures of size less than 20 nm, preferably less than 10 nm. By microstructures is meant crystallites in polycrystalline materials or porous materials. In crystalline materials, crystallites are also called grains.
    [0011] Thus, microstructures smaller than 20 nm, preferably less than 10 nm, give the trapping layer a resistivity greater than 5 kOhm.cm. According to one embodiment, the trapping layer comprises a porous or polycrystalline material.
    [0012] According to one embodiment, the trapping layer comprises porous silicon. According to one embodiment, the trapping layer comprises polycrystalline silicon comprising 1 to 20% of carbon. Thus, the carbon atoms included in the polycrystalline silicon layer accumulate at the grain boundaries. Said accumulation of carbon atoms at the grain boundaries block both the reorganization and the growth of the polycrystalline silicon gains that may occur during a possible thermal annealing including a rise in temperature. The electrical resistivity of the trapping layer will then be unchanged. According to one embodiment, the thickness of the trapping layer is between 10 and 50 μm, preferably between 20 and 30 μm. Thus, with such thicknesses of the trapping layer, the support substrate has little, if any, effect on the damping of the second generation harmonics. It is thus possible to use a support substrate 3029682 6 having an average resistivity, for example a resistivity of less than 1 kOhm.cm. In addition, since the difference in thermal expansion coefficient of the trapping layer and the support substrate is less than 5 ppm / K between 100 ° C. and 1200 ° C., such large thicknesses of the trapping layer will not generate excessive deformation of the high-resistivity semiconductor substrate during thermal annealing including a rise in temperature. The integrity of the high-resistance semiconductor substrate will thus be guaranteed during the manufacture of the RF devices.
    [0013] According to one embodiment, the support substrate comprises at least one of the materials selected from the following group: silicon, silicon carbide, silicon germanium. According to one embodiment, the resistivity of the support substrate is between 10 and 2000 Ohm.cm.
    [0014] According to one embodiment, the semiconductor layer comprises at least one of the materials selected from the following group: silicon, silicon carbide, silicon germanium. According to one embodiment, the thickness of the semiconductor layer is between 10 nm and 1 μm.
    [0015] According to one embodiment, the dielectric layer comprises at least one of the materials selected from the following group: silicon dioxide, silicon nitride, aluminum oxide. According to one embodiment, the dielectric layer is between 10 nm and 1 μm.
    [0016] The invention also relates to a method for manufacturing a high-resistivity semiconductor substrate, comprising, from its rear face to its front face, a support substrate, a trapping layer, a dielectric layer, and a semiconductor layer. -conductor, said method comprising the steps of: a. providing a semiconductor substrate; b. provide a support substrate; 3029682 7 c. forming a trapping layer on the support substrate; d. forming a dielectric layer; e. forming an embrittlement zone in the semiconductor substrate, the weakening zone delimiting a semiconductor layer from the rest of the semiconductor substrate; f. assembling the semiconductor substrate and the support substrate; boy Wut. fracturing the semiconductor substrate along the embrittlement zone so as to transfer the semiconductor layer onto the support substrate; The method being characterized in that the trapping layer comprises a defect density greater than a predetermined defect density, the predetermined defect density is the defect density above which the electrical resistivity of the trapping layer is essentially independent of the temperature.
    [0017] By resistivity of the trapping layer is essentially temperature independent, the electrical resistivity is understood to have a variation of less than 10% as a function of temperature. Thus, such a substrate makes it possible to limit the degradation of the performance of the RF devices in the event of heating of said devices.
    [0018] Indeed, since the electrical resistivity of the trapping layer is essentially temperature independent, the RF devices which are manufactured on the high resistivity semiconductor substrates will not suffer degradation of their performance in case of heating. According to one embodiment, the trapping layer has a resistivity at 20 ° C greater than a resistivity greater than 5 kOhm.cm, preferably greater than 10 kOhm.cm. Thus, it is possible to manufacture high resistivity semiconductor substrates compatible with RF devices designed for 4G. Indeed, the resistivity greater than 5 kOhm.cm of the trapping layer 30 makes it possible to attenuate the second-generation harmonics at -100 dBm (according to the geometric characteristics of the CPWs of [RODA]) as required for the devices. RF designed for 4G. Furthermore, it is not necessary, unlike the high-resistivity semiconductor substrates known from the prior art, to use a support substrate having a high resistivity. According to one embodiment, the difference in coefficient of thermal expansion of the trapping layer and the support substrate is less than 5 ppm / K between 100 ° C and 1200 ° C. Thus, during the manufacturing process, the deformations excited by the high-resistivity semiconductor substrate will be sufficiently weak and will not generate breakage of said substrate. According to one embodiment, the weakening zone is formed, in step e., By implantation of species selected from the following group: hydrogen, helium.
    [0019] According to one embodiment, step g. Fracture is a thermal annealing comprising a rise in temperature. According to one embodiment, the semiconductor substrate comprises at least one of the materials selected from the following group: silicon, silicon carbide, silicon germanium.
    [0020] According to one embodiment, the support substrate comprises at least one of the materials selected from the following group: silicon, silicon carbide, silicon germanium. According to one embodiment, the dielectric layer comprises at least one of the materials selected from the following group: silicon dioxide, silicon nitride, aluminum oxide. According to one embodiment, the trapping layer comprises microstructures of size less than 20 nm, preferably less than 10 nm. By microstructures is meant crystallites in polycrystalline materials or porous materials. In crystalline materials, crystallites are also called grains.
    [0021] According to one embodiment, the trapping layer comprises a porous or polycrystalline material. According to one embodiment, the trapping layer comprises porous silicon and has a porosity of between 20 and 80%. According to one embodiment, the trapping layer comprises polycrystalline silicon comprising 1 to 20% of carbon. Thus, the carbon atoms included in the polycrystalline silicon layer accumulate at the grain boundaries. Said accumulation of carbon atoms at the grain boundaries block both the reorganization and growth of the polycrystalline silicon gains that may occur during any thermal annealing including a temperature rise. According to one embodiment, the trapping layer has a thickness of between 10 and 50 μm, preferably between 20 and 30 μm. According to one embodiment, the resistivity of the support substrate is between 10 and 2000 Ohm.cm. BRIEF DESCRIPTION OF THE DRAWINGS The invention will be better understood in the light of the description which follows of the particular and nonlimiting embodiment of the invention with reference to the attached figures among which: FIG. schematic cross-section of a high-resistivity semiconductor substrate known from the state of the art; FIG. 2 is a schematic cross-sectional view of a high-resistivity semiconductor substrate according to the invention; - Figure 3 is a schematic cross-sectional view of the method of manufacturing a high-resistivity semiconductor substrate according to the invention.
    [0022] DETAILED DESCRIPTION OF THE INVENTION For the different embodiments, the same references will be used for identical elements or ensuring the same function, for the sake of simplification of the description. The high-resistivity semiconductor substrate 10 illustrated in FIG. 2 comprises a support substrate 20. The support substrate 20 may consist of all the materials commonly used in the microelectronics, optics and opto industries. - 10 electronics and photovoltaics. In particular, the support substrate 20 may comprise at least one of the materials selected from the following group: silicon, silicon carbide, silicon germanium. The high resistivity semiconductor substrate 10 comprises a trapping layer 30.
    [0023] A trapping layer 30 is disposed on the support substrate 20. As disposed on the support substrate 20, it is arranged on one of its faces. The trapping layer 30 includes a defect density greater than a predetermined defect density.
    [0024] The predetermined defect density is defined as the defect density above which the electrical resistivity of the trapping layer 30 is substantially temperature independent. The resistivity of the trapping layer 30 is essentially temperature independent and is understood to mean the electrical resistivity having a variation of less than 10% as a function of temperature. For a sufficient defect density, the predetermined density of defects according to the invention, the conductivity mechanism is dominated by a hopping conductivity regime ("hopping conductivity" according to the English terminology). This mechanism of electrical conductivity is essentially temperature independent. In this regard, the skilled person will find a presentation of electrical conductivity by jumps in N. F. Mott, Phil. Mag, 19, 835, 1969 ". When the electrical conductivity mechanism in the trapping layer 30 is provided by a hopping conductivity mechanism, the electrical resistivity of said material is, therefore, substantially temperature independent. In other words, its electrical resistivity varies little with temperature variations. The determination of the number of defects or the density of defects can be carried out by transmission electron microscopy ("TEM") techniques. The defect density known by the aforementioned technique, the electrical resistivity of the trapping layer 30 can then be measured at different temperatures.
    [0025] Such a protocol then makes it possible to determine the predetermined density of defects beyond which the trapping layer has an electrical resistivity essentially independent of the temperature. By default, without being limiting, we mean grain boundaries in polycrystalline materials, void areas in porous materials, interstices, inclusions... This mechanism of jump conductivity is particularly interesting in the case because it does not have a temperature dependence. The trapping layer 30 may have, at 20 ° C, a resistivity greater than 5 kOhm.cm, preferably greater than 10 kOhm.cm.
    [0026] The entrapment layer 30 may have a thickness of between 10 and 50 μm, preferably between 20 and 30 μm. The trapping layer 30 may very advantageously include microstructures. By microstructures is meant crystallites in polycrystalline materials or porous materials. In crystalline materials, crystallites are also called grains.
    [0027] Advantageously, the trapping layer 30 may comprise a polycrystalline or porous material. Still advantageously, the trapping layer 30 may comprise microstructures smaller than 20 nm, preferably less than 10 nm. The size of a microstructure is defined as the largest of its dimensions. Thus, when the microstructures forming the trapping layer 30 are smaller than 20 nm, it is possible to obtain a trapping layer having a resistivity greater than 5 kOhm.cm. Indeed, the smaller the microstructures, the greater the density of defects or grain boundaries is important. Therefore, microstructure sizes less than 20 nm, or less than 10 nm, the defect density is sufficient to provide conductivity in the jump trapping layer. The jump conductivity generally implies a very high resistivity, and a very low dependence of the resistivity as a function of the temperature. On the other hand, the difference in coefficient of thermal expansion of the entrapment layer 30 and the support substrate 20 is less than 5 ppm / K between 100 ° C and 1200 ° C. The manufacture of RF devices generally requires thermal annealing steps at temperatures above 850 ° C, or above 1000 ° C, for example 1200 ° C. Thus, at such temperatures, and for trapping layer thicknesses of 10 to 50 μm, a difference in coefficient of thermal expansion between the trapping layer 30 and the excessively large support substrate 20 may cause deformations. The sufficiently low coefficient of thermal expansion coefficient, i.e., less than 5 ppm / K, between the support substrate 20 and the trapping layer 30 prevents the high-resistivity semiconductor substrate from being prevented. breaking of the high resistivity semiconductor substrate 10 during a thermal annealing step. By way of example, the support substrate 20 is a silicon substrate, the trapping layer 30 is porous silicon comprising microstructures with a size of less than 20 nm, preferably less than 10 nm, and having a porosity greater than 50%. . The thickness of the trapping layer is between 10 and 50 μm, for example 30 μm. Thus, the size of the microstructures gives the trapping layer a resistivity greater than 5 kOhm.cm for temperatures below 125 ° C. Furthermore, the grains of the trapping layer 30, and more particularly their size, will not be affected during a thermal annealing step comprising a rise in temperature above 850 ° C. Since the grain size of the trapping layer 30 controls the resistivity of said trapping layer 30, its resistivity then remains unchanged during the aforementioned thermal annealing. Still by way of example, the support substrate 20 is a silicon substrate, and the trapping layer 30 is a polycrystalline silicon layer comprising grains smaller than 20 nm, preferably less than 10 nm, and a thickness of between 10 and 50 μm, for example 30 μm. Thus the difference in coefficient of thermal expansion between the support substrate 20 and the trapping layer 30 is less than 5 ppm / K, and prevents any excessive deformation of the substrate 10 that may cause it to break.
    [0028] Thus, the trapping layer 30 has a resistivity greater than 5 kOhm.cm for temperatures below 125 ° C. Furthermore, the polycrystalline silicon layer comprises carbon at a content of between 1 and 20%, for example 5%. Carbon doping of the poly-silicon layer makes it possible to stabilize the size of the grains during a thermal anneal comprising a rise in temperature higher than 850 ° C., for example 1200 ° C. Indeed, without this carbon doping, the grains of the poly silicon layer reorganize and increase in size. This has the effect of reducing the resistivity of the trapping layer 30. When a carbon doping is introduced into the poly silicon layer, the carbon atoms concentrate at the grain boundaries, and freeze any reorganization of the grains during a thermal anneal comprising a rise in temperature above 850 ° C. Therefore, the thermal annealing steps do not affect the electrical properties of the poly silicon layer. The high resistivity semiconductor substrate 10 comprises a dielectric layer 40 disposed on the trapping layer 30. By dielectric layer is meant an electrical insulating layer. The dielectric layer 40 comprises at least one of the materials selected from the following group: silicon dioxide, silicon nitride, aluminum oxide.
    [0029] The dielectric layer 40 may have a thickness of between 10 nm and 1 μm. The high resistivity semiconductor substrate comprises a semiconductor layer 50 disposed on the dielectric layer 40. The semiconductor layer 50 may comprise at least one of the materials selected from the following group: silicon, silicon germanium. The thickness of the semiconductor layer 50 may be between 10 nm and 1 μm, for example 70 nm. It is thus possible to obtain a high-resistivity semiconductor substrate 10 which, according to the invention, makes it possible to extend the field of application of the substrates 10 to the fabrication of RF devices such as antenna switches (" antenna switch "according to the English terminology), amplifiers. Indeed, such substrates 10 have the properties prescribed for the manufacture of RF devices designed for the 4G telecommunications standard.
    [0030] It has also been demonstrated, in the context of the present invention, that a substrate 10 comprising a trapping layer 30 having a resistivity greater than 5 kOhm.cm for temperatures below 125 ° C., formed on a substrate support 20 having a resistivity of 1 kOhm 5 makes it possible to attenuate the power of second generation harmonics at -100 dBm for an input signal of -15 dBm. According to the present invention, the resistivity of the support substrate 20 may be between 10 and 2000 Ohm.cm. It should be noted that with a trapping layer according to the prior art, the resistivity of the support substrate 20 should have been greater than 10 kOhm.cm. However, such support substrates are not commercially available. The invention also relates to the method of manufacturing the high-resistivity semiconductor substrate 10, and illustrated in FIG.
    [0031] The manufacturing process comprises a step a. providing a semiconductor substrate 51. The semiconductor substrate 51 may comprise at least one of the materials selected from the following group: silicon, silicon carbide, silicon germanium.
    [0032] Step b. The method of manufacture comprises providing a support substrate 20. The support substrate 20 may comprise at least one of the materials selected from the following group: silicon, silicon carbide, silicon germanium.
    [0033] The resistivity of the support substrate 20 may be between 10 and 2000 Ohm.cm. Step c. of the process comprises forming a trapping layer on one side of the support substrate 20. Moreover, the trapping layer according to the invention has, at 30 ° C., a resistivity greater than 5 kOhm.cm, preferably greater than 10 kOhm.cm.
    [0034] In addition, according to the invention, the difference in coefficient of thermal expansion of the trapping layer and the support substrate 20 is less than 5 ppm / K between 100 ° C. and 1200 ° C. The trapping layer 30 has a thickness of between 10 and 50 μm, preferably between 20 and 30 μm. Particularly advantageously, the trapping layer 30 comprises microstructures smaller than 20 nm, preferably less than 10 nm. In one embodiment, the trapping layer 30 comprises a porous or polycrystalline material. For example, the trapping layer 30 may be a porous silicon layer formed by an electrochemical anodization step, preferably with a hydrofluoric acid electrolyte, known to those skilled in the art.
    [0035] The formation of the trapping layer 30 in the form of porous silicon may, for example, comprise the following steps: - Formation of an epitaxially doped silicon layer on the support substrate 20, said formation being carried out by the deposition technique in the vapor phase, at a temperature between 900 ° C and 1200 ° C, with precursors of trichlorosilane and B2H6. - An electrochemical anodization step, known per se by the skilled person is then performed. In this case, the support substrate 20 is placed in an enclosure comprising a hydrofluoric acid electrolyte.
    [0036] An anode and a cathode, immersed in the electrolyte, are fed by a source of electric current. The support substrate 20 is positioned so that the doped silicon layer faces the cathode. An electric current is applied between the anode and the cathode through the electric power source. This electric current is generally constant.
    [0037] At the end of anodization, the support substrate 20 is rinsed. Advantageously, the doped silicon layer is p-doped, which makes it possible to accelerate the anodization. The trapping layer 30 thus formed comprises porous silicon.
    [0038] Said porous silicon has a porosity of between 20 and 80%, and microstructures with a size of less than 20 nm. According to another particularly advantageous embodiment, the trapping layer 30 comprises doped polycrystalline silicon comprising 1 to 20% of carbon. The polycrystalline silicon grains are smaller than 20 nm, preferably less than 10 nm. Such polycrystalline silicon layers comprising a doping of 1 to 20% carbon, and grains smaller than 20 nm, or even 10 nm, can not be produced by techniques such as low-pressure chemical vapor deposition. (LPCVD) or chemical vapor deposition at atmospheric pressure (APCVD). The production of such polycrystalline silicon layers comprising a doping of 1 to 20% carbon, and grains smaller than 20 nm, or even 10 nm, then requires the technique of chemical vapor deposition. The formation temperature of the layers must then be greater than 700 ° C, preferably greater than 900 ° C, even more preferably between 1100 and 1200 ° C. The precursors of carbon (C) can comprise at least one of the elements chosen from: methylsilane (SiH3CH3), methane (CH4), ethane (C2H6), propane (C3H8), butane (C4H10), and methyltrichlorosilane (SiCH3Cl3). Silicon precursors (Si) may comprise at least one of silane (SiH4), disilane (Si2H6), dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), tetrachlorosilane (SiCl4). Step d. comprises forming a dielectric layer 40. The dielectric layer 40 may be formed on the trapping layer 30.
    [0039] The dielectric layer 40 may also be formed on the semiconductor substrate 51. The dielectric layer 40 may comprise at least one of the materials selected from the following group: silicon dioxide, silicon nitride, aluminum oxide. A dielectric layer 40 comprising silicon dioxide may for example be obtained by thermal oxidation of a semiconductor substrate 51 made of silicon. The thermal oxidation of a semiconductor substrate 51 made of silicon 10 can be carried out by a thermal annealing step at a temperature of between 800 and 1100 ° C., for example 950 ° C., under an oxygen atmosphere. The thickness of the dielectric layer 40 may be between 10 nm and 1 μm.
    [0040] Step e. comprises forming an embrittlement zone 60 in the semiconductor substrate 51. The embrittlement zone 60 delimits a semiconductor layer 50 from the remainder of the semiconductor substrate 51. In other words, the semiconductor layer 50 is delimited by the embrittlement zone 60 and the free surface 20 of the semiconductor substrate. The weakening zone 60 may be formed by implantation of species selected from the following group: hydrogen, helium. For example, the hydrogen species are implanted in the silicon semiconductor substrate 20, comprising a silicon oxide dielectric layer 40 at an energy of 70 keV and a dose of 6 atoms per cm 2. After formation of the embrittlement zone 60, step f. assembly of the semiconductor substrate 51 and the support substrate 20 is performed. The assembly is carried out so as to form the structure 30 comprising, from its rear face by its front face, the support substrate 20, the trapping layer 30, the dielectric layer 40, and the semiconductor layer 50. following step f. assembly, step g. fracture of the semiconductor substrate 51 according to the weakening zone 60 is executed.
    [0041] This step results in the transfer of the semiconductor layer 50 and the dielectric layer 40 to the trapping layer 30. When the embrittlement zone 60 is obtained by implantation of species, the fracture step g. may be performed by thermal annealing including a rise in temperature, for example 400 ° C for 1 hour. At the end of step g. of fracture, the semiconductor substrate obtained can undergo a thermal annealing comprising a rise in temperature above 850 ° C, for example 900 ° C, for reinforcing the assembly interface formed by the dielectric layer 40 and the layer In view of the thickness of the trapping layer 30, the difference in coefficient of thermal expansion between the trapping layer 30 and the support substrate 20 of less than 5 ppm / K is used to limit the deformation. of the high-resistivity semiconductor substrate, and the risk of breakage of said substrate 10. REFERENCES - Silicon-on-insulator (SOI) Technology, manufacture and 25 applications ", points 10.7 and 10.8, Oleg Kononchuk and Bich-Yen Nguyen, at Woodhead Publishing - C. Roda Neve et al., Impact of neutron irradiation on the RF properties of oxidized high-resistivity silicon substrates with and without a rich passivation layer, Microelectronics Reliability, 50 (2011), 326-331 - F. F. Mott, Phil. Mag, 19, 835, 1969
    权利要求:
    Claims (28)
    [0001]
    REVENDICATIONS1. A high resistivity semiconductor substrate comprising: - a trapping layer (30); a dielectric layer (40) disposed on the trapping layer (30); a semiconductor layer (50) disposed on the dielectric layer (40); the substrate being characterized in that the trapping layer (30) comprises a defect density greater than a predetermined defect density, the predetermined defect density is the defect density beyond which the electrical resistivity of the trapping layer (30) is essentially temperature independent.
    [0002]
    2. The substrate of claim 1, wherein the trapping layer (30) has a resistivity at 20 ° C greater than 5 kOhm.cm, preferably greater than 10 kOhm.cm.
    [0003]
    3. The substrate according to claim 1 or 2, wherein the trapping layer (30) rests on a support substrate (20), the difference in coefficient of thermal expansion of the trapping layer (30) and the support substrate (20). ) is less than 5 ppm / K between 100 ° C and 1200 ° C.
    [0004]
    4. Substrate according to one of claims 2 to 3, wherein the trapping layer (30) comprises microstructures smaller than 20 nm, preferably less than 10 nm.
    [0005]
    5. Substrate according to one of claims 2 to 4, wherein the trapping layer (30) comprises a porous or polycrystalline material.
    [0006]
    6. Substrate according to one of claims 2 to 5, wherein the trapping layer (30) comprises porous silicon. 3029682 21
    [0007]
    Substrate according to one of claims 2 to 5, wherein the entrapment layer (30) comprises polycrystalline silicon comprising 1 to 20% carbon. 5
    [0008]
    8. Substrate according to one of claims 2 to 7, wherein the thickness of the trapping layer (30) is between 10 and 50 pm, preferably between 20 and 30 pm.
    [0009]
    9. Substrate according to one of claims 2 to 8, wherein the support substrate (20) comprises at least one of the materials selected from the following group: silicon, silicon carbide, silicon germanium.
    [0010]
    10. Substrate according to one of claims 2 to 9, wherein the resistivity of the support substrate (20) is between 10 and 2000 Ohm.cm.
    [0011]
    11. Substrate according to one of claims 1 to 10, wherein the semiconductor layer (50) comprises at least one of the materials selected from the following group: silicon, silicon carbide, silicon germanium.
    [0012]
    12. Substrate according to one of claims 1 to 11, wherein the thickness of the semiconductor layer (50) is between 10 nm and 1 pm.
    [0013]
    Substrate according to one of claims 1 to 12, wherein the dielectric layer (40) comprises at least one of the materials selected from the group consisting of silicon dioxide, silicon nitride, aluminum oxide.
    [0014]
    Substrate according to one of claims 1 to 13, wherein the dielectric layer (40) is between 10 nm and 1 μm. 15 20 3029682 22
    [0015]
    A method of manufacturing a high-resistivity semiconductor substrate, comprising, from its back face to its front face, a support substrate, a trapping layer, a dielectric layer, and a semiconductor layer, said method comprising the following steps: a. providing a semiconductor substrate (51); b. providing a support substrate (20); vs. forming a trapping layer (30) on the support substrate (20); d. forming a dielectric layer (40); e. forming a weakening zone (60) in the semiconductor substrate, the weakening zone (60) defining a semiconductor layer (50) of the remainder of the semiconductor substrate (51); f. assembling the semiconductor substrate (51) and the support substrate (20); boy Wut. fracturing the semiconductor substrate (51) along the embrittlement zone (60) so as to transfer the semiconductor layer (50) to the support substrate (20); the method being characterized in that the trapping layer (30) comprises a defect density greater than a predetermined defect density, the predetermined defect density is the defect density beyond which the electrical resistivity of the trapping layer (30) is essentially temperature independent.
    [0016]
    16. The manufacturing method according to claim 15, wherein the trapping layer (30) has a resistivity, at 20 ° C, greater than 5 kOhm.cm, preferably greater than 10 kOhm.cm. 25
    [0017]
    17. The manufacturing method according to claim 15 or 16, wherein the difference in coefficient of thermal expansion of the trapping layer (30) and the support substrate (20) is less than 5 ppm / K between 100 ° C and 1200 ° C. 3029682 23
    [0018]
    18. Manufacturing method according to one of claims 15 to 17, wherein the weakening zone (60) is formed in step e., By implantation of species selected from the following group: hydrogen, helium. 5
    [0019]
    19.Manufacturing method according to one of claims 15 to 18, wherein step g. Fracture is a thermal annealing comprising a rise in temperature. 10
    [0020]
    20.Procédé de manufacture according to one of claims 15 to 19, wherein the semiconductor substrate (51) comprises at least one of the materials selected from the following group: silicon, silicon carbide, silicon germanium. 15
    [0021]
    21.Procédé de manufacture according to one of claims 15 to 20, wherein the support substrate (20) comprises at least one of the materials selected from the following group: silicon, silicon carbide, silicon germanium. 20
    [0022]
    22.Procédé de manufacture according to one of claims 15 to 21, wherein the dielectric layer (40) comprises at least one of the materials selected from the following group: silicon dioxide, silicon nitride, aluminum oxide. 25
    [0023]
    23. The manufacturing method according to one of claims 15 to 22, wherein the trapping layer (30) comprises microscratures of size less than 20 nm, preferably less than 10 nm.
    [0024]
    24. The manufacturing method according to one of claims 15 to 23, wherein the trapping layer (30) comprises a porous or polycrystalline material. 3029682 24
    [0025]
    25.Procédé de manufacture according to one of claims 15 to 24, wherein the trapping layer (30) comprises porous silicon, and porosity between 20 and 80%. 5
    [0026]
    26. The manufacturing method according to one of claims 15 to 24, wherein the trapping layer (30) comprises polycrystalline silicon comprising 1 to 20% carbon.
    [0027]
    27. The manufacturing method according to one of claims 15 to 26, wherein the trapping layer (30) has a thickness of between 10 and 50 μm, preferably between 20 and 30 μm.
    [0028]
    28.Procédé de manufacture according to one of claims 15 to 27, wherein the resistivity of the support substrate (20) is between 10 and 2000 Ohm.cm.
    类似技术:
    公开号 | 公开日 | 专利标题
    FR3029682A1|2016-06-10|HIGH RESISTIVITY SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME
    EP2715808B1|2018-07-25|Semiconductor structure for emitting light, and method for manufacturing such a structure
    EP3175477B1|2021-02-24|Structure for radio-frequency applications
    FR2933233A1|2010-01-01|GOOD RESISTANCE HIGH RESISTIVITY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME
    EP2157603B1|2011-10-12|Method for manufacturing localised GeOI structures, obtained by germanium enrichment
    FR2860341A1|2005-04-01|METHOD FOR MANUFACTURING LOWERED LOWER MULTILAYER STRUCTURE
    FR3062238A1|2018-07-27|SUPPORT FOR A SEMICONDUCTOR STRUCTURE
    FR2946478A1|2010-12-10|RESONATOR WITH VOLUME WAVES.
    EP3420583A1|2019-01-02|Carrier for a semiconductor structure
    FR3051595A1|2017-11-24|METHOD FOR MANUFACTURING A CONDUCTIVE SEMICONDUCTOR TYPE SUBSTRATE ON INSULATION
    WO2020008116A1|2020-01-09|Substrate for an integrated radiofrequency device, and process for manufacturing same
    FR2865850A1|2005-08-05|Production of field effect transistors with reduced short channel effects and offering an elevated degree of integration for Silicon On Insulator integrated circuits
    FR3051596A1|2017-11-24|METHOD FOR MANUFACTURING A CONDUCTIVE SEMICONDUCTOR TYPE SUBSTRATE ON INSULATION
    EP3469627B1|2020-07-29|Structure for radiofrequency applications
    FR3068506A1|2019-01-04|PROCESS FOR PREPARING A SUPPORT FOR A SEMICONDUCTOR STRUCTURE
    EP3840032A1|2021-06-23|Process for producing a multilayer stack of the semiconductor-on-insulator type
    EP3391407B1|2020-01-15|Compensation of an arc curvature generated in a wafer
    FR3106019A1|2021-07-09|MANUFACTURING PROCESS OF A SEMICONDUCTOR TYPE STRUCTURE ON INSULATION FOR RADIO FREQUENCY APPLICATIONS
    EP3503173A1|2019-06-26|Useful film transfer method
    WO2018142052A1|2018-08-09|Structure for a radio frequency application
    WO2022023630A1|2022-02-03|Method for transferring a thin layer onto a support substrate provided with a charge trapping layer
    FR3085537A1|2020-03-06|SOI WAFER AND METHOD FOR PRODUCING THE SAME
    FR3113184A1|2022-02-04|METHOD FOR PREPARING A SUPPORT SUBSTRATE, AND METHOD FOR TRANSFERRING A THIN LAYER ONTO THIS SUPPORT SUBSTRATE
    WO2021234280A1|2021-11-25|Method for manufacturing a semiconductor-on-insulator substrate for radiofrequency applications
    FR3085538A1|2020-03-06|SOI WAFER AND METHOD FOR PRODUCING THE SAME
    同族专利:
    公开号 | 公开日
    FR3029682B1|2017-12-29|
    EP3227905A1|2017-10-11|
    EP3227905B1|2021-08-18|
    CN107004572A|2017-08-01|
    US10250282B2|2019-04-02|
    US20170331501A1|2017-11-16|
    JP6612872B2|2019-11-27|
    EP3872839A1|2021-09-01|
    JP2018501651A|2018-01-18|
    CN107004572B|2020-05-22|
    KR20170091627A|2017-08-09|
    SG11201704516QA|2017-07-28|
    WO2016087728A1|2016-06-09|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20100314722A1|2008-03-19|2010-12-16|Shin-Etsu Handotai Co., Ltd.|Soi wafer, semiconductor device, and method for manufacturing soi wafer|
    US20130084689A1|2010-12-24|2013-04-04|Io Semiconductor, Inc.|Trap Rich Layer Formation Techniques for Semiconductor Devices|EP3319113A1|2016-11-04|2018-05-09|Soitec|Method of fabrication of a semiconductor element comprising a highly resistive substrate|
    WO2018137937A1|2017-01-26|2018-08-02|Soitec|Support for a semiconductor structure|
    FR3067517A1|2017-06-13|2018-12-14|Commissariat A L'energie Atomique Et Aux Energies Alternatives|SUBSTRATE SOI COMPATIBLE WITH RFSOI AND FDSOI TECHNOLOGIES|
    US10297464B2|2015-06-09|2019-05-21|Soitec|Process for the manufacture of a semiconductor element comprising a layer for trapping charges|US5637883A|1995-02-27|1997-06-10|The United States Of America As Represented By The Secretary Of The Navy|Optically addressed spatial light modulator using an intrinsic semiconductor active material and high resistivity cladding layers|
    JP4983010B2|2005-11-30|2012-07-25|富士通株式会社|Piezoelectric element and manufacturing method thereof|
    FR2973158B1|2011-03-22|2014-02-28|Soitec Silicon On Insulator|METHOD FOR MANUFACTURING SEMICONDUCTOR-TYPE SUBSTRATE ON INSULATION FOR RADIO FREQUENCY APPLICATIONS|
    KR101876579B1|2012-09-13|2018-07-10|매그나칩 반도체 유한회사|Power Semiconductor and Fabricating Method Thereof|US10541667B2|2015-08-25|2020-01-21|Avago Technologies International Sales Pte. Limited|Surface acoustic waveresonator having trap-rich region|
    US10530327B2|2015-08-25|2020-01-07|Avago Technologies International Sales Pte. Limited|Surface acoustic waveresonator|
    US10523178B2|2015-08-25|2019-12-31|Avago Technologies International Sales Pte. Limited|Surface acoustic waveresonator|
    US10181428B2|2015-08-28|2019-01-15|Skyworks Solutions, Inc.|Silicon on porous silicon|
    EP3144958B1|2015-09-17|2021-03-17|Soitec|Structure for radiofrequency applications and process for manufacturing such a structure|
    KR20180116261A|2016-02-25|2018-10-24|니폰 제온 가부시키가이샤|HEAT CONDUCTIVE SHEET, METHOD FOR MANUFACTURING THE SAME,|
    FR3053532B1|2016-06-30|2018-11-16|Soitec|HYBRID STRUCTURE FOR ACOUSTIC SURFACE WAVE DEVICE|
    FR3062517B1|2017-02-02|2019-03-15|Soitec|STRUCTURE FOR RADIO FREQUENCY APPLICATION|
    US10784348B2|2017-03-23|2020-09-22|Qualcomm Incorporated|Porous semiconductor handle substrate|
    US11063117B2|2017-04-20|2021-07-13|Taiwan Semiconductor Manufacturing Co., Ltd.|Semiconductor device structure having carrier-trapping layers with different grain sizes|
    CN111884616B|2020-07-23|2021-04-13|中国科学院上海微系统与信息技术研究所|Substrate/piezoelectric material thin film structure and preparation method and application thereof|
    CN112750686B|2020-12-30|2021-12-07|济南晶正电子科技有限公司|Multilayer substrate, electronic component and preparation method of multilayer substrate|
    法律状态:
    2015-11-23| PLFP| Fee payment|Year of fee payment: 2 |
    2016-06-10| PLSC| Publication of the preliminary search report|Effective date: 20160610 |
    2016-11-21| PLFP| Fee payment|Year of fee payment: 3 |
    2017-11-21| PLFP| Fee payment|Year of fee payment: 4 |
    2019-11-20| PLFP| Fee payment|Year of fee payment: 6 |
    2020-11-25| PLFP| Fee payment|Year of fee payment: 7 |
    2021-11-25| PLFP| Fee payment|Year of fee payment: 8 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1402801A|FR3029682B1|2014-12-04|2014-12-04|HIGH RESISTIVITY SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME|FR1402801A| FR3029682B1|2014-12-04|2014-12-04|HIGH RESISTIVITY SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME|
    EP15788467.7A| EP3227905B1|2014-12-04|2015-09-17|Structure for radiofrequency applications|
    PCT/FR2015/052494| WO2016087728A1|2014-12-04|2015-09-17|Structure for radiofrequency applications|
    SG11201704516QA| SG11201704516QA|2014-12-04|2015-09-17|Structure for radiofrequency applications|
    JP2017529767A| JP6612872B2|2014-12-04|2015-09-17|Structure for high frequency applications|
    US15/531,976| US10250282B2|2014-12-04|2015-09-17|Structure for radiofrequency applications|
    KR1020177015538A| KR20170091627A|2014-12-04|2015-09-17|Structure for radiofrequency applications|
    EP21170134.7A| EP3872839A1|2014-12-04|2015-09-17|Structure for radiofrequency applications|
    CN201580065277.5A| CN107004572B|2014-12-04|2015-09-17|Architecture for radio frequency applications|
    [返回顶部]