• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
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    • 专利摘要:
    The invention relates to a read circuit for reading a programmed resistive state of resistive elements (102) of a resistive memory (101), each resistive element being programmable to take one of a first and a second state. resistor (Rmax, Rmin), the circuit comprising a current integrator (122) adapted to integrate a current difference between a read current (IR) passing through a first of the resistive elements and a reference current (IREF).
    公开号:FR3029342A1
    申请号:FR1461717
    申请日:2014-12-01
    公开日:2016-06-03
    发明作者:Salim Renane；Pierre Paoli；Virgile Javerliac
    申请人:Centre National de la Recherche Scientifique CNRS；Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] The present description relates to the field of resistive memories, and in particular a read circuit for a resistive memory.
    [0002] PRIOR ART It has already been proposed to produce a non-volatile memory cell in the form of a programmable resistive element. Such resistive elements are programmable to take one of a resistive state up or down. The programmed resistive state is maintained even when a supply voltage of the memory cell is disconnected, and therefore data can be stored by such an element in a non-volatile manner. A resistive memory is a device that comprises a plurality of memory cells each comprising a resistive element, the cells forming for example a matrix. To read the data programmed in one of the memory cells of the resistive memory, the memory cell is selected, and a current is passed through the resistive element of the cell. The high or low resistive state of the resistive element can then be detected by measuring the level of current flowing in the resistive element.
    [0003] B13636 - BD15664 - 0107627-01 2 A difficulty is that, in order to conserve relatively low power consumption and surface area on the chip, the high and low resistive states tend to have relatively similar resistances. In addition, manufacturing dispersions can lead to actual strengths that are even closer. For example, for an average resistance of about 4 kilo-ohms, the difference between the high and low resistive states can be as low as 200 ohms, in other words only about 5 percent. There is therefore a need in the art for a circuit capable of accurately detecting such a small current change resulting from the two resistive states. SUMMARY An object of embodiments of the present disclosure is to at least partially solve one or more needs of the prior art. According to one aspect, there is provided a read circuit for reading a programmed resistive state of resistive elements of a resistive memory, each resistive element being programmable to take one of a first and a second resistive state, the circuit comprising: a current integrator adapted to integrate a current difference between a read current flowing in a first of the resistive elements and a reference current. According to one embodiment, the current integrator comprises a capacitive transimpedance amplifier. According to one embodiment, the read circuit further comprises a current mirror comprising a first branch adapted to conduct the reference current, and a second branch coupled to: a first line coupled to the first resistive element to conduct the current of reading ; and a second line coupled to the current integrator for conducting the difference between the read current and the reference current. According to one embodiment, the current integrator comprises a differential amplifier comprising: a first input node coupled to the second line; a feedback path comprising a capacitor coupled between an output node of the differential amplifier and the first input node; and a second input node coupled to a first reference voltage. According to one embodiment, the first branch of the current mirror is coupled to a reference current generation block, and the second input node of the differential amplifier is coupled to the first branch. According to one embodiment, the read circuit further comprises a selection and bias circuit for selecting the first resistive element and applying a bias voltage to the first resistive element, the selection and biasing circuit comprising: a first transistor coupled to the first resistive element and adapted to conduct the read current, the first transistor having a control node coupled to the bias voltage. According to one embodiment, the first transistor is a NOS transistor, and the selection and polarization circuit further comprises by its conduction nodes: a second main coupled transistor between the gate of the first transistor and a ground level; and a third transistor coupled by its main conduction nodes between a source of the first transistor and the ground level. According to one embodiment, the selection and polarization circuit further comprises another transistor coupled in series with the first transistor. According to one embodiment, the first transistor is an N-channel NOS transistor, and the other transistor is a P-channel NOS transistor having its source coupled to a drain of the first transistor. According to one embodiment, the reference current 35 is generated by a reference current generating block B13636 - BD15664 - D107627-t1 - 4 comprising a K matrix with K resistive elements, K being a positive peer integer greater than or equal to 2. According to one embodiment, the matrix of resistive elements comprises K rows of resistive elements, the resistive elements of each row being coupled in parallel with each other, the rows of resistive elements being coupled in series with each other, and the Resistive elements in one half of the rows are programmed to have the high resistive state, and the resistive elements in the other half of the rows are programmed to have the low resistive state. According to one embodiment, the reference current is generated by a reference current generation block comprising a reference resistive element sized and programmed so that its resistance is at a level located between the resistances of the first and second states. resistive of each resistive element. According to one embodiment, the resistive memory comprises a plurality of resistive element columns, and the read circuit comprises a current integrator for each column, and a reference current generation block common to the plurality of columns. According to one embodiment, each of the resistive elements is of one of the following types: a spin transfer torque element having anisotropy in the plane; a spin transfer torque element having anisotropy perpendicular to the plane; an oxidation-reduction element; a ferroelectric element; and a phase change element. In another aspect, there is provided a method of reading a programmed resistive state of resistive elements of a resistive memory, each resistive element being programmable to take one of a first and a second resistive state, the method comprising: selecting a first one of the resistive elements; and integrating, by a current integrator, a current difference between a read current flowing in a first of the resistive elements, and a reference current.
    [0004] B13636 - BD15664 - D107627-01 According to one embodiment, the reference current is generated by a reference branch of a current mirror, and the integration of the current difference is based on a reference voltage of the branch reference. Brief description of the drawings. The foregoing and other features and advantages will be apparent from the following detailed description of embodiments, given by way of illustration and not limitation, with reference to the accompanying drawings in which: FIG. 1 schematically illustrates a memory non-volatile according to one embodiment of the present description; Figure 2 schematically illustrates a current integrator of Figure 1 in more detail according to an exemplary embodiment; Figure 3 is a timing diagram showing signals in the circuit of Figure 2 according to an exemplary embodiment; FIG. 4 schematically illustrates circuits of FIG. 1 in more detail according to an exemplary embodiment; Fig. 5 is a timing chart illustrating signals in the circuit of Fig. 4 according to an embodiment of the present disclosure; FIGS. 6A and 6B each schematically illustrate a switching circuit of FIG. 1 according to alternative embodiments of the present description; Figs. 7A-70 each schematically illustrate a reference current generating block of Fig. 1 in more detail according to alternative embodiments of the present disclosure; FIG. 8 schematically illustrates a non-volatile memory according to another embodiment of the present description; and FIGS. 9A and 9B illustrate resistive elements based on magnetic tunnel junctions according to embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Detailed Description In the following description, the term "connected" is used to refer to direct connections between one element and another, while the term "coupled" implies that the connection between the two elements may be direct, or may be via an intermediate element, such as a transistor, resistor or other component. FIG. 1 schematically illustrates a non-volatile memory 100 comprising a resistive memory 101 comprising a plurality of resistive elements 102. The resistive elements 102 form, for example, a matrix and although this is not illustrated in FIG. 1, they can be arranged in a grid of rows and columns. The memory elements 102 could also form other types of resistive memories, such as one or more registers. Each of the resistive elements 102 is capable of being programmed to take one of two resistive states. The resistive elements 102 may be of any type of resistance switching element for which the resistance is programmable by the direction of a current passed through it, and / or by other means, such as application of a magnetic field near the element. For example, the resistive elements 102 are spin transfer torque (STT) elements having anisotropy in the plane or perpendicular to the plane, as described in more detail in the publication entitled "Magnonic spin-transfer torque MRAM with low". power, high speed, and error-free switching ", N. Mojumder et al., IEDM Tech. Digest (2010), and in the publication titled "Electric toggling of magnets", E. Tsymbal, Natural Materials Vol 11, January 2012. Alternatively, the resistive elements could be those used in RAM RedOx type resistive switching memories ( Redox NMRs), which are described in more detail in the publication entitled "Redox-Based Resistive Switching Memories - Nanoionic Mechanisms, Prospects and Challenges", by Rainer Waser et al., Advanced Materials 2009, 21, pages 2632 to 2663. In yet another example, the resistive elements could be those used in FeRAM (ferroelectric RAM) or in PCRAM (phase change RAM). Whatever the type of the resistive elements, a bit of data is for example stored in each element in a nonvolatile manner by programming the element so that it takes a relatively high resistance (Rmax) or a relatively low resistance (Rmin). . Each resistive element 102 has, for example, only two resistive states corresponding to the high and low resistors Rmax and Rmin, but the exact values of Rmin and Rmax can vary depending on conditions such as the manufacturing process, the materials, the variations in temperature, etc. The resistive elements 102 are for example adapted such that Rmax is always significantly greater than Rmin, for example greater than at least 5 percent. In general, the ratio between the resistance Rmax and the resistor Rmin is, for example, between 1.05 and 100. Each of the resistives Rmin and Rmax is, for example, in the range of 1 to 10 kilo-ohms, and the difference between Rmin and Rmax is, for example, in the range of 100 ohms to 4 kilo-ohms, although many other values are possible. The resistive memory 101 comprises, for example, a selection and biasing circuit 104A, 104B for selecting a resistive element during a read operation, and for applying a bias voltage Vpol across the selected resistive element to create an IR read current in the resistive element 102. The circuit 104A allows for example selectively couple each of the resistive elements 102 to a line 105, and also allows to apply the bias voltage Vpol, to a node of each 35 Resistive element 102. In some embodiments, another circuit 104B is also provided to selectively couple each resistive element 102 to a ground voltage, and provide another level of selection. Each of the circuits 104A and 1048 receives, for example, an ADDRESS address signal indicating which resistive element 102 of the resistive memory 101 is to be read. The signals Vpol, and ADDRESS are for example generated by a control block 106, which for example receives a clock signal CLK. The line 105 is coupled to a node 107, which in turn is coupled to a branch of a current mirror 108. The current mirror 108 consists, for example, of two transistors 110, 112, each being, for example, a NOS transistor. P-channel (PMOS). For example, the transistor 110 has its main conduction nodes, for example its source and drain nodes, coupled to a supply voltage VDD and the node 107, respectively, and its control node coupled to the control node of the transistor 112. The transistor 112 has, for example, its main conduction nodes coupled to the supply voltage VDD and to a line 114, respectively. The line 114 is also for example coupled to the control nodes of the transistors 110, 112. The line 114 conducts a reference current IREF, which is for example generated by a reference current generation block 115. The block 115 comprises, for example a bias circuit 116 coupling the line 114 to a reference resistive block 117. In some embodiments, the reference resistive block 117 is coupled to ground via a dummy selection block 118 which matches the characteristics of the circuit 104E of the resistive memory 101. In some embodiments, the reference resistive block 117 is adapted to have a resistance equal to the average resistance of the high and low resistors of each resistive element 102 of the resistive memory, in other words, substantially equal to (Rmin + Rmax) / 2, where the term "sensi- B13636 - BD15664 - D107627-01 9" implies an equal tolerance, eg example at +/- 2 percent. The node 107 is also coupled to a current integrator 122 via a line 120. The transistor 111 of the current mirror 108 for example leads a current IREF equal to the reference current on the line 114, and thus the line 120 leads for example a current in the direction of the node 107 equal to IR-IREF, in other words equal to the difference between the read current and the reference current IREF. This current difference is, for example, positive in the case where the selected resistive element 102 has the low resistive state Emin, and is negative in the case where the resistive element 102 has the high resistive state Rmax. The current integrator 122 provides a VDIFF signal, which is for example positive in the case where the IR-IREF current is positive, and negative in the case where the IR-IREF current is negative. This VDIFF voltage is for example compared to a reference voltage VREF1 by a comparator 124 to provide a BIT output data signal indicating the binary value stored by the selected resistive element 102 which is being read. The comparator 124 is for example controlled to sample the VDIFF signal by a control signal COMP generated by the control block 106. In one embodiment, the reference voltage VREF1 is equal to the ground voltage. As a variant, the reference voltage VREF1 is equal to the voltage on the line 114 of the reference branch of the current mirror 108. In addition, the current integration performed by the current integrator 122 is for example performed relative to at a reference voltage VREF2, which could be identical to or different from the reference voltage VREF1, for example equal to the ground voltage, or to the voltage on the line 114. Advantageously, in the case where the voltages VREF1 and VREF2 are both equal to the voltage on line 114, there will be an adaptation of the drain-source voltages for the two PMOS transistors 110, 112 of the current 108, which leads to good matching between the reference currents IREF in each PMOS transistor 110; 112 of the current mirror 108. FIG. 2 illustrates the current integrator 122 of FIG. 1 in more detail according to an example in which it is implemented by a capacitive transimpedance amplifier (CTIA). Of course, in alternative embodiments, other types of current integrators could be used. Line 120 from node 107 is, for example, coupled to a negative input node of differential amplifier 202, which has, for example, its positive input node coupled to reference voltage VREF2. The input line 120 is also coupled through a feedback path including the parallel connection of a capacitor 204 and a switch 206 to an output line 208 of the amplifier. Differential indicator 202. Switch 206 is for example controlled by a reset signal RAZ. The capacitor 204 has for example a capacitance of the order of 1 fF to 100 fF. The output line 208 provides, for example, the voltage signal VDIFF. The operation of the circuit of FIGS. 1 and 2 will now be described in more detail with reference to the timing diagram of FIG. 3. FIG. RAZ reset signal, VDIFF voltage, and BIT output signal. Initially, the reset signal reset is, for example, turned on so that the switch 206 is conductive, and the voltage across the capacitor 204 is reset to a low level of about 0 V. The reset signal reset is made to the low state with a falling edge 302, triggering a period of integration of the IR-IREF current on the line 120. In the example of FIG. 3, the VDIFF signal increases, which implies that the IR-IREF current is positive, in other words B13636 - BD15664 - D107627-01 11 flows towards the node 107. At a sampling instant ts at the end of the integration period tINT, the comparator 124 is for example, synchronized by the signal COMP to sample the signal VIDIFF, and the output of the comparator thus goes high. FIG. 3 also illustrates an example of the next cycle during which the reset signal RAZ is again applied, causing a resetting of the voltage across the capacitor 204, and a falling edge 304 of the reset signal causes the start of a new one. integration period tINT. This time, the VDIFF output signal goes low due to a negative current on the line 120. FIG. 4 schematically illustrates the resistive memory 101 and the reference current generation block 115 of FIG. in more detail according to an exemplary embodiment. In the example of FIG. 4, the resistive memory 101 comprises M columns COL1 to COLM, each column comprising N resistive elements, M and N being positive integers greater than or equal to 2. In each column, the N resistive elements 102 have one of their nodes coupled to a common line 402, and their other node coupled to the selection circuit 1045. In the example of Figure 4, the selection circuit 104B comprises, for each resistive element 102, a corresponding transistor 404 coupling to a line 406. The selection circuit 104B also includes for example a transistor 408 coupling the line 406 to ground. Transistors 404 and transistor 408 are all for example NMOS transistors. The transistors 404 for the N elements are for example controlled by control signals WSEL1 to WSELN respectively. The selection and polarization circuit 104A comprises, for example, for each column, a transistor 412 having one of its main conduction nodes coupled to the line 105, and the other of its main conduction nodes 35 coupled to the line For example, the control node of the transistor 412 is coupled via a switch 414 to an input line receiving the bias voltage VpoL. The switches 414 of the columns COL1 to COLM are for example controlled by corresponding control signals BSEL1 to BSELM forming part of the address signal ADDRESS. The transistor 412 is for example an NMOS transistor, and its gate node and its source node are for example both coupled to ground by a corresponding transistor 416, 418. The transistors 416 and 418 of COLI COLM columns are for example NMOS transistors monitored at their gate nodes by signals to BSEL1 to BSELM respectively. The reference current generating block 115 comprises, for example, a transistor 420 forming the circuit 116 and coupled by its main conduction nodes between the line 114 and the resistive reference block 117. The transistor 420 is for example an NMOS transistor and at its control node coupled to the bias voltage VpoL. The reference resistive block 117 is also for example coupled to ground via a transistor 422, which is for example an NMOS transistor 20 adapted to have characteristics similar to those of the transistor 408 of each column of the resistive memory 101. FIG. 5 is a timing diagram showing examples of signals in the circuit of FIGS. 1 and 4 according to an exemplary embodiment. In particular, Fig. 5 shows the signals CLK, ADDRESS, RAZ, BSEL1, BSEL2, BSEL3, BSELM, VDIFF, COMP and BIT. As illustrated, during a first read period, a first resistive element at the address @ 1 is selected by activating one of the word line signals WSEL1 through WSELN (not shown in FIG. 5) and selecting a first bit by activating the control signal BSEL1. A short time later, the signal RAZ is brought from a high state to a low state, to activate the current integrator 122. In the example of FIG. 5, the VDIFF signal 35 then rises up to a time when the signal COMP goes to the high state which causes the comparator 124 to sample the input signal. The BIT signal on the output of comparator 124 thus goes high shortly thereafter. For example, the signal VIDIFF has a small step 5 when the signal COMP is activated, and then continues to rise until the reset signal reset is activated again on a rising edge of the clock signal CLK. Several subsequent read cycles are also illustrated in FIG. 5, corresponding to read operations at addresses @ 2, @ 3 up to address @M, which correspond for example to resistive elements in columns 2 to M. FIG. 6A schematically illustrates the selection and biasing circuit 104A of FIG. 4 in more detail according to an alternative embodiment with respect to FIG. 4. For each column COL1 to COLM, the circuit 104A comprises for example two transistors 602 and 604 coupled in series by their main conduction nodes between the line 105 and the line 402 of the respective column. Both transistors 602 and 604 are, for example, NMOS transistors. Transistors 602 have for example their drains coupled to node 105, and are for example controlled by bias voltage VpoL. The transistor 604 of each column COLI to COLM is for example controlled by the corresponding selection signal BSEL1 to BSELM, and has its source coupled to the corresponding line 402. FIG. 63 schematically illustrates the selection and polarization circuit 104A of FIG. Figure 4 in more detail according to yet another embodiment. For each column COL1 to COLM, the circuit 104A comprises, for example, two transistors 606 and 608 coupled in series by their main cohesion nodes between the line 105 and the line 402 of the respective column. Transistors 606 are for example PMOS transistors having their source nodes coupled to line 105, and respectively controlled by the inverse signals BSEL1 to BSELAI of the corresponding selection signal. Transistors 608 are, for example, NMOS transistors having their source nodes coupled to the corresponding line 402, each of which is controlled at its gate node by the bias voltage V.sub.L.sub.L. An advantage of the circuit of FIG. 6B is that the circuit has a high efficiency since the bias voltage Vp1 0 is applied by the transistors 608 to the lines 402 without intermediate components. Figs. 7A-7C schematically illustrate block 117 of the reference current generating block 115 in more detail according to exemplary embodiments. In the embodiment of FIG. 7A, the block 117 is constituted for example by an arrangement of K by K reference cells 701, where K is equal to two, but in variant embodiments, K could be any integer Greater than or equal to 2. Each cell 701 comprises, for example, a resistive element 102 similar to those of the resistive memory 101 of FIG. 1, coupled in series with a transistor 702. The transistors 702 are all for example NMOS transistors, and each has its source or drain node coupled to a node of the corresponding resistive element 102, and its control node is coupled to a high voltage, so that it is permanently activated. The cells 701 of each row of cells are, for example, serially coupled to each other between input / output lines 704, 706 of block 117, and the rows are, for example, coupled in parallel between each other between the input lines. output 704, 706. Thus, the overall resistance of the block between the input / output lines 704, 706 is equal to the average resistance of the cells 701. The resistive elements 102 of half of the rows and / or half of the columns For example, 30 cells are adapted to have a high programmed resistance of Rmax, while the other resistive elements are, for example, programmed to have a low programmed resistive of Rmin. FIG. 7E illustrates in more detail block 117 of the reference current generating block 115 in accordance with FIG. 7A, in which a source of variable current source is used. Variable current .710 is for example a current source which can be calibrated, for example during a calibration phase of the memory, on the basis of test data stored in the resistive memory 101 and read by the read circuit. The current source 710 is for example controlled by a control signal S, for example a voltage level. The variable current source 710 is, for example, provided by one or more polymer resistors, one or more diffusion resistors being used. , and / or one or more NMOS current sources. Alternatively, the variable current source 710 could be implemented by one or more external current sources, in other words current sources which are either disposed outside the nonvolatile memory but in the same way. integrated circuit, or arranged in another integrated circuit, coupled to the non-volatile memory by an input / output pad. FIG. 7C illustrates in more detail block 117 of the reference current generation block 115 according to an exemplary variant with respect to FIGS. 7A and 7B, in which it is implemented by an arrangement of L by L resistive elements. 102, where L is four in the example of FIG. 70. In alternative embodiments, L could be any integer equal to 2 or more. The resistive elements 102 of each row are for example coupled in parallel with each other, and the rows are coupled in series between the lines 704 and 706. The resistive elements 102 of the half rows are for example programmed to have a high resistance. of Rmax, and the resistive elements of the other half of the rows are for example programmed to have a low resistance of Rmin, so that the overall resistance of the block 116 between the lines 704, 706 is equal to (Rmax + Rmin) / 2. In another example, the block 117 of the reference current generation block 115 could include an exemplary variant thereof 710. The reference resistive element coupled between the lines input and output 704, 706 and programmed to have a resistance substantially equal to the average of the resistors Rmin and Rmax of the resistive elements of the non-volatile memory. For example, the reference resistive element is a magnetic tunnel junction which is permanently programmed in the antiparallel state, and which is dimensioned such that its resistance in this state is substantially equal to (Rmin + Rmax) / 2 . Figure 8 schematically illustrates a nonvolatile memory device 800 according to another embodiment. As in the embodiment of FIG. 1, the device 800 comprises a current mirror having a branch comprising a transistor 112 coupled to a reference current generating block 115. However, rather than having another branch coupled to the resistive memory 101, there is a plurality of L other branches, each comprising a corresponding transistor 110_1 to 110_L having its count node coupled to the control node of the transistor 112. Each other branch is coupled to a corresponding resistive memory 101_1 to 101_L , and a corresponding block 802_1 to 802L. Each of the blocks 802_1 to 802_L comprises, for example, the current integrator 122 and the comparator 124 of FIG. 1, to generate corresponding signals BIT1 to BITL. Each of the blocks 802 1 to 802_L receives a reference voltage VREF, which is for example equal to the voltage on the line 114 of the reference branch, or receives the reference voltages VREF1 and / or VREF2 used by the current integrator 122 and the comparator 124 of the blocks 802_1 to 802_L. FIGS. 9A and 9B illustrate the spin transfer torque (STT) resistive element structures according to an exemplary embodiment. For example, the resistive element 102 described herein has a structure corresponding to that of FIGS. 9A or 9B. Alternatively, as previously mentioned, the resistive elements could be RAM Red0x elements, FeRAM elements, PC RAM elements, or other types of resistive elements having a resistive element. programmable resistor. Figure 9A illustrates a resistive element STT 900 having a magnetic in-plane anisotropy. The element 900 is for example substantially cylindrical, but has a section which is non-circular, for example oval, which leads for example to an increase in the retention stability of the resistive elements when the device is programmed. Element 900 comprises lower and upper electrodes 902 and 904, each substantially disk-shaped, and sandwiching therebetween a number of intermediate layers. The intermediate layers comprise, from bottom to top, a fixed layer 906, an oxidation barrier 908 and a storage layer 910.
    [0005] The oxidation barrier 908 consists for example of MgO or Al x Oy. The fixed layer 906 and the storage layer 910 are for example made of ferromagnetic material, such as CoFe. The spin direction of the fixed layer 906 is fixed, as shown by an arrow from left to right in FIG. 9A. Of course, in alternative embodiments, the spin direction could be from right to left in the fixed layer 906. However, the spin direction in the memory layer 910 can be changed, as shown by arrows in opposite directions in Figure 9A. The spin direction is programmed by the direction of the write current I passed through the element, so that the spin direction in the storage layer is parallel, in other words is in the same direction , or is antiparallel, in other words is in the opposite direction, relative to that of the fixed layer 906. Figure 93 illustrates an STT resistive element 920 having a magnetic anisotropy perpendicular to the plane. Such a resistive element may for example be programmed by a lower write current I than the element 900 for a given size and / or for a given storage layer volume. An element, for example, is for example used in the memory cell 900 of FIG. 9, where a relatively low write current is desirable. The element 920 is substantially cylindrical, and has for example a circular section. Element 920 comprises lower and upper electrodes 922 and 924, each substantially disk-shaped and sandwiching a number of interlayers. The intermediate layers comprise, from bottom to top, a fixed layer 926, an oxidation barrier 928, and a storage layer 930. These layers are similar to the corresponding layers 906, 908 and 910 of the element 900, except that the fixed layer 926 and the storage layer 930 have anisotropy perpendicular to the plane, as represented by the vertical arrows 15 in the layers 926 and 930 of FIG. 9E. The fixed layer 926 is shown to have a bottom-to-top spin direction in FIG. 9B, but of course, in alternative embodiments, this spin direction could be from top to bottom. If the STT element 900 or 920 of FIG. 9A or 9B is used to implement each of the resistive elements 202, 204 described herein, their orientations may for example be chosen so as to minimize the level of write current which allows programming them. In particular, depending on factors such as the dimensions of the elements 202, 204, a low write current can be obtained when each element has its lower electrode 902, 922 connected to the corresponding storage node 206, 210, or reverse. An advantage of the embodiments described herein is that the readout circuit permits accurate detection of the read current flowing in the resistive element during a read operation. Thus, the programmable resistive states of the resistive elements forming the resistive memory may have relatively similar resistances, which may result in a compact, low energy consumption circuit.
    [0006] With the description thus given of at least one illustrative embodiment, various alterations, modifications and improvements will readily occur to those skilled in the art. B13636 - BD15664 - D107627-01 For example, it will be apparent to those skilled in the art that the supply voltage VDD in the various embodiments could be at any level, for example between 1 and 3 V, and rather than being at 0. V, the ground voltage could also be considered as a supply voltage which could be at any level, such as a negative level. In addition, it will be apparent to those skilled in the art that the rows and columns described herein are interchangeable, in other words that the rows could be considered columns, and vice versa.
    [0007] Furthermore, it will be apparent to those skilled in the art that in all the embodiments described herein, all NMOS transistors could be replaced by PMOS transistors and / or all PMOS transistors could be replaced by transistors. NMOS. The manner in which all the circuits 20 could be implemented using only PMOS transistors or only transistors clearly to those skilled in the art, for example feeder rails. In addition, although transistors based on MOS technology have been described here, in alternative embodiments, other transistor technologies could be used, which is compatible with bipolar technology. In addition, it will be clear to those skilled in the art that the various elements described in connection with the various embodiments could be combined, in alternative embodiments, in any combinations. NMOS will appear by inverting the
    权利要求:
    Claims (16)
    [0001]
    REVENDICATIONS1. A read circuit for reading a programmed resistive state of resistive elements (102) of a resistive memory (101), each resistive element being programmable to take one of a first and a second resistive state (Rmax, Rmin ), the circuit comprising a current integrator (122) adapted to integrate a current difference between a read current (IR) passing through a first of the resistive elements and a reference current (IREF). 10
    [0002]
    The readout circuit of claim 1, wherein the current integrator (122) comprises a capacitive transimpedance amplifier (CTIA).
    [0003]
    The readout circuit of claim 1 or 2, further comprising a current mirror (108) comprising a first branch (112, 114) adapted to conduct the reference current (IREF), and a second branch (110, 114) 107) coupled to: a first line (105) coupled to the first resistive element (102) for driving the read current (IR); and a second line (120) co-Lipled to the current integrator (122) to drive the difference between the read current (IR) and the reference current (IREF) -
    [0004]
    The readout circuit of any one of claims 1 to 3, wherein the current integrator (122) comprises a differential amplifier (202) having: a first input node coupled to the second line (120) ; a feedback path comprising a capacitor (204) coupled between an output node of the differential amplifier and the first input node; and a second input node coupled to a first reference voltage (VREF2).
    [0005]
    The readout circuit of claim 4, wherein the first branch (112,114) of the current mirror (108) is coupled to a reference current generating block (115), and wherein the second input node of the differential amplifier (202) is coupled to the first branch (112, 114).
    [0006]
    A read circuit as claimed in any one of claims 1 to 5, further comprising a selection and bias circuit (104A, 1043) for selecting the first resistive element and applying a bias voltage (VpoL) to the first resistive element , the selection and biasing circuit (104A, 1043) comprising a first transistor (412, 602, 608) coupled to the first resistive element (102) and adapted to conduct the read current, the first transistor having a coupled control node to the bias voltage (VPOL) -
    [0007]
    The readout circuit of claim 6, wherein the first transistor (412) is a NOS transistor, and the select and bias circuit (104A, 104B) further comprises: a second conduction coupled transistor (416). main between the grid of the first 20 a mass level; and its transistor nodes and a third main conduction coupled transistor (418) between a source of the first ground level. its transistor nodes and
    [0008]
    The readout circuit of claim 6, wherein the selection and biasing circuit (104A, 104B) further comprises another transistor (604, 606) coupled in series with the first transistor (602, 608).
    [0009]
    A read circuit according to claim 8, wherein the first transistor (412) is a N-channel MOS transistor, and wherein the other transistor is a P-channel NOS transistor having its source coupled to a drain of the first transistor .
    [0010]
    The readout circuit of any one of claims 1 to 9, wherein the reference current (IREF) is generated by a reference current generation block (115) comprising a matrix of K by K resistive elements, K being a positive integer greater than or equal to 2.
    [0011]
    11. Read circuit according to claim 10, wherein the matrix of resistive elements comprises K rows of resistive elements, the resistive elements of each row being coupled in parallel with each other, the rows of resistive elements being coupled in series. between them, and wherein the resistive elements in one half of the rows are programmed to have the high resistive state, and the resistive elements in the other half of the rows are programmed to have the low resistive state.
    [0012]
    The readout circuit of any one of claims 1 to 9, wherein the reference current (TREF) is generated by a reference current generating block (115) comprising a scaled and programmed reference resistive element. so that its resistance is at a level between the resistors of the first and second resistive states of each resistive element.
    [0013]
    The readout circuit of any one of claims 1 to 12, wherein the resistive memory (101) comprises a plurality of resistive element columns, and wherein the read circuit comprises a current integrator (122). for each column, and a reference current generation block (115) common to the plurality of columns. 25
    [0014]
    A read circuit as claimed in any one of claims 1 to 13, wherein each of the resistive elements is of one of the following types: a spin transfer torque element having anisotropy in the plane; A spin transfer torque element having anisotropy perpendicular to the plane; an oxidation-reduction element (Red0x); a ferroelectric element; and a phase change element.B13636 - BD15664 - D107627-01 23
    [0015]
    A method for reading a programmed resistive state of resistive elements (102) from a resistive memory (101), each resistive element being programmable to take one of a first and a second resistive state, the method comprising : select a first of the resistive elements; and integrating, by a current integrator (122), a current difference between a read current (IR) passing through a first one of the resistive elements, and a reference current (IREF).
    [0016]
    The method of claim 15, wherein the reference current (IREF) is generated by a reference branch (112, 114) of a current mirror (108), and the integration of the current difference is based on a reference voltage (VREF2) of the reference branch.
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    同族专利:
    公开号 | 公开日
    EP3227889A1|2017-10-11|
    US10304529B2|2019-05-28|
    WO2016087763A1|2016-06-09|
    FR3029342B1|2018-01-12|
    US20170271005A1|2017-09-21|
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    法律状态:
    2015-12-23| PLFP| Fee payment|Year of fee payment: 2 |
    2016-06-03| PLSC| Publication of the preliminary search report|Effective date: 20160603 |
    2016-12-29| PLFP| Fee payment|Year of fee payment: 3 |
    2018-01-02| PLFP| Fee payment|Year of fee payment: 4 |
    2019-12-30| PLFP| Fee payment|Year of fee payment: 6 |
    2020-12-28| PLFP| Fee payment|Year of fee payment: 7 |
    2021-12-31| PLFP| Fee payment|Year of fee payment: 8 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1461717|2014-12-01|
    FR1461717A|FR3029342B1|2014-12-01|2014-12-01|READING CIRCUIT FOR RESISTIVE MEMORY|FR1461717A| FR3029342B1|2014-12-01|2014-12-01|READING CIRCUIT FOR RESISTIVE MEMORY|
    PCT/FR2015/053273| WO2016087763A1|2014-12-01|2015-12-01|Reading circuit for resistive memory|
    EP15810692.2A| EP3227889A1|2014-12-01|2015-12-01|Reading circuit for resistive memory|
    US15/531,782| US10304529B2|2014-12-01|2015-12-01|Reading circuit for resistive memory|
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