• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention relates to a method for detecting a wiring fault of a capacitive sensor (1), such as a knock sensor, connected by a passive type acquisition interface (5) to a communication port. (P1) configurable either in input mode or in output mode of a computer (2). According to the invention, the communication port (P1) is configured in output mode, and a voltage slot Vn is generated for a period of time Tc adapted to charge at least partially the capacitors (C6, C7, C8a, C8b, C10 ) of the acquisition interface (5) and the capacitive sensor (1), and then the communication port (P1) is switched into its input mode, so as to acquire at least one data representative of the voltage of the capacitors and the capacitive sensor, and finally comparing these data with reference data previously stored, so as to conclude a wiring fault in the absence of correspondence between said data.
    公开号:FR3026842A1
    申请号:FR1459372
    申请日:2014-10-01
    公开日:2016-04-08
    发明作者:Jacques Rocher
    申请人:Continental Automotive GmbH；Continental Automotive France SAS；
    IPC主号:
    专利说明:

    [0001] The invention relates to a method for detecting a wiring fault of a capacitive sensor, such as a knock sensor, connected, by a passive type acquisition interface comprising capacitors, to a configurable communication port or in a input is in output mode, a calculator.
    [0002] In order to detect the wiring faults of capacitive sensors such as knock sensors, a current solution described in particular in patent FR 2 912 814 consists of a method according to which: a periodic reference signal is applied to the terminals of the capacitive sensor by means of a square periodic signal generator permanently connected to said capacitive sensor, the capacitance is measured across the capacitive sensor, and the measured capacitance is compared with a nominal capacitance. In practice, such a technique is found to reliably detect short circuit wiring faults and open circuit.
    [0003] However, this technique requires adding to each capacitive sensor and its acquisition interface, the constraints relating to the production and routing of a periodic signal. The present invention aims to overcome this drawback and its main purpose is to provide a method for detecting wiring faults of a capacitive sensor connected by a passive acquisition interface to a computer, requiring no material subjection (neither component nor additional cabling) for implementation. Another object of the invention is to provide a method of detection of wiring faults applicable without hardware modification on current computers. For this purpose, the invention is directed to a method for detecting a wiring fault 25 of a capacitive sensor, such as a knock sensor, connected, by a passive type acquisition interface comprising capacitors, to a port of communication configurable either in input mode or in output mode of a computer, and according to the invention, this method is characterized in that: in a preliminary calibration phase, it is delivered to the acquisition interface, during a charging time Tc, a voltage slot Vn adapted to charge at least partially the capacitors of said acquisition interface and the capacitive sensor, and then acquiring and memorizing at least one datum, called reference datum, representative, after minus a time interval tm 0 following the interruption of the voltage slot, the voltage of said capacitors and capacitive sensor in the absence of a wiring fault, and it implements detection procedures of wiring faults consisting of: - configuring the communication port in output mode, and generating a voltage slot Vn during a charging time Tc, - switching the communication port in its input mode at the end of the charging time Tc, and acquiring at least one piece of data, called representative measured data, after each lapse of time tm 0 following the interruption of the voltage slot, the voltage of the capacitors and the capacitive sensor, and comparing each measured data item with the data corresponding reference, so as to conclude to a wiring fault of the capacitive sensor in the absence of coincidence between said data. Thus, according to the invention, the voltage slot is generated by the computer on a communication port configured in output mode, which is then switched to input mode for acquisition of data representative of the capacitor load of the interface. acquisition and capacitive sensor. The method according to the invention therefore makes it possible to establish a diagnosis of capacitive sensors by means of a simple software adaptation of existing computers, without requiring the addition of electronic components or the creation of additional wire links. According to a first advantageous embodiment of the invention, the reference and measurement data are acquired during the interruption of the voltage slot so as to compare reference and measurement data representative of the charging voltage. capacitors and capacitive sensor after generating said voltage range. According to a second advantageous embodiment of the invention, the reference and measurement data are acquired after a lapse of time tm> 0 following the interruption of the voltage slot, so as to compare reference data and data. representative of the discharge voltage of the capacitors and the capacitive sensor. According to this second embodiment, in addition, data representative of the time constant of the voltage during the discharge of the capacitors and of the capacitive sensor are advantageously acquired according to the invention. Furthermore, the method according to the invention applies, firstly, to the capacitive sensors connected in common mode, and makes it possible to detect the wiring faults of the wired connection connecting the capacitive sensor to the communication port.
    [0004] This method also applies to capacitive sensors cabled in differential mode by means of an acquisition interface comprising two branches each connecting a terminal of said capacitive sensor to a configurable communication port either in input mode or in output mode.
    [0005] For this application, moreover, several strategies can be implemented. A first strategy can thus advantageously consist in splitting each detection procedure into two successive steps consisting of a first step in which a voltage slot Vn is generated on one of the communication ports, while Another communication port is grounded, and in a second step in which the role of the two communication ports is reversed. A second strategy may advantageously according to the invention, generate, either simultaneously or with a time shift, a voltage slot Vn, respectively during load times Here and Tc2, on each of the two communication ports, and acquiring, for each of said two communication ports, the data representative of the voltage of the capacitors and of the capacitive sensor respectively at the end of the charging times I and Ic2. According to this principle, furthermore, information derived from the processing of data acquired on either communication port can be independently processed, or correlated. Furthermore, during the preliminary calibration phase, and advantageously according to the invention, reference data representative of the voltage of the capacitors and of the capacitive sensor are acquired and stored for various types of wiring faults. way to distinguish said wiring faults. Other features and advantages of the invention will become apparent from the detailed description which follows with reference to the accompanying drawings which represent by way of non-limiting example an advantageous embodiment. In these drawings: FIG. 1 is a schematic representation of a device for implementing the method according to the invention, comprising a capacitive sensor and means for acquiring and processing the signals delivered by this capacitive sensor, FIG. 2a represents a voltage slot Vn as generated on a communication port 35 in accordance with the method according to the invention; FIG. 2b represents a curve of the voltage of the capacitors and of the capacitive sensor, obtained in the absence of the wiring fault, during the generation of the voltage slot Vn shown in FIG. 2a, and FIG. 2c represents a curve of the voltage of the capacitors and of the capacitive sensor, obtained, in the presence of a wiring fault, when the generation of the voltage slot Vn shown in Figure 2a. The device shown diagrammatically in FIG. 1 consists of a device for acquiring and processing the measurement signals delivered by a capacitive sensor 1, of the knock sensor type, wired in a differential mode.
    [0006] This acquisition and processing device consists of a computer 2 comprising, firstly, a microcontroller 3 connected to a voltage source Vn by a power supply circuit 4 having a power supply buffer 4a. This microcontroller 3 is equipped, in a conventional manner, with a plurality of communication ports, including two communication ports Pi, P2, represented in FIG. 1, dedicated to the connection with the capacitive sensor 1. The calculator 1 also comprises a passive interface 5 for acquiring the signals delivered by the capacitive sensor 1. This acquisition interface 5 comprises two main branches 6,7 each connecting one of the terminals 1a, 1b of the capacitive sensor 1 to one of the ports communication P1, P2, and on each of which 20 are connected in series a capacitor C6, respectively C7, and a resistor R6, respectively R7. The acquisition interface 5 also comprises three secondary branches 8, 9, 10 each extending between the two main branches 6, 7, and consisting of: a first secondary branch 8 (furthest from the microcontroller 3) on which are connected in series two capacitors C8a, C8b disposed on either side of a central connection connected to ground, - a second median secondary branch 9 on which is mounted a resistor R9, connecting the two main branches 6, 7 at two points of the latter 30 located between the first branch 8 and the capacitors C6, C7, and a third secondary branch 10 (closest to the microcontroller 3) on which a capacitor C10 is mounted, connecting the two main branches 6, 7 at two points of the latter separated from the median secondary branch 9, respectively by the capacitor C6 and the resistor R6 and by the capacitor C7 and the resistor R7. Moreover, each communication port P1, P2 of the microcontroller 3 consists of a configurable digital communication port either in input mode for the purpose of acquiring a signal, or in level 1 output mode (potential equal to Vn) or level 0 (grounding the communication port). The method according to the invention aims at detecting wiring faults of the capacitive sensor 1, and for this purpose, according to a first embodiment, this detection method consists of splitting each detection procedure into two successive stages. similar consisting of: - a first step in which a voltage slot Vn is generated during a time Tc on one of the communication ports Pi, while the other communication port P2 is grounded, and configured for this purpose in level 0 output mode, - a second step in which the role of the two communication ports Pi, P2 is reversed. According to this principle, the calibration phase consists, as a preliminary step, in generating, for a period of time Tc, in one of the main branches 6 or 7 of the "guaranteed" acquisition interface 5 without a wiring fault, a slot Vn voltage shown in Figure 2a, adapted, as shown in Figure 2b, to obtain an at least partial charge capacitors 06, 07, C8a, C8b, 01 0, and the capacitive sensor 1, followed by a discharge said capacitors and capacitive sensor after interruption of said voltage slot. This preliminary phase then consists in acquiring and storing, one or more representative reference data (s): - the charging voltage of the capacitors of the acquisition interface 5 and the capacitive sensor 1 during the interrupting the voltage slot V n, and / or the voltage (s) for discharging the capacitors of the acquisition interface 5 and of the capacitive sensor 1, after one (of) time period t m> 0 following the interrupting the voltage slot Vn, one of said data consisting, for example, of a data representative of the time constant. According to the same principle as that developed above, this preliminary calibration phase can also include the acquisition and storage of data representative of the voltage of the capacitors 06, 07, 08a, 08b, 010 and of the capacitive sensor 1 for different types of wiring faults, so as to distinguish said data wiring faults. Once this calibration step has been performed, the first step of each detection procedure consists, as mentioned above, in configuring one of the communication ports, for example P2, in the level 0 output mode (grounding of this port of communication P2), and to implement a procedure consisting in: - configuring the other communication port P1 in level 1 output mode (potential of the communication port P1 equal to Vn), so as to generate a voltage slot of value Vn during a period of time Tc identical to the time Tc of the voltage slot during the preliminary calibration phase, - then switching the communication port P1 in its input mode, and acquiring measured data corresponding to the stored reference data, and finally comparing the measured data and the stored data, so as to conclude either that there is no wiring fault of the capacitive sensor 1 or that there is a wiring fault in the short-circuit type, or an open-circuit type wiring fault.
    [0007] By way of example, FIG. 2c represents the curve of the voltage of the capacitors of the acquisition interface 5 and of the capacitive sensor 1, obtained, in the presence of a wiring fault, during the generation of the voltage slot. Vn. The comparison of this curve with the curve of FIG. 2b showing the curve of the voltage in the absence of wiring faults, reveals very significant differences, in particular concerning the time constants of these voltages, which make it possible to diagnose without ambiguity a wiring fault. The detection procedure then comprises a second step during which, as mentioned above, the role of the communication ports Pi, P2 is reversed, and thus consisting in configuring the communication port Pi, in the output mode of level 0, and applying to the other communication port P2 a procedure identical to that described above. It should be noted, moreover, that each of the steps described above makes it possible, when it is applied to a capacitive sensor wired in common mode, to detect the wiring faults of the wired link connecting this capacitive sensor to the port of 25. communication. Moreover, a second strategy for detecting wiring faults of a capacitive sensor 1 cabled in differential mode consists, according to the invention, in place of the execution of the two aforementioned successive steps, to be generated, either simultaneously or with a time shift, a voltage slot Vn, respectively during charging times Here and Tc2, on each of the two communication ports P1 and P2, then to acquire, for each of said two communication ports, the data, representative of the voltage of the capacitors of the acquisition interface 5 and the capacitive sensor 1 respectively at the end of the charging times Here and 1c2. According to this principle, advantageously, the information derived from the processing of the data acquired on the one and the other communication ports P1 and P2 can be processed independently, or be correlated, so that a large number of Opportunities are available for the selection of meaningful reference data to diagnose wiring faults and to distinguish between different types of wiring faults. By implementing either two successive detection steps, or a single step, the method according to the invention therefore makes it possible, without requiring the addition of electronic components or the creation of additional wire links, to detect all the faults. wiring that may affect the operation of a capacitive sensor 1 wired in differential mode, and distinguish the different types of wiring faults.
    权利要求:
    Claims (7)
    [0001]
    REVENDICATIONS1. Method for detecting a wiring fault of a capacitive sensor (1), such as a knock sensor, connected by a passive-type acquisition interface (5) comprising capacitors (06, 07, C8a, C8b, 010), to a communication port (P1) configurable either in input mode or in output mode, of a computer (2), characterized in that: - in a preliminary calibration phase, it delivers to the interface d acquisition (5), during a charging time Tc, a voltage slot Vn adapted to charge at least partially the capacitors (06, 07, 08a, 08b, 010) of said acquisition interface and the capacitive sensor (1 ), then one acquires and stores at least one datum, called reference datum, representative, after at least a lapse of time tm 0 following the interruption of the voltage slot, the voltage of said capacitors and capacitive sensor in the absence wiring fault, and dice detection procedures are implemented. cabling faults 15 consisting of: - configuring the communication port (P1) in output mode, and generating a voltage slot Vn during a charging time Tc, - switching the communication port (P1) in its input mode to the end of the charging time Tc, and acquiring at least one piece of data, known as measured data, representative, after each lapse of time tm 0 following the interruption of the voltage slot, of the voltage of the capacitors (06, 07, 08a, 08b, Cl 0) and the capacitive sensor (1), and to compare each measured data with the corresponding reference data, so as to conclude that the capacitive sensor (1) has a wiring fault in the absence of a coincidence between said data.
    [0002]
    2. Detection method according to claim 1 characterized in that one acquires the reference and measurement data during the interruption of the voltage slot, so as to compare reference and measurement data representative of the voltage of the charging capacitors (06, 07, 08a, 08b, C10) and the capacitive sensor (1) after generating said voltage pulse.
    [0003]
    3. Detection method according to claim 1, characterized in that the reference and measurement data are acquired after a lapse of time tm> 0 following the interruption of the voltage slot, so as to compare reference data and demesure representative of the discharge voltage of the capacitors (06, 07, C8a, C8b, 01 0) and of the capacitive sensor (1).
    [0004]
    4. Detection method according to claim 3, characterized in that a datum representative of the time constant of the voltage is acquired during the discharge of the capacitors (06, 07, C8a, C8b, 010) and the capacitive sensor. (1).
    [0005]
    5. Detection method according to one of claims 1 to 4 characterized in that, in the preliminary phase, one acquires and stores also reference data representative of the voltage of the capacitors (06, 07, 08a, 08b, 01 0) and the capacitive sensor (1) for different types of wiring faults, so as to make it possible to distinguish said wiring faults.
    [0006]
    6. Method according to one of the preceding claims for detecting wiring faults of a capacitive sensor (1) wired in differential mode by means of an acquisition interface (5) comprising two branches (6,
    [0007]
    7) each connecting a terminal (1a, 1b) of said capacitive sensor to a communication port (P1, P2), characterized in that each detection procedure is divided into two successive stages consisting of a first step during of which one voltage slot Vn is generated on one of the communication ports (P1), while the other communication port (P2) is grounded, and in a second step during which the role of the two ports of communication (P1, P2) is reversed. 7. Method according to one of claims 1 to 5 for detecting wiring faults of a capacitive sensor (1) wired in differential mode by means of an acquisition interface (5) comprising two branches (6, 7). ) each connecting a terminal (1a, 1b) of said capacitive sensor to a communication port (P1, P2), characterized in that a voltage slot Vn, 25 respectively, is generated, either simultaneously or with a time offset. during charging times Tc1 and Tc2 on each of the two communication ports (P1, P2), and in that for each of said two communication ports the data representing the voltage of the capacitors (06, 07, 08a, 08b, 010) and the capacitive sensor (1) respectively at the end of the charging times Tcl and Tc2.
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    法律状态:
    2015-10-23| PLFP| Fee payment|Year of fee payment: 2 |
    2016-04-08| PLSC| Publication of the preliminary search report|Effective date: 20160408 |
    2016-10-20| PLFP| Fee payment|Year of fee payment: 3 |
    2017-10-24| PLFP| Fee payment|Year of fee payment: 4 |
    2018-10-22| PLFP| Fee payment|Year of fee payment: 5 |
    2019-10-28| PLFP| Fee payment|Year of fee payment: 6 |
    2020-10-21| PLFP| Fee payment|Year of fee payment: 7 |
    2021-04-16| TP| Transmission of property|Owner name: VITESCO TECHNOLOGIES, DE Effective date: 20210309 |
    2021-10-21| PLFP| Fee payment|Year of fee payment: 8 |
    2022-02-11| CA| Change of address|Effective date: 20220103 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1459372A|FR3026842B1|2014-10-01|2014-10-01|METHOD FOR DETECTING A WIRING DEFECT OF A CAPACITIVE SENSOR|FR1459372A| FR3026842B1|2014-10-01|2014-10-01|METHOD FOR DETECTING A WIRING DEFECT OF A CAPACITIVE SENSOR|
    CN201510635148.7A| CN105486967B|2014-10-01|2015-09-30|Method for detecting the line fault in capacitance type sensor|
    US14/872,720| US9835667B2|2014-10-01|2015-10-01|Method for detecting a wiring fault in a capacitive sensor|
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