• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The doping method of a GaN-based semiconductor comprises a first step of providing a substrate (1) comprising a layer of GaN-based semiconductor material (1b) covered by a mask (3) based on of silicon. The method comprises a second step of impurity implantation (2) in the mask (3) so as to transfer additional doping impurities (4) of Si type by diffusion from the mask (3) to the semi-material layer. driver (1b). A heat treatment is then configured to activate the doping impurities (2) and the additional doping impurities (4).
    公开号:FR3026557A1
    申请号:FR1459130
    申请日:2014-09-26
    公开日:2016-04-01
    发明作者:Claire Agraffeil
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] FIELD OF THE INVENTION The invention relates to a method for ion implantation and activation of doping impurities in a GaN-based semiconductor. State of the art Ion implantation is commonly used to dope semiconductors. To make p-n junctions, masks are generally used to select areas of the semiconductor to be implanted and areas to be protected. The implantation step is then carried out, using ions generally produced from a gaseous or solid source (source used for Mg for example), which impact the semiconductor after having been accelerated to an energy understood for example between 10 and 500 keV. The nature of the implanted ions is chosen according to the type of doping that one wishes to obtain. Mg + ions are used, for example, to carry out p-doping (excess holes) in GaN-based semiconductors, whereas Si + ions are often used to perform n-doping (excess of electrons) of the same type of semiconductor. The semiconductor is then subjected to heat treatment in order to more or less effectively activate the doping impurities. 302 6 5 5 7 2 The document "Implanted pn junctions in GaN" (XA Cao et al., Solid-state Electronics, 43 (1999) 1235-1238) discloses a method for implanting Si + ions in a semi- GaN-type doped conductor doped with Mg ions, in order to obtain an n + / p doped semiconductor. Here the Si + ions are implanted in selected areas by means of a mask deposited on the semiconductor. The mask is removed after implantation, then an AlN layer is sputtered onto the semiconductor to protect the semiconductor during the dopant activation heat treatment. The document "Experimental and numerical investigation of the electrical characteristics of vertical diodes created by Si implantation into p-GaN" (A. Baharin, Institute of Electrical and Electronics Engineers, 978-14244-2717-8 / 08, (2008). )) describes a method of manufacturing vertical pn junctions from p / p + doped GaN semiconductors using Mg + ions. Here, Si + ions are implanted by means of beams of ions of different energies, to control the depth of implantation in the semiconductor. OBJECT OF THE INVENTION An object of the invention is to provide an alternative to the methods of the prior art for doping a semiconductor, in particular for the purpose of manufacturing p-n junctions. This problem is solved by means of a method which comprises the following steps: - providing a substrate comprising a layer of GaN-based semiconductor material covered by a silicon-based mask, - implanting impurities in the mask in order to transfer Si-type doping impurities by diffusion from the mask to the GaN-based semiconductor material layer; - to carry out a heat treatment configured to activate the doping impurities. According to one aspect of the invention, the mask may partially cover the substrate so as to define an area covered by the mask and a discovery zone, the implantation being performed with Mg + ions to dope the uncovered area of the substrate. The method may also comprise a step of depositing a protective layer produced before the heat treatment step. The material of the protective layer may be chosen from silicon oxide, or silicon nitride of the SixNy type, amorphous silicon, and compounds of the HfSix0y type, and preferably from aluminum oxide and nitride. 'aluminum. The deposition of the protective layer is carried out before the heat treatment step, and may for example be carried out after the step of implantation of the doping impurities and additional doping impurities, directly on the mask, or after withdrawal of the latter . Alternatively, it is conceivable to deposit the protective layer before implantation of the doping impurities in the case where the protective layer is not based on silicon. After the heat treatment, the protective layer can advantageously be removed. Preferably, the implantation step may be carried out at a temperature of between 15 and 700 ° C., preferably between 450 and 600 ° C. In addition, the heat treatment step may advantageously comprise a combination of at least two anneals of different durations and temperatures. At least one of the anneals may also be carried out at a temperature above 1000 ° C. As regards the mask, it may advantageously have a thickness of between 2 and 400 nm. The thickness of the semiconductor material layer can be between 5 nm and 10 μM, preferably between 500 nm and 1 μm, ideally equal to 1 μm. BRIEF DESCRIPTION OF THE DRAWINGS Other advantages and features will become more clearly apparent from the following description of particular embodiments of the invention given by way of nonlimiting example and represented in the accompanying drawings, in which FIGS. schematically illustrate one embodiment of the doping method of a GaN-based semiconductor. DETAILED DESCRIPTION According to a first embodiment of the doping method shown in FIGS. 1 to 10, provision must first be made for a substrate 1 such as that represented in FIG. 1. This substrate comprises a support for example in silicon or sapphire, A1203, SIC, and a layer of semiconductor material Ib based on GaN. Alternatively, the substrate 1 may be solid GaN. When the substrate 1 is a block of solid GaN, it is possible to cover the rear face with protective layers which are advantageously identical to those deposited on the substrate 1 on the front face, and which will be described below. The front face of the substrate 1 is defined here as the face impacted by the doping impurities beam, and the rear face as the opposite face to the front face. The embodiment of the substrate 1 advantageously comprises a first cleaning step of the support 1a, for example a cleaning type RCA if the support is made of silicon. The layer of semiconductor material 1b is then manufactured by epitaxial growth directly on the support 1a. The choice of the material of the support is advantageously chosen to have mesh parameters similar to those of the layer of semiconductor material lb so that the latter increases in a coherent manner.
    [0002] To improve the quality of the semi-conductor material layer 1b, an AlGaN-based interlayer of at least 1 μm thickness may optionally be deposited on the support 1a before the epitaxial growth of the layer 1b (mode of not shown). For example, for a sapphire support, the GaN-based semiconductor layer Ib may be directly deposited on the support 1a if it is made of sapphire. However, if it is made of silicon, it is advisable to deposit a buffer layer based on AlGaN.
    [0003] When the production of the semiconductor material layer 1b is complete, it may advantageously have a thickness of between 100 nm and 10 μm, preferably between 5 nm and 1 μm, ideally equal to 1 μm.
    [0004] According to an advantageous embodiment, the semiconductor material Ib based on GaN is not initially doped or is not intentionally doped initially. This makes it possible simultaneously to carry out p and n doping during the ion implantation step, as will be seen below and to form a layer lb capable of forming complementary circuits with devices using an excess of electrons and devices. using an excess of holes. Alternatively, it is possible to use a layer of p-doped semiconductor material lb. In this embodiment, the doping impurities 2 can for example be Mg + ions, introduced directly during the epitaxial growth (see FIG. 1). In the second step of the embodiment, a mask 3 is made to cover all or part of the surface of the layer of semiconductor material 1b. This step of the method is shown in FIG. 2. As illustrated, the mask 3 may partially cover the substrate 1 so as to define a covered zone and an uncovered zone. This mask 3 can for example be made by photolithography or electronic lithography. Its thickness is advantageously between 2 and 400 nm. The mask material 3 is preferentially silicon based, silicon oxide and / or silicon nitride, amorphous silicon, or HfSiO 2. It therefore comprises Si atoms capable of diffusing into the substrate 1 when they are supplied with the necessary energy. This property makes it possible to implant Si atoms in the semiconductor material 1b and thus to carry out a local doping n.
    [0005] In a third step of the embodiment, a dopant implantation 2 is carried out on the mask 3 and on the uncovered zone of the substrate 1 (see FIG. The dopants 2 may be p-type, for example Mg, n-type ions, for example Si ions, or non-electrically active dopants such as N + ions. Conventionally, the implantation conditions are imposed on the one hand by the technical performance of the implantation equipment, and on the other hand by the concentration and location of the doping impurities 2 that it is desired to implant in the coating layer. semiconductor material 1 b. For example, for a Mg + ion beam having a fluence of 2.1015 atoms / cm 2 and an energy of 200 keV, the doping impurities 2 can be implanted in a GaN layer to a depth of the order of 400 nm with a peak concentration estimated at 160-180 nm. This depth is also called the average implantation depth or R. The implantation energy of the dopants 2 can be chosen so that, in the areas covered by the mask 3, the average implantation depth Rp is located: (i) in the mask 3 near the interface with the layer of semiconductor material 1b, or (ii) in the semiconductor material layer 1b near the interface with the mask 3, or (iii) deep within the layer of semiconductor material 1b.
    [0006] Whatever the implantation energy chosen, it is sufficient for the implanted dopants 2 to supply the energy necessary for the Si atoms present in the mask 3 to diffuse into the semiconductor material layer 1. dopants 2 are of type p, the areas which are not covered by the mask 3 are directly p-doped, whereas in areas covered by the mask, the p-type dopants provide the energy necessary for the Si atoms to diffuse. At the end of the ion implantation, the semiconductor material layer 1b comprises open areas provided with p-type doping impurities 2, and covered areas provided with both p-type doping impurities 2 and p-type doping impurities 2. n-type additional doping impurities 4, the residual doping in this zone being finally n-type doping (see FIG. 4).
    [0007] In the case of p-type dopants 2, it may be advantageous to choose the implantation energy so that the average implantation depth is located at the interface between the mask 3 and the semiconductor material layer 1b, or then close to this interface, either in the mask 3 or in the layer of semiconductor material 1b. After implantation, the p-type doping impurities 2 and the n-type additional doping impurities 4 are then situated in the so-called active zone of the semiconductor 1b, that is to say the depth used, for example, to make junctions or transistors. The active area of the semiconductor lb extends for example to 100 or 300 nm deep. Performing an implantation of Si through the mask 3 has the advantage of less degrading the surface of the semiconductor material layer 1b in comparison with a conventional implantation of Si.
    [0008] When the maximum implantation is located in the mask 3 or at the interface between the mask 3 and the semiconductor layer 1b, the energy provided by the dopants 2 is sufficient to allow the incorporation of the Si atoms of the mask 3 to the active area of the semiconductor material 1b. When the maximum implantation is located deep in the semiconductor layer 1b, the energy provided by the n-type dopants allow the Si atoms to diffuse into the layer 1b in a deeper zone.
    [0009] Performing implantation of non-electrically active dopants may be useful for producing a semiconductor material layer 1b that is n-doped in the semiconductor regions 1b covered by the mask 3, and undoped elsewhere. As for implantations of n-type or p-type, the implantation energy is chosen so as to allow the diffusion of Si atoms more or less deep in the semiconductor matrix 1b. The use of non-electrically active dopants can give rise to the repair of gaps which are either created by the diffusion of the Si atoms, or already present in the semiconductor material layer 1b.
    [0010] According to one aspect of the invention, it may be advantageous to control the temperature at which the ion implantation is performed. Preferably, the latter can be carried out at a temperature in a range from 15 ° C to 700 ° C, preferably between 200 ° C and 600 ° C, and preferably between 450 ° C and 600 ° C. For this, one can advantageously use a system for heating the rear face of the support 1a, for example of the Peltier effect module type. The fact of carrying out heating of the substrate during the ion implantation step allows both a better diffusion of the dopants in the semiconductor material layer 1b, and a better diffusion of the Si atoms from the mask 3 to the semiconductor material layer 1b. According to a particular embodiment of the method (not shown), the mask 3 can be removed after the ion implantation step, before carrying out a heat treatment of the substrate 1. The withdrawal can for example 302 6 5 5 7 It can be produced by wet etching using hydrofluoric acid (HF) if the mask is SiO2 or phosphoric acid (H3PO4) if the mask is SiNx or AlN. Advantageously, to activate the doping impurities 2 and the additional doping impurities 4, the substrate 1 can be annealed at an elevated temperature, for example greater than 1000 ° C. However, beyond a temperature of the order of 850 ° C., the GaN-based semiconductor material layer 1b is highly degraded and a part of the nitrogen evaporates. It is therefore advantageous to carry out a step of depositing a protective layer 5 after the step of implantation of doping impurities 2 and additional doping impurities 4, and before carrying out the heat treatment. The protective layer 5 serves to greatly limit the degradation of the surface of the semiconductor layer I b. This step of the process is shown in FIG. 5. The material of the protective layer 5 may be chosen from aluminum oxide, aluminum nitride, silicon nitride of the SixNy type or silicon oxide. or compounds of the type HfSix0y. Preferably, the material of the protective layer 5 of aluminum nitride. The deposit may, for example, be a metalorganic chemical vapor deposition ("MOCVD") in an equipment identical to that used for the epitaxial growth of the semiconductor material layer. I b. The deposition can also be achieved by a low pressure chemical vapor deposition ("LPCVD" or "low pressure chemical vapor deposition"). It is advisable to deposit an aluminum nitride protective layer 5 because the mesh parameters of this material are very close to those of the gallium nitride semiconductor material, which makes it possible to increase the adhesion. of the protective layer 5 on the substrate 1. It is also possible to replace the AlN with AlGaN, or with a stack of AlN and AlGaN layers. In this case, the AlGaN layer may comprise up to 50% Ga, advantageously up to 20% Ga, and preferably less than 5% Ga.
    [0011] According to a preferred embodiment, the protective layer 5 may have a thickness of between 1 and 200 nm, and more precisely between 1 and 100 nm. This thickness is sufficient to create an effective barrier to prevent the evaporation of the nitrogen molecules of the semiconductor material layer 1b during the heat treatment.
    [0012] The heat treatment step illustrated schematically in FIG. 6 may comprise rapid annealing ("Rapid Thermal Annealing" or "RTA" and "Rapid Thermal Processing" or "RTP" in English) so that the activation rate of doping impurities 2 and additional doping impurities 4 is high without the surface of the semiconductor layer 1b being damaged. Standard anneals ("Furnace Annealing" in English) may also be made to allow effective diffusion of the doping impurities 2 and additional doping impurities 4 in the semiconductor layer 1b in the substitutional position. During the heat treatment step, it is therefore possible to perform standard annealing, rapid annealing, or any combination of fast and standard annealing depending on the result that is desired. At least one of the anneals may advantageously be carried out at a temperature greater than 1000 ° C. in order to obtain a high level of activation of the doping impurities 2 and additional doping impurities 4.
    [0013] By way of illustration, standard annealing at a temperature of between 850 and 1250 ° C. can be carried out for a duration ranging from a few minutes to a few hours. Rapid annealing can also be performed in a temperature range of 850 to 1250 ° C, or even up to 1600 ° C if the support is in sapphire. In this case, the duration of the fast annealing is between a few seconds and a few minutes. Advantageously, the annealing (s) can be carried out under a controlled atmosphere containing a gas advantageously chosen from N 2, Ar, He, NF 3, O 2, or a mixture of N 2 / O 2, N 2 / H 2, Ar / H 2.
    [0014] The inventors have observed that the heat treatment makes it possible to increase the diffusion of the Si dopants in the direction of the semiconductor material layer 1b. For example, for an annealing carried out at 1100 ° C., the concentration of n-type dopant impurities 4 increases as the duration of the heat treatment is long.
    [0015] Moreover, the heat treatment makes it possible to activate the doping impurities 2 and the additional doping impurities 4. Knowing that the atomic radius of the silicon atoms is 1.17 Å, that of the gallium atoms is 1.26 Å, and that that of the Magnesium atoms is 1.36 Å, it is argued that silicon atoms are more easily placed in substitutional position in semiconductor material layer lb than magnesium atoms. Therefore, the activation rate of the Si impurities is higher than the activation rate of the Mg impurities in the area covered by the mask 3 (see FIG. 7). The inventors have observed that the the activation of n-type dopants (Si impurities) can reach 100%, whereas the activation rate of p-type dopants (Mg impurities) is between 5 and 60%.
    [0016] Following the heat treatment, the mask 3 and the protective layer 5 can be removed (see Figures 8 and 9). It is possible, for example, to perform a wet etching with phosphoric acid for the protective layer if the latter is in AlN or SiNx, and using hydrofluoric acid to remove the mask 3 if it is SiOx or SiNx. Alternatively, the protective layer 5 can be removed by chemical mechanical planarization ("CMP"), or any other suitable etching technique. The implementation of the method therefore makes it possible to produce a substrate 1 comprising a p-doped semiconductor layer 1b in certain zones and n-doped in other zones (see FIG. This method can therefore be used in the manufacture of devices requiring pn junctions, such as Schottchy diodes, in the field effect transistors ("Metal semi-conductor Field Transistor" or "MESFET" in English), or the transistors to High Electron Mobility Transistor ("HEMT"). According to an alternative embodiment not shown, it is conceivable to remove the mask 3 before depositing the protective layer 5, before carrying out the heat treatment step. However, this limits the concentration of n-type dopants in the semiconductor material layer 1b, since a large quantity of Si + ions diffuse during the heat treatment.
    [0017] According to a third mode of implementation of the method, it may be envisaged to first deposit a protective layer 5 covering only certain areas of the substrate 1. The mask 3 may then be deposited on other areas of the substrate covering or not the protective layer 5. The thicknesses of the protective layer 5 and the mask 3 are judiciously chosen so as to correctly protect the substrate 1. Thus, when the implantation step is performed, there is: - a implantation of dopant impurities 2 in the uncovered areas of the substrate 1, - implantation of doping impurities 2 and additional doping impurities 4 in the regions of the substrate 1 only covered by the mask 3, - no implantation in the zones of the substrate 1 covered by the protective layer 5.
    [0018] This mode of implementation of the method advantageously makes it possible to make p-i-n junctions in a simple and effective manner. Finally, in a fourth mode of implementation, it is possible to carry out the heat treatment step without having deposited a protective layer 5 beforehand. This is possible if the heat treatment is carried out by means of standard anneals carried out at temperatures below 1000 ° C., that is to say at temperatures where the degradation of the substrate 1 is low. If the heat treatment is carried out by means of rapid annealing, it is possible to rise to a temperature of the order of 1100 ° C for a few seconds.
    权利要求:
    Claims (15)
    [0001]
    REVENDICATIONS1. A method of doping a GaN-based semiconductor comprising the following steps: - providing a substrate (1) comprising a layer of semiconductor material (1b) based on GaN covered by a mask (3) based on of silicon, - implanting doping impurities (2) in the mask (3) so as to transfer additional doping impurities (4) of Si type by diffusion from the mask (3) to the layer of semiconductor material (1b - perform a heat treatment configured to activate doping impurities (2) and additional doping impurities (4).
    [0002]
    The method of doping a semiconductor according to claim 1, wherein the mask (3) partially covers the substrate (1) so as to define an area covered by the mask (3) and an uncovered area.
    [0003]
    3. Method of doping a semiconductor according to any one of claims 1 or 2, wherein the doping impurities (2) are p-type.
    [0004]
    4. Method of doping a semiconductor according to any one of claims 1 or 2, wherein the doping impurities (2) are Si + ions.
    [0005]
    The doping method of a semiconductor according to any one of claims 1 to 4, wherein the average implantation depth of doping impurities (2) is disposed at a distance of at least 300 nm from the interface so as to incorporate additional doping impurities (4) in the layer of semiconductor material (1b). 3 0 2 6 5 5 7 16
    [0006]
    6. Method for doping a semiconductor according to any one of claims 1 to 5, comprising a step of depositing a protective layer (5) made before the heat treatment step. 5
    [0007]
    7. Method of doping a semiconductor according to claim 6, wherein the step of depositing the protective layer (5) is performed before the step of implantation doping impurities (2). 10
    [0008]
    8. Semiconductor doping method according to claim 7, wherein the deposition of the protective layer (5) is carried out after the step of implantation of doping impurities (2) and additional doping impurities (4). ). 15
    [0009]
    9. Method for doping a semiconductor according to any one of claims 6 to 8, wherein the material of the protective layer (5) is selected from aluminum oxide, aluminum nitride, silicon oxide, or silicon nitride of the SixNy type, amorphous silicon and compounds of the HfSix0y type. 20
    [0010]
    10. Method for doping a semiconductor according to any one of claims 6 to 9, comprising a step of removing the protective layer (5) by etching after the heat treatment. 25
    [0011]
    11. Method for doping a semiconductor according to any one of claims 1 to 10, wherein the implantation step is carried out at a temperature between 15 and 700 ° C, preferably between 450 and 600 ° vs.
    [0012]
    The method of doping a semiconductor according to any one of claims 1 to 11, wherein the heat treatment step is a combination of at least two annealing of different durations and temperatures.
    [0013]
    13. Method of doping a semiconductor according to claim 12, wherein at least one of the annealing is carried out at a temperature above 1000 ° C.
    [0014]
    14. Method of doping a semiconductor according to any one of claims 1 to 13, wherein the thickness of the mask (3) is between 2 and 400 nm.
    [0015]
    15. Method of doping a semiconductor according to any one of claims 1 to 14, wherein the thickness of the layer of semiconductor material (1b) is between 5 nm and 10 pm, preferably between 500nm and 1 OpM, ideally equal to 1pm.
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    优先权:
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    FR1459130A|FR3026557B1|2014-09-26|2014-09-26|METHOD FOR DOPING A SEMICONDUCTOR BASED ON GAN|
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    EP15184348.9A| EP3001448A1|2014-09-26|2015-09-08|Method for doping a gan semiconductor|
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