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    • 专利摘要:
    Methods for manufacturing a semiconductor structure include implanting ions in a second region of a semiconductor layer constrained to a multilayer substrate to amorphize a portion of a crystalline semiconductor material in the second region of the semiconductor layer constrained without rendering amorphous a first region of the strained semiconductor layer. The amorphous region is recrystallized and elements are diffused in the semiconductor layer to enrich a concentration of diffused elements in a portion of the second region of the semiconductor layer, and modify a state of stress therein with respect to a state of stress of the first region of the stressed semiconductor layer. A first plurality of transistor channel structures are formed for each of them to include a portion of the first region of the semiconductor layer, and a second plurality of transistor channel structures are formed for each of them to comprise a part of the second region of the semiconductor layer.
    公开号:FR3026225A1
    申请号:FR1558136
    申请日:2015-09-02
    公开日:2016-03-25
    发明作者:Mariam Sadaka；Bich-Yen Nguyen；Ionut Radu
    申请人:Soitec SA；
    IPC主号:
    专利说明:

    [0001] METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURES INCLUDING CHANNELS OF TRANSISTORS HAVING DIFFERENT STRAIN STATES, AND RELATED SEMICONDUCTOR STRUCTURES FIELD 1 FIELD [0001] Embodiments of the present disclosure relate to methods that can be used for producing N-type metal-oxide-semiconductor field effect transistors (NMOS) and P-type metal-oxide-semiconductor (PMOS) field effect transistors having different stress states in a layer on a semiconductor substrate, as well as semiconductor structures and semiconductor devices made by these methods. BACKGROUND [0002] Semiconductor devices, such as microprocessors and memory devices, employ semiconductor transistors as the primary, basic operational structure of their integrated circuits. The field effect transistor (FET) is a type of transistor commonly used in semiconductor structures and semiconductor devices, which typically includes a source contact, a drain contact, and one or more gate contacts. A region of the semiconductor channel extends between the source contact and the drain contact. One or more PN junctions is (are) defined between the source contact and the gate contact. The gate contact is adjacent to at least a portion of the channel region, and the conductivity thereof is varied by the presence of an electric field. An electric field is therefore provided in the region of the channel, applying a voltage to the gate contact. Thus, for example, the electric current can flow through the source contact transistor at the drain contact, through the channel region, when a voltage is applied to the gate contact, but not at the source contact at the drain contact, in the absence of application of voltage at the gate contact. [0003] Recently developed field effect transistors (FETs) employ discrete, elongated channel structures called "fins." This type of transistors is often referred to in the art as "finned FETs." Many different configurations of finned FETs have been proposed in the art. [0004] The elongated channel or finned structures of a finned FET comprise a semiconductor material which can be N or P doped. It has also been demonstrated that the conductivity of N-doped semiconductor materials can be improved when the N-type semiconductor material is strained in tension, as is the conductivity of P-type semiconductor materials, when the P-type semiconductor material is compressively stressed. BRIEF SUMMARY OF THE INVENTION [0005] The present disclosure is intended to present a selection of concepts in simplified form, which will be detailed in the following description of exemplary embodiments. This statement is not intended to identify the main or essential features of the claims, nor to be used to limit the scope thereof. In some embodiments, the present disclosure includes a method of manufacturing a semiconductor structure. A proposed multi-layer substrate includes a base substrate, an oxide layer buried on a surface of the base substrate, and a semiconductor layer constrained to one side of the oxide layer, opposite the base substrate. . The strained semiconductor layer comprises a crystalline semiconductor material. The method further comprises implanting ions into a second region of the strained semiconductor layer without ion implantation in a first region of the strained semiconductor layer, and converting a portion of the crystalline semiconductor material in the second region of the amorphous material-constrained semiconductor layer, so that this second region has an amorphous region and an underlying crystalline region. The amorphous region is recrystallized, and elements are scattered from a part of the second region of the semiconductor layer constrained in another part of this layer, so as to enrich a concentration of elements diffused in the other part of the second region of the strained semiconductor layer, and to modify a state of stress of this second region, so that it is in a state of stress different from a state of stress of the first region of the strained semiconductor layer. A first plurality of transistor channel structures are formed such that each includes a portion of the first region of the semiconductor layer, and a second plurality of transistor channel structures is formed for each of them comprises a portion of the second region of the semiconductor layer. In additional embodiments, the present disclosure includes semiconductor structures that can be fabricated by methods as described herein. For example, in some embodiments, the present disclosure includes a semiconductor structure comprising a base substrate, an oxide layer buried on a surface of the base substrate, and a first plurality of transistor channel structures and a second a plurality of transistor channel structures disposed on the buried oxide layer in a common plane, on one side thereof, opposite the base substrate. Each transistor channel structure of the second plurality of transistor channel structures includes a condensed, constrained semiconductor layer including two or more elements. Each transistor channel structure of the first plurality of transistor channel structures comprises an uncondensed, constrained semiconductor layer. The transistor channel structures of the second plurality of transistor channel structures exhibit a crystallographic stress differing from a crystallographic constraint of the transistor channel structures of the first plurality of transistor channel structures. BRIEF DESCRIPTION OF THE DRAWINGS [0008] Although the description ends with claims in particular signaling and distinctly claiming the embodiments of the invention, the advantages of embodiments of the description will be more readily apparent from that of certain examples of the invention. Embodiments of the description, read in conjunction with the accompanying drawings, in which: Figure 1 is a schematic, simplified sectional view illustrating a multi-layer substrate including a stressed semiconductor layer, which may be employed according to the embodiments of the present description; FIG. 2 illustrates the substrate of FIG. 1, after application of a mask layer on a portion of the multi-layer substrate, as well as the implantation of ions in the semiconductor layer, which is constrained in an unmasked part. multi-layer substrate; Figure 3 is an enlarged view of a portion of the substrate of Figures 1 and 2, showing a portion of the semiconductor layer after ion implantation therein, to form an amorphous region of the inside the semiconductor layer; Figure 4 is similar to Figure 3 and illustrates the portion of the semiconductor layer after recrystallization of the amorphous region therein; Figure 5 is similar to Figures 3 and 4, and illustrates the portion of the semiconductor layer after removal of an oxide layer from the surface of the semiconductor layer; Figure 6 is similar to Figures 3 to 5, and illustrates the portion of the semiconductor layer after epitaxial deposition of additional semiconductor material thereon, so as to thicken the layer; Figure 7 is similar to Figures 3 to 6, and illustrates the portion of the semiconductor layer after diffusion of elements from one region thereof into another region thereof, so as to enrich a region. of the semiconductor layer with one or more elements, and to modify a state of stress of this region; Figure 8 is a schematic simplified sectional view illustrating a semiconductor structure fabricated using the methods described with reference to Figures 1-7, which comprises a semiconductor-on-insulator substrate (SeOI) including a semiconductor layer having regions with different stress states on an oxide layer buried on a base substrate; FIG. 9 is a schematic simplified sectional view illustrating a semiconductor structure that can be fabricated from the Se0I substrate of FIG. 8, and includes a first plurality of fin structures formed in a region of the a semiconductor layer having a first state of stress, and a second plurality of fin structures formed in a region of the semiconductor layer having a different second state of stress; FIG. 10 is a schematic, simplified sectional view illustrating another semiconductor structure that can be fabricated from the Se0I substrate of FIG. 8, and includes an insulating structure having shallow grooves, formed between regions of different stress states; Figure 11 is a schematic, simplified sectional view illustrating another multi-layer substrate, similar to that of Figure 1, including a constrained semiconductor layer employable in accordance with the embodiments of the present invention. description; Figure 12 illustrates a plurality of fin structures formed from the strained semiconductor layer of the substrate of Figure 11; Figure 13 illustrates the implantation of ions in some of the finned structures; Fig. 14 is an enlarged view of a portion of the substrate of Fig. 13 showing some of the fin structures after implanting ions therein, and forming an amorphous region within these structures; Figure 15 is similar to Figure 14, and illustrates the fin structures after recrystallization of the amorphous regions therein; Figure 16 is similar to Figures 14 and 15, and illustrates the fin structures after diffusion of elements from one region thereof into another region thereof, so as to enrich a region of the structures. finned with one or more elements, and modifying a state of stress of these structures; and Figure 17 illustrates an exemplary structure of a finned FET transistor. DETAILED DESCRIPTION [0026] The illustrations presented here are not actual views of a particular structure, device, system or semiconductor process, but merely representations. idealized, used to describe embodiments of the description. The headers used herein should not be construed as limiting the scope of the embodiments of the invention as defined by the claims below and their legal equivalents. The concepts described in a specific header generally apply in other sections throughout the description. The terms "first and second" in the description and claims serve to distinguish between similar elements [ As used herein, the terms "fins" and "fin structure" refer to a defined, finite, three-dimensional, elongated volume of semiconductor material having a length, a width, and a height, wherein the length is greater than to the width. In some embodiments, the width and height of the fins may vary along their length. The methods that can be used to make semiconductor structures, and the semiconductor structures that can be fabricated using these methods, are described below with reference to the figures. [0031] Referring to FIG. 1, a multilayer substrate 100 that may be provided includes a base substrate 102, a buried oxide (BOX) layer 104 on a surface of the base substrate 102, and a layer constrained semiconductor 106 on one side of the BOX layer 104, opposite the base substrate 102. The strained semiconductor layer 106 may comprise a strained silicon layer, and the multilayer substrate 100 may comprise a substrate. of constrained silicon on insulator (SS01). The base substrate 102 may comprise a chip or wafer, for example, of semiconductor material (silicon, silicon carbide, germanium, semiconductor material III-V, etc.), ceramic material (silicon oxide aluminum oxide, silicon carbide, etc.), or of metallic material (molybdenum, etc.). In some embodiments; the base substrate 102 may have a monocrystalline or polycrystalline microstructure. In other embodiments, the base substrate 102 may be amorphous. The base substrate 102 may have a thickness of, for example, from about 400 μm to about 900 μm (e.g., about 750 μm), although thicker or thinner base substrates 102 may also be employed. The layers covering the base substrate 102, such as the BOX layer 104, can be deposited, "drawn" or otherwise formed on the substrate epitaxially, by means of one of several different methods, such as, for example, p. chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PLD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE) and thermal oxidation. In additional embodiments, they may be transferred to the base substrate 102 from another donor substrate using known methods. By way of nonlimiting example, the multi-layer substrate 100 can be formed using the method known in the art as the SMART-CUT® process, in which a layer of semiconductor material is transferred from a donor structure to a recipient substrate (base substrate), so that an oxide layer (BOX layer 104) is deposited between the receiving substrate and the semiconductor layer of the transferred layer. The SMARTCUT® process is described, for example, in US Pat. No. RE39,484 to Bruel (issued February 6, 2007), US Pat. No. 6,303,468 to Aspar et al. (issued Oct. 16, 2001), U.S. Patent No. 6,335,258 to Aspar et al. (issued January 1, 2002), US Patent No. 6,756,286 to Monceau et al. (issued June 29, 2004), U.S. Patent No. 6,809,044 to Aspar et al. (issued October 26, 2004), and US Patent No. 6,946 to 65 of Aspar et al. (issued September 20, 2005). The BOX layer 104 may comprise, for example, an oxide (eg, silicon dioxide, aluminum oxide, hafnium oxide, etc.), a nitride (eg, silicon nitride) ), an oxynitride (e.g., silicon oxynitride) or a combination of these dielectric materials. The BOX layer 104 may be crystalline or amorphous. It may have an average layer thickness of, for example, from about 10 nm to about 200 nm, although thicker or thinner layers may also be employed in embodiments of the present disclosure. The strained semiconductor layer 106 may comprise a constrained crystalline semiconductor material (in compression or traction), such as a strained silicon layer 10 (Si). In other embodiments, the strained semiconductor layer 106 may comprise constrained germanium (Ge), silicon-constrained silicon (SiGe) or a constrained III-V semiconductor material. Thus, the constrained semiconductor material 106 may have a crystal structure having lattice parameters that are either above (tensile stress) or below (compression stress) the relaxed lattice parameters that would normally be presented by the lattice. the crystalline structure of the respective semiconductor material, isolated and non-epitaxial, at steady state. The strained semiconductor layer 106 may have an average thickness of about 50 nm or less, or even about 10 nm or less. It may have an average thickness less than its critical thickness. In embodiments in which the strained semiconductor layer 106 comprises a strained silicon layer, transferred to the base substrate 102, from a donor substrate, and in which the strained semiconductor layer 106 is formed by epitaxial growth on a SiGe buffer layer, on the donor substrate, before the layer transfer process, the critical thickness of the constrained silicon layer may be a function of the concentration of germanium in the SiGe buffer layer, critical thickness decreasing with the increase of this concentration. Thicker layers of strained semiconductor material 106 may also be employed in embodiments of the present disclosure. The strained semiconductor layer 106 may be thickened to a value greater than its critical thickness, after transfer thereof to the base substrate 102, without degrading the stress relaxation by means of epitaxial deposition techniques, as described, for example, 30 in, Thean et al., Uniaxial-Biaxial Stress Hybridization for Super-Critical Strained-Directly On Insulator (SC-SSOI) PMOS With Different Channel Orientations, IEEE International (Electron Devices Meeting, Washington, DC 2005), pages 509-512. As a non-limiting, specific example, the base substrate 102 of the donor substrate 100 may comprise a monocrystalline silicon substrate, the BOX 104 layer, silicon dioxide (SiO 2), and the constrained semiconductor layer. 106, monocrystalline silicon constrained (sSi), of a thickness less than its respective critical thickness, so as to avoid a start of relaxation and the formation of localized defects in the crystal structure thereof. In some embodiments, an oxide layer 108, which may be a native oxide layer or a deposited oxide, may be present on the side of the main surface of the strained semiconductor layer 106, at the opposite of the BOX 104 layer. In other embodiments, the oxide layer 108 may not be present. Referring to Figure 2, a pattern mask layer 110 may be provided on the strained semiconductor layer 106. This layer may cover one or more regions of the strained semiconductor layer 106, while other regions thereof may not be covered by the patterned mask layer 110. By way of non-limiting example, FIG. 2 illustrates a first region of the semiconductor layer 106A, covered by the layer pattern mask 110, and a second region of the stressed semiconductor layer 106B, not covered by the latter. [0040] The pattern mask layer 110 may comprise a hard mask layer material, such as one or more of an oxide layer, a nitride layer, or an oxynitride layer. The patterned mask layer 110 may be formed by deposition or otherwise by providing a continuous layer of hard mask material on the multi-layered substrate 100, and then patterning the hard mask material with the help of a photolithographic masking and etching process for forming apertures in the hard mask material, at locations where it is desired to remove portions of the material, to discover regions of the stressed semiconductor layer 106. In other embodiments, the patterned mask layer 110 may comprise a photoresist masking material. With reference to FIG. 2, after formation of the patterned mask layer 110, ions can be implanted in the region or regions of the stressed semiconductor layer 106, not covered by the layer pattern mask 110 (as indicated by the directional arrows), such as the second region of the constrained semiconductor layer 106B, without ion implantation in the region or regions of the layer 110 covered by the layer 110 , such as the first region of the strained semiconductor layer 106A. The ions can pass through the apertures of the mask layer 110 and reach the first region of the strained semiconductor layer 106A, while the mask layer 110 protects the second region of the strained semiconductor layer 106B and inhibits the ions. to be implanted there. In some embodiments, when the oxide layer 108 is present, it can be removed from the strained semiconductor layer 106, so as to expose a surface of the strained semiconductor layer 106. In other embodiments, however, the ions may be implanted in the strained semiconductor layer 106 through the oxide layer 108. The ion implantation may convert a portion of the crystalline semiconductor material of the strained semiconductor layer 106 of amorphous material. Thus, the region (s) of the semiconductor layer 106 in which the ions are implanted may or may have an amorphous region 112 and an underlying crystalline region 114, as illustrated in the magnified view of FIG. 3. The implanted ions may be ions of elements different from at least one element present in the crystalline structure of the semiconductor layer 106. For example, in embodiments in which the semiconductor layer The constraint comprises constrained silicon (sSi), the implanted ions may comprise, for example, germanium ions, different from those of silicon. This is because the implanted ions having a different atomic radius, other elements of the semiconductor layer 106, can be used to subsequently modify a state of stress of this layer in subsequent processing, as described in more detail. below. [0045] Table 1 below gives examples of concentration and germanium content in a tensile-strained silicon semiconductor layer 106, at the thicknesses thereof, for each of the five (5) different assays. a process for implanting germanium ions, carried out with energies of 40-50 KeV.
    [0002] TABLE 1 Dose No.  Ge Implant Ge Conc.  Ge Content If Layer Dose (at. cm-3) Thickness (at. cm-2) (1) '1. 00E + 19 0. 02% 100 nm 1. 00E + 15 (2) 5. 00E + 15 5. 00E + 19 0. 10% ° Y E 6 1. 00E + 20 0. 20% () - 5. 00E + 16 5. 00E + 20 1. 00% (5) 1. 00E + 17 1. 00E + 21 200% '(1) 1. 00E + 15 2. 00E + 19% 50 nm (2) 5. 00E + 15 1. 00E + 20 0. 20% (3) 1_00E + 16 2. 00E + 20 040% (4) 5. 00E + 16 1_00E + 21 2. 00% (5) 1. 00E + 17 2. 00E + 21 4. 00% (1) 1. 00E + 15 3. 33E + 19 0. 07% 30 nm (2) 5. 00E + 15 1. 67E + 20O. 33% (3) 1. 00E + 16 3. 33E + 20 0. 67% (4) 5. 00E + 16 1 67E + 2_1 3. 33% (5) 1. 00E + 17 3. 33E + 21 6. 67% (1) 1 0 E 5 5. 00E + 19 0. 10% 20 nm (2) 5_00E + 15 2. 50E + 20 (3) 1 0 E + 16 5. 00E + 20 1. 00% (4) 5_00E + 16 2. 50E + 21 5. 00% (5) 1. 00E + 17 5. 00E + 21 10. 00% 1. 00E + 15 1. 40E + 20 0. 20% 10 nm (2) 5. 00E + 15 5. 00E + 20 1. 00% (3) 1. 00E + 16 1. 00E + 21 200% (4) 500E + 16 5 00E + 21 10. 00% (5) 1. 00E + 17 1. 00E + 22 20. With reference to Figure 4, after implantation of the ions in the region or regions of the strained semiconductor layer 106, so that it (s) comprises (include) an amorphous region 112 and a Underlying crystalline region 114 (as shown in FIG. 3), the amorphous regions 112 of the semiconductor layer 106 can be recrystallized.  For example, an annealing process, carried out in a furnace at elevated temperatures, may be used to recrystallize the amorphous regions 112 and form recrystallized regions 120, as shown in Figure 4.  During recrystallization, the recrystallized regions 120 may be in a state of stress different from that of the first region of the strained semiconductor layer 106A (FIG. 2), due to the presence of the implanted ions (e.g.  ex.  germanium ions) having an atomic radius different from that of at least one element (e.g.  ex.  silicon) present in the semiconductor layer 106 formed initially.  Thus, in embodiments in which the initially formed, constrained semiconductor layer 106 comprises tensile stressed silicon and the implanted ions comprise germanium ions, the recrystallized regions 120 may comprise SiyGel_y, wherein y is from about 0.01 to about 0.50, or from about 0.10 to about 0.20 in some embodiments.  During the recrystallization process, the recrystallization of the amorphous regions can be seeded by the underlying crystalline regions 114 of this layer since the underlying crystalline region 114 of the semiconductor layer 106 may include silicon and that recrystallized regions 120 may comprise SiyGe1y, recrystallized regions 114 thereof are formed on the underlying Si, and the crystal lattice of SiyGel. y can be constrained by the underlying Si, so that the recrystallized regions of SiyGei_y are in a compressive stress state (the SiyGei_y lattice parameters being greater than those of Si, since the atomic radius of Ge is greater great than that of Si).  Referring to Figure 5, after recrystallization of the amorphous regions 112 of the semiconductor layer 106, to form the recrystallized regions 120, if the optional oxide layer 108 is present, it can be removed by means of one or more chemical etching, mechanical polishing or chemical mechanical polishing (CMP) processes.  As shown in Figure 6, in some embodiments, an additional semiconductor material 124 may be grown epitaxially, selectively, on the second region of the semiconductor layer 106B, without epitaxial growth. an additional semiconductor material on the first region of the semiconductor layer 106A.  The additional semiconductor material 124 may comprise silicon or Si-SiGe, for example.  In some embodiments, the growth of the additional semiconductor material 124 may be performed after recrystallization of the amorphous regions 112 to form the recrystallized regions 120, as illustrated in the sequence of the figures.  In other embodiments, however, the growth of the semiconductor material 124 may be performed prior to implanting the ions in the second region of the semiconductor layer 106B and forming the amorphous regions 112 (Figure 3). The selective epitaxial growth of the additional semiconductor material 124, as discussed in connection with FIG. 6, when performed prior to the ion implantation method described with reference to FIG. a larger amount of ions that can allow higher concentrations of the ions implanted in the second region of the semiconductor layer 106B, as well as the realization of a longer thermal diffusion process, as described below with reference to Figure 7, and therefore, a higher degree of modification of a state of stress of the second region of the semiconductor layer 106B.  The thickness of the additional semiconductor material 124 grown epitaxially, selectively, on the second region of the semiconductor layer 106B can be selected, so that after a diffusion and enrichment method described in FIG. Referring to Figure 7, a thickness of the second region of the semiconductor layer 10613 may be at least substantially equal to a thickness of the first region of the semiconductor layer 106A, not subject to the diffusion and enrichment method described in reference to Figure 7.  Referring to Figure 7 after recrystallization of the amorphous regions 112 of the second region of the semiconductor layer 106B to form the recrystallized regions 120, elements may be diffused from a portion of the recrystallized regions 120 of the second region of the semiconductor layer 106B in another part of this second region, so as to enrich a concentration of the diffused elements in the other part of it and to modify a state of stress of the region.  For example, a condensation process (often referred to as a "thermal mixing" process) or another type of process may be used to diffuse elements into the second region of the semiconductor layer 106B, so that they are concentrated and enriched in a part of the second region of the semiconductor layer 106B so as to selectively reduce the tensile stress, increase the compressive stress, and / or relax the stress in the second region of the semi-conductor layer 106B -conductor 106B relative to the stress level of the first region of the semiconductor layer 106A.  In these embodiments, the elements may not be substantially diffused in the first region of the semiconductor layer 106A.  In other words, the condensation process can only be performed on the second region of the semiconductor layer 106B, and not on the first region of the semiconductor layer 106A.  This condensation process is described below.  FIG. 7 is similar to FIGS. 3 to 6, and illustrates the multilayer substrate 100, after execution of a condensation process on the second region of the semiconductor layer 106B.  The condensation process may involve subjecting the second region of the semiconductor layer 106B to an oxidation process in an oven at elevated temperatures (e.g.  ex. between about 900 ° C and about 1150 ° C) in an oxidizing atmosphere (e.g.  ex.  02 sec with or without HCL).  The oxidation process may result in the formation of an oxide layer 122 on the surface of the second region of the semiconductor layer 106B and may result in the diffusion of elements from within an upper region. the second region of the semiconductor layer 106B in a lower region of the second region of the semiconductor layer 106B.  In embodiments in which the strained semiconductor layer 106 comprises constrained silicon (sSI), the ions implanted in the second region of the semiconductor layer 106B, described with reference to FIG. comprise germanium ions, and the germanium atoms can continue to diffuse in the second region of the semiconductor layer 106B during the condensation process.  An oxide layer 122 may form on the surface of the second region of the semiconductor layer 106B, and grow in thickness in that region.  Since the thickness of the oxide layer 122 increases during the germanium condensation process, the thickness of the semiconductor layer 106 of SiyGei_y decreases, and the concentration of germanium in the semiconductor layer 106 increases until the semiconductor layer 106 of SiyGel_y has the desired concentration of germanium therein.  The diffusion and concentration of germanium in the second region of the semiconductor layer 106B may result in a decrease in the tensile stress in the strained semiconductor layer 106, and lead to stress relaxation and / or generation. compressive stress in this layer.  As a result, the first region of the semiconductor layer 106A may be in a first state of stress, and the second region of the semiconductor layer 106B in a second state of stress different from the first state of stress.  The oxide layer 122 formed in the diffusion and enrichment process (e.g.  ex.  condensation process) can be removed from the second region of the semiconductor layer 106B before further processing.  As mentioned above, the first region of the semi-conductive layer 106A may comprise a layer of silicon constrained in tension.  The tensile stress of the first region of the semiconductor layer 106A can enhance the mobility of the electrons in the first region of the semiconductor layer 106A, which may be desirable to form N-type FET transistors having channel comprising portions of the first region of the semiconductor layer 106A.  The ion implantation and recrystallization process, as well as the condensation method, performed in the second region of the semiconductor layer 106B, can result in improved hole mobility in the second region of the semiconductor layer. and -conductor 106B, which may be desirable to form P-type FET transistors having channel regions comprising portions of the second region of the semiconductor layer 106B.  As shown in FIG. 8, the oxide layer 108 and the mask layer 110 covering the semiconductor layer 106 can be removed to form a semiconductor structure 130.  Semiconductor structure 130 illustrated in Figure 8, formed by the methods described with reference to Figures 1-7, includes a base substrate 102, a BOX layer 108, on a surface of base substrate 102, and a first region of a semiconductor layer 106A, and a second region of a semiconductor layer 106B, disposed on the BOX layer 104, in a common plane, on a side thereof, opposite the substrate of base 102.  The semiconductor structure 130 can be further processed to complete the fabrication of a semiconductor device including N and P type transistors.  The N-type transistors may be formed on and / or in the first region of the semiconductor layer 106, and the P-type transistors on and / or in the second region of the semiconductor layer 106.  Figure 9, for example, illustrates the formation of a first plurality of fin structures 132A, each comprising a portion of the first region of the semiconductor layer 106A, and a second plurality of fin structures 132B, each comprising a portion of the second region of the semiconductor layer 106B.  Each of the finned structures 132A, 132B is sized and configured for use as a transistor channel structure in fin FET transistors.  By way of nonlimiting example, each of the fin structures 132A, 132B may be formed to have an average width of about 15 nm or less.  The finned structures I 32B of the second plurality of fin structures 132B have a crystallographic stress differing from a crystallographic stress of the fin structures 132A of the first plurality of finned structures 132A.  Each fin structure 132A of the first plurality of fin structures 132A includes a non-condensed constrained semiconductor material.  Each fin structure 132B of the second plurality of fin structures 132B includes a condensed constrained semiconductor material having two or more members (e.g.  ex.  silicon and germanium).  After forming the first and second plurality of fin structures 132A, 132B, a first plurality of N-type fin FET transistors may be formed, including the first plurality of IA fin structures 32A and a second plurality of FET transistors. P-type finned fins may be formed comprising the second plurality of I32B finned structures.  In further embodiments, the semiconductor structure 130 of FIG. 8 can be further processed to form a plurality of N-type metal-oxide-semiconductor field effect transistors in conventional planar technology. (NMOS FET) on and / or in the first region of the semiconductor layer 106A and a plurality of P-type metal-oxide-semiconductor field effect transistors in conventional planar technology (PMOS FET) on and or in the second region of the semiconductor layer 106B, and as illustrated in Figure 10.  For example, one or more insulation structures having shallow grooves (STI) 134 may or may be formed (s) partially or wholly through the semiconductor layer 106, so as to electrically isolate the transistor channel to be formed in the semiconductor layer 106.  Conventional STI processing can be used to define transistor channel structures in the semiconductor layer 106.  In this treatment, the masking and etching method can be used to form grooves between adjacent transistor channel structures, and a dielectric material can be provided in the grooves to form STI structures 134, between the structures to be formed. transistor channel.  The STI structures 134 in the semiconductor layer 106 can thus serve to electrically isolate the transistor channel structures to be defined in the semiconductor layer 106.  Although a single STI structure 134 is illustrated in Figure 10, a plurality of STI structures 134 may be used to define the transistor channel structures in the semiconductor layer 106.  After forming the STI structures 134 in the semiconductor layer 106, a first plurality of transistor channel structures may be formed, so that each of them comprises a portion of the first region of the semiconductor layer. 106A, and a second plurality of transistor channel structures may be formed, such that each includes a portion of the second region of the semiconductor layer 106B.  The transistor channel structures may be sized and configured to be used as transistor channel structures in MOS FET transistors.  The NMOS FET transistor channel structures formed in the first region of the semiconductor layer 106A exhibit a crystallographic stress differing from a crystallographic stress of the PMOS FET transistor channel structures formed in the second region of the the semiconductor layer 106B.  After forming the first and second plurality of transistor channel structures, a first plurality of NMOS FET transistors may be formed, including the first plurality of transistor channel structures, and a second plurality of PMOS FET transistors may be formed, including the second plurality of transistor channel structures.  In further embodiments, a first plurality of NMOS FET transistors may be formed, including the first plurality of transistor channel structures, and a second plurality of PMOS FET transistors may be formed, including the second plurality of transistor channel structures before forming the STI structures 134.  Figures 11 to 16 illustrate a further embodiment of a method that can be used to fabricate P-type finned FET transistors, in co-planar technology, similar to those described above, with reference to the Figures.  1 to 9.  Figure 11 illustrates a multilayer substrate 140 which includes a base substrate 102, a buried oxide layer 104, and a strained semiconductor layer 106, as previously described herein, with reference to Figure 1 .  As shown in Figure 12, patterns may be applied to the strained semiconductor layer 106, using, for example, a masking and etching process to form fin structures 142, each including constrained semiconductor layer region 106.  The finned structures 142 may be formed using finned FET manufacturing methods, known in the art, and include dual spacer defined masking (SDDP) methods (also known in the art as of "Sidewall image transfer").  Winged structures 142 may include a second plurality of winged structures 142B and a first plurality of winged structures 142A.  With reference to FIG. 13, one or more masking layers may be deposited on the finned structures 142.  The masking layers may include, for example, a passivation oxide layer 144, a nitride layer 146, and a mask layer 148.  The mask layer 148 may comprise, for example, a photo-resist masking material, which may bear patterns to form apertures therethrough, on the second plurality of winged structures 142B.  One or both of the oxide layer 144 and the nitride layer 146 may be removed by one or more etching processes in which they are exposed to a reagent. the mask layer 148 protects the rest of the etch reagent structure.  As shown in Figure 13, in some embodiments, regions of the nitride layer 146, covering the second plurality of winged structures 142B, can be removed by means of an etching process, while at least a portion of the oxide layer 144 may be left in place on the second plurality of fin structures 142B.  In other embodiments, however, the portions of the oxide layer 144 covering the second plurality of winged structures 142B may be at least substantially completely removed.  The mask layer 148 may be removed, optionally, before further processing or the mask layer 148 may be left in place, as shown in FIG. 13.  As shown in FIG. 13, ions may be implanted in the second plurality of winged structures 142B, through the apertures, in one or both of the mask layer 148 and the nitride layer 146, in a method, as previously described, with reference to Figure 2, so as to form amorphous regions 150, in portions of the second plurality of fin structures 142B, as illustrated in Figure 14.  The second plurality of winged structures 142B may include crystalline regions 114 of the stressed semiconductor layer 106, remaining under the amorphous regions 150, substantially as previously described with reference to Figure 3.  With reference to FIG. 15, the amorphous regions 150 may be recrystallized to form recrystallized regions 154, after formation of the amorphous regions 150.  The recrystallization process can be carried out as described above, with reference to FIG. 4.  With reference to FIG. 16, a diffusion and enrichment method (p.  eg, a condensation process) can be performed on the second plurality of fin structures 142B, in a manner as described above, with reference to Figure 7 after formation of the recrystallized regions 154 (Figure 15). Enrichment may result in the formation of an oxide layer 156 on each of the second plurality of vane structures 142B.  The epitaxial growth of an additional semiconductor material may, optionally, also be carried out on the second plurality of winged structures 142B, before carrying out the diffusion and enrichment process, as previously described, by reference to Figures 5 and 6.  The second plurality of fin structures 142B may therefore comprise transistor channel structures sized and configured to form P-type finned FET transistors, and the first plurality of finned structures 142A may comprise channel structures. transistor sized and configured to form N-type FET finned transistors.  [0076] After forming the first and second plurality of fin structures 142A, 142B, as previously described, with reference to Figures 11-16, a first plurality of NMOS finned FET transistors may be formed, including the first plurality of structures. with fins 142A, and a second plurality of PMOS finned FET transistors may be formed, including the second plurality of winged structures 142B.  FIG. 17 illustrates an exemplary, non-limiting, simplified embodiment of a finned FET configuration, which may be fabricated using the second plurality of winged structures 142B, and / or the first There is a plurality of finned structures 142A in accordance with the embodiments of the present disclosure (finned structures of FIG. 9). It will be appreciated that many different configurations of finned FETs 30 are known in the art. which can be employed in accordance with the embodiments of the invention, and the structure of the fin FETs, shown in Figure 17, is merely exemplary of these structures.  As shown in FIG. 17, a fin FET transistor 160 includes a source region 162, a drain region 164, and a channel extending between the source region 162 and the drain region 164.  The channel is defined by and includes fins, such as either a first fin structure 142A, or a second fin structure 142B.  In some embodiments, the source region 162 and the drain region 164 may include or be defined by longitudinal end portions of a fin structure 142.  A conductive grid 166 extends adjacently over at least a portion of the fin structure 142 between the source region 162 and the drain region 164.  The gate 166 can be separated from the fin structure 142 by a dielectric material 168.  It may include a multi-layer structure, and semiconductor and / or conductive layers.  A low resistance layer including a metal, a metal compound or both, such as a conductive silicide, may be deposited on the source region 162 and / or the drain region 164, to form electrical contacts with the one (s) - this.  [0079] Advantageously, a tension / tensile stress in the channel can increase the performance of NMOS finned FET transistors, and reduce the threshold voltage, while a reduced tensile stress / strain (e.g.  ex. , less tensile stress, no tensile or compressive stress or compressive stress) in the channel, can increase the performance of PMOS finned FET transistors, and reduce the threshold voltage.  For certain functions, constrained devices are advantageous because of the need for high performance; for others, the performance is not as important, but a high threshold voltage is advantageous.  With the embodiments of the present invention, the manufacturer can selectively incorporate different voltage / strain levels in the crystal lattices of different MOSFETs or fin FETs, in the same device, into a common FET plane.  [0080] Examples of additional embodiments, not limiting, of the invention are described below.  Embodiment 1: A method of manufacturing a semiconductor structure, comprising: providing a multi-layer substrate, including: a base substrate, an oxide layer buried on a surface of the substrate base, and a semiconductor layer constrained on one side of the buried oxide layer, opposite the base substrate, the strained semiconductor layer comprising a crystalline semiconductor material; implanting ions in a second region of the strained semiconductor layer, without ion implantation in a first region of the strained semiconductor layer, and converting a portion of the crystalline semiconductor material into the second region of the semiconductor layer constrained by amorphous material, such that the second region of the strained semiconductor layer has an amorphous region and an underlying crystalline region; recrystallization of the amorphous region; diffusing elements of a part of the second region of the semiconductor layer constrained in another part of the strained semiconductor layer, so as to enrich a concentration of the elements diffused in the other part of the second region of the strained semiconductor layer and modifying a stress state of the second region of the strained semiconductor layer, such that the second region of the strained semiconductor layer is in a stress state different from a stress state of the first region of the strained semiconductor layer; and forming a first plurality of transistor channel structures, each comprising a portion of the first region of the semiconductor layer and a second plurality of transistor channel structures, each comprising a portion of the second region of the the semiconductor layer.  Embodiment 2: The method of Embodiment 1, further comprising selecting the constrained semiconductor layer to include constrained silicon.  Embodiment 3: The method of Embodiment 2, further comprising selecting the constrained semiconductor layer to include tensile stressed silicon.  Embodiment 4: The method of Embodiment 2 or 3, wherein the ion implantation in the second region of the strained semiconductor layer comprises implanting germanium ions into the second region of the a semiconductor layer constrained to form SiyGei_y, wherein y is from about 0.10 to about 0.50, and wherein the diffusion of elements from a portion of the second region of the constrained semiconductor layer. in another part of the strained semiconductor layer comprises the diffusion of germanium in the other part of the second region of the strained semiconductor layer.  Embodiment 5: The method of any one of Embodiments I to 4, wherein forming the first plurality of transistor channel structures and the second plurality of transistor channel structures comprises forming a first plurality of fin structures, each including a portion of the first region of the semiconductor layer, and a second plurality of fin structures, each including a portion of the second region of the semiconductor layer.  Embodiment 6: The method of Embodiment 5, further comprising forming a plurality of N-type FET finned transistors comprising the first plurality of fin structures, and forming a plurality of P-type finned FET transistors comprising the second plurality of finned structures.  Embodiment 7: The method of any one of Embodiments 1 to 6, further comprising forming the transistor channel structures of the first and second plurality of transistor channel structures for have an average width of about 15 nm or less.  Embodiment 8: The method of any one of Embodiments 1 to 7, wherein the diffusion of elements of a portion of the second region of the semiconductor layer constrained in another portion of the semiconductor layer. The constrained conductive comprises the stress relaxation in the second region of the strained semiconductor layer.  Embodiment 9: The method of Embodiment 8, wherein the stress relaxation in the second region of the strained semiconductor layer, comprises increasing the mobility of the holes, in the second region of the constrained semiconductor layer.  Embodiment 10: The method of any one of Embodiments 1 to 9, wherein the diffusion of elements of a portion of the second region of the semiconductor layer constrained to another portion of the layer. Constrained semiconductor comprises performing a condensation process on the second region of the strained semiconductor layer.  Embodiment 11: The method of Embodiment 10 wherein performing a condensation process on the second region of the strained semiconductor layer comprises oxidizing a portion of the second region. of the strained semiconductor layer.  Embodiment 12: The process of any one of Embodiments 1 to 30 wherein the recrystallization of the amorphous region comprises seeding the recrystallization of the amorphous region with the underlying crystalline region.  Embodiment 13: The method of any one of Embodiments I to 12, further comprising epitaxially growing an additional semiconductor material on the second region of the semiconductor layer without growth of an additional semiconductor material on the first region of the semiconductor layer, prior to diffusion of elements of a portion of the second region of the semiconductor layer constrained in the other portion of the strained semiconductor layer.  Embodiment 14: Semiconductor structure, comprising: a base substrate, an oxide layer buried on a surface of the base substrate, a first plurality of transistor channel structures and a second plurality of transistor structures; transistor channel 10 disposed on the buried oxide layer in a common plane, on one side thereof, opposite to the base substrate, each transistor channel structure of the second plurality of transistor channel structures comprising a condensed stress semiconductor layer including two or more elements, each transistor channel structure of the first plurality of transistor channel structures comprising a non-condensed strained semiconductor layer; wherein the transistor channel structures of the second plurality of transistor channel structures have a crystallographic stress differing from a crystallographic constraint of the transistor channel structures of the first plurality of transistor channel structures.  Embodiment 15: Semiconductor structure of Embodiment 14 wherein the uncondensed constrained semiconductor layer of each transistor channel structure of the first plurality of transistor channel structures comprises constrained silicon.  Embodiment 16: Semiconductor structure of Embodiment 14 or 15, wherein the condensed constrained semiconductor layer of each transistor channel structure of the second plurality of transistor channel structures comprises SixGei ,, wherein x is from about 0.01 to about 0.50.  Embodiment 17: Semiconductor structure of any one of Embodiments 14 to 16, wherein the transistor channel structures of the first plurality of transistor channel structures are in a state of constraint. traction, and the transistor channel structures of the first plurality of transistor channel structures are relaxed or in a state of compressive stress.  Embodiment 18: Semiconductor structure of any one of Embodiments 14 to 17, wherein the transistor channel structures of the first plurality of transistor channel structures, and the second plurality of structures transistor channel, have an average width of about 15 nm or less.  Embodiment 19: Semiconductor structure of any one of Embodiments 14 to 18, wherein the transistor channel structures of each of the first plurality of transistor channel structures, and the second plurality of transistor channel structures, includes finned structures and the second plurality of transistor channel structures, includes finned structures. Embodiment 20: Semiconductor structure of Embodiment 19, further comprising: a first plurality of N-type FET transistors comprising the first plurality of transistor channel structures, and a second P-type fin FETs comprising the second plurality of transistor channel structures.  [00101] The exemplary embodiments described above do not limit the scope of the invention, since they are merely simple examples thereof, which is defined by the scope of the appended claims and their equivalents. legal.  All equivalent embodiments are intended to be included within the scope of the present invention.  Of course, various modifications of the invention, in addition to those indicated and described herein, such as other useful combinations of presented elements will be apparent to those skilled in the art.  In other words, one or more features of an exemplary embodiment described herein may or may be combined with one or more features of another exemplary disclosed embodiment. here, to provide additional embodiments of the invention.  These modifications and embodiments are also intended to be included in the scope of the appended claims. 25
    权利要求:
    Claims (10)
    [0001]
    REVENDICATIONS1. A method of manufacturing a semiconductor structure, comprising: providing a multi-layer substrate including: a base substrate, an oxide layer buried on a surface of the base substrate, and a constrained semiconductor layer on one side of the buried oxide layer, opposite the base substrate, the strained semiconductor layer comprising a crystalline semiconductor material; implanting ions in a second region of the strained semiconductor layer, without ion implantation in a first region of the strained semiconductor layer, and converting a portion of the crystalline semiconductor material into the second region of the semiconductor layer constrained by amorphous material, so that said second region has an amorphous region and an underlying crystalline region; recrystallization of the amorphous region; diffusing elements of a portion of the second region of the semiconductor layer constrained in another part of this layer, so as to enrich a concentration of diffused elements in the other part of the second region of the layer; constrained semiconductor, and modifying a state of stress of this second region, so that it is in a state of stress different from a state of stress of the first region of the strained semiconductor layer; and forming a first plurality of transistor channel structures, each comprising a portion of the first region of the semiconductor layer, and a second plurality of transistor channel structures, each comprising a portion of the second region of the semiconductor layer.
    [0002]
    The method of claim 1 further comprising selecting the constrained semiconductor layer to comprise strained silicon.
    [0003]
    The method of claim 2, further comprising selecting the constrained semiconductor layer to include tensile stressed silicon.
    [0004]
    The method of claim 2, wherein implanting ions into the second region of the constrained semiconductor layer comprises implanting germanium ions into the second region of the strained semiconductor layer to form SiyGei_y. wherein y is from about 0.10 to about 0.50, and wherein the diffusion of elements from a portion of the second region of the semiconductor layer constrained in another portion of the semiconductor layer. stress comprises the diffusion of germanium in the other part of the second region of the strained semiconductor layer.
    [0005]
    The method of claim 1, wherein forming the first plurality of transistor channel structures and the second plurality of transistor channel structures comprises forming a first plurality of fin structures, each comprising a portion of the first region of the semiconductor layer, and a second plurality of fin structures each comprising a portion of the second region of the semiconductor layer.
    [0006]
    The method of claim 1, wherein scattering of elements of a portion of the second region of the semiconductor layer constrained in another portion of the strained semiconductor layer comprises stress relaxation in the second region. of the strained semiconductor layer.
    [0007]
    7. The method of claim 1, wherein the diffusion of elements of a part of the second region of the semiconductor layer constrained in another part of the strained semiconductor layer comprises carrying out a condensation process. on the second region of the strained semiconductor layer.
    [0008]
    The method of claim 7, wherein performing a condensation process on the second region of the strained semiconductor layer comprises oxidizing a portion of the second region of the strained semiconductor layer.
    [0009]
    The process of claim 1, wherein recrystallizing the amorphous region comprises seeding the recrystallization of the amorphous region with the crystalline-underlying region.
    [0010]
    The method of claim 1, further comprising epitaxially growing an additional semiconductor material on the second region of the semiconductor layer without growing an additional semiconductor material on the first region of the semiconductor layer. before diffusion of elements of a part of the second region of the semiconductor layer constrained in the other part of the stressed semiconductor layer. He. A semiconductor structure, comprising: a base substrate, an oxide layer buried on a surface of the base substrate, a first plurality of transistor channel structures and a second plurality of transistor channel structures disposed on the substrate layer; buried oxide in a common plane on one side thereof, opposite to the base substrate, each transistor channel structure of the second plurality of transistor channel structures comprising a condensed constrained semiconductor layer including two or more elements each transistor channel structure of the first plurality of transistor channel structures comprising a non-condensed strained semiconductor layer; wherein the transistor channel structures of the second plurality of transistor channel structures have a crystallographic stress differing from a crystallographic constraint of the transistor channel structures of the first plurality of transistor channel structures. The semiconductor structure of claim 11 wherein the uncondensed constrained semiconductor layer of each transistor channel structure of the first plurality of transistor channel structures comprises constrained silicon. A semiconductor structure according to claim 11, wherein the condensed stressed semiconductor layer of each transistor channel structure of the second plurality of transistor channel structure comprises SixGe] x, wherein x is between about 0.01 and about 0.50. The semiconductor structure of claim 11, wherein the transistor channel structures of the first plurality of transistor channel structures are in a tensile stress state, and the transistor channel structures of the first plurality of transistor channels are in a state of tensile stress, and the transistor channel structures of the first plurality of Transistor channel structures are relaxed or in a state of compressive stress. The semiconductor structure of claim 11 wherein the transistor channel structures of each of the first plurality of transistor channel structures, and the second plurality of transistor channel structures comprise finned structures.
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    US14489798|2014-09-18|
    US14/489,798|US9165945B1|2014-09-18|2014-09-18|Method for fabricating semiconductor structures including transistor channels having different strain states, and related semiconductor structures|
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