• 专利附录
  • 专利说明
  • 权利要求
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    • 专利摘要:
    A FinFET transistor (100) comprising at least: - a channel forming fin (113), a source (114) and a drain (116), including an alternating stack of first silicon-rich SiGe portions (102) and second portions (104) a dielectric or semiconductor material, and third portions (108) of germanium rich SiGe disposed at least against side faces of the first portions, - a gate (109) covering the channel, and wherein each third portions have crystal-facing faces [111] covered by the grid.
    公开号:FR3025654A1
    申请号:FR1458487
    申请日:2014-09-10
    公开日:2016-03-11
    发明作者:Sylvain Maitrejean；Emmanuel Augendre；Louis Hutin；Yves Morand
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] FIELD OF THE INVENTION The invention relates to the field of FinFet transistors ("Fin-shaped Field Effect Transistor", or "fin-shaped field effect transistor"), as well as that of electronic devices comprising such transistors. A FET or field effect transistor is produced taking into account several criteria: the desired electrical performance, the maximum tolerated compactness or the heat dissipation to be achieved by the transistor. A FinFET type transistor is a totally descreted transistor having a very compact structure which makes it possible to maintain a good electrostatic control of the transistor, even for advanced technological nodes (28 nm and less). In such a transistor, one or more fin-shaped semiconductor portions, for example made of silicon, are produced on the surface of a substrate. The gate is made by covering the upper face and the side faces of a portion of the fin or fins which is intended to form the channel of the transistor.
    [0002] The use of SiGe rich in germanium in place of silicon for the realization of the or fins of this type of transistor makes it possible to increase the mobility of the holes in the semiconductor, and therefore to improve the performance of the transistor. In order to further increase this mobility of the holes, it is also possible to use constrained semiconductor in compression, and advantageously SiGe rich in germanium which is constrained in compression. However, because of stress relaxation occurring in a constrained semiconductor epitaxial layer when it exceeds a certain thickness, it is difficult to achieve a FinFET transistor fin which is both large and high, and which has SiGe with a high proportion of germanium. To remedy this drawback, it is possible to make the 5 or each of the fins of a FinFET transistor from a first portion of silicon or SiGe rich in silicon, then to epitaxially produce a second portion of SiGe rich in silicon. germanium covering the first portion of silicon or SiGe rich in silicon. FIGS. 1A to 2B show the steps used to produce such a finFET transistor fin.
    [0003] As shown in FIGS. 1A and 1B, the FinFET transistor vane for forming the transistor channel, source, and drain is formed by first making a first silicon-rich SiGe portion 10 on a silicon substrate. silicon 12, by epitaxy. An upper face 14 of this first portion 10 has a crystalline orientation [100] and its side faces 16 each have a crystalline orientation [110]. The SiGe of this first portion 10 is slightly constrained uni-axially in compression. This constraint, which is exerted in the direction of the length of the fin (parallel to the Y axis shown in Figures 1A and 1B), is represented symbolically by two horizontal arrows in Figure 1B.
    [0004] A second portion 18 of germanium-rich SiGe is then epitaxially grown on the first portion 10 (FIGS. 2A and 2B). As for the first portion 10, an upper face 20 of the second portion 18 has a crystalline orientation [100] and side faces 22 of the second portion 18 have a crystalline orientation [110]. The germanium-rich SiGe of the second portion 18 is strongly bi-axially constrained in compression. These constraints, which are mainly in the direction of the length of the fin and, to a lesser extent, in the direction of the height of the fin (parallel to the Z axis), are represented symbolically by four arrows in Figure 2B.
    [0005] The grid is then made on a portion of the upper face 20 and side faces 22 of the second portion 18 which forms the channel of the transistor. A FinFET transistor whose channel, source and drain are formed by such a fin, however, has several disadvantages. Indeed, this structure implies that the grid is arranged against SiGe of crystalline orientation [110]. However, strong interface states, or surface states, are in this case obtained at gate-channel interfaces, which limits the mobility of electrons in the transistor. In addition, the fact that the uni-axial nature of the stress of the semiconductor of the first portion 10 is not maintained in the semiconductor of the second portion 18 reduces the mobility of the holes in the fin of the transistor because a bi-axial constraint is less effective, in terms of hole mobility, than a uni-axial stress. SUMMARY OF THE INVENTION An object of the present invention is to propose a new FinFET transistor whose fins have SiGe with a high proportion of germanium and a high compressive stress irrespective of the geometry of the fin (s). and which has reduced interface states at the gate-channel interfaces, and thus good mobility of the electrons and holes in the transistor. For this, the present invention proposes a FinFET transistor comprising at least: a fin forming a channel, a source and a drain, comprising an alternating stack of first portions of SiGe rich in silicon and second portions of a dielectric material or semiconductor, and third portions of germanium rich SiGe disposed at least against side faces of the first portions, - a gate covering the channel, and wherein each of the third portions has crystalline orientation faces [111] covered by the grid. The or each of the fins of this FinFET transistor comprises first silicon-rich SiGe portions on which third portions of germanium-rich SiGe are made. Thus, this structure makes it possible to have a channel comprising SiGe rich in germanium strongly constrained in compression and whose geometry is not limited to avoid relaxation of the stresses as is the case for a fin formed solely of SiGe rich in germanium.
    [0006] In addition, because the gate is in contact with crystalline orientation-rich germanium SiGe [111], the interface states at the gate-channel interfaces are greatly reduced with respect to gate-SiGe interfaces. rich in crystalline orientation germanium [110] or [100]. This configuration makes it possible to improve the mobility of the electrons in the transistor.
    [0007] The term "side faces" refers to faces that are parallel to the alignment axis of the transistor channel, source, and drain (i.e., parallel to the length of the fin), and perpendicular to the faces of the first and second portions which are arranged against each other. These side faces correspond to the facing faces of which the grid is disposed on the sides of the fin, at the level of the channel. The channel is formed by the portions of the first portions and third portions that are covered by the grid. When the second portions comprise a semiconductor, the channel is also formed by the portions of these second portions which are covered by the grid.
    [0008] The term "SiGe rich in silicon" may be SiGe with a silicon content of between about 60% and 100%. The term "SiGe rich in germanium" may correspond to SiGe, the proportion of germanium of which is between about 40% and 100%.
    [0009] When the second portions comprise the semiconductor material, this material may be silicon. Advantageously, the second portions comprise the dielectric material, which makes it possible to improve the control of the threshold voltage of the transistor and to facilitate the production of the transistor. At least at the level of the channel, each of the third portions may have substantially a right prism shape with triangular bases, for example isosceles, and having three substantially rectangular sides joining said bases, one of the three sides being able to be arranged against one side faces of one of the first portions and the other two of the three sides being able to form the crystal orientation faces [111]. The bases of the right prism formed by each of the third portions may be isosceles triangular because the angle formed by the sides of the third portions with the main plane of the channel (parallel to said side faces of the first portions) is defined by the crystallographic orientations of the portions. materials. The angle between the crystalline orientation plane [111] and the main plane of the channel is, for example, equal to approximately 36 °. At least at the level of the channel, each of the third portions may have substantially a straight prism shape with trapezoidal bases, for example isosceles, and having four substantially rectangular sides joining said bases, one of the four sides being able to be arranged against the one of the lateral faces of one of the first portions and two others of the four opposite sides, which can form the crystalline orientation faces [111]. The prisms formed by the third portions may be part of the transistor channel, source and drain. These prisms may have a geometry (especially in terms of dimensions) that is similar in the channel, the source and the drain, or have, in the channel, a geometry that is different from that in the source and the drain. At least at the level of the channel, each of the third portions may be disjoint from one or two adjacent third portions such that the germanium-rich SiGe of the third portions is constrained uni-axially in compression. Such a configuration makes it possible to increase the mobility of the holes in the transistor. In this case, the grid may cover at least a portion of the side faces of the second portions. A dimension of the second portions which is substantially perpendicular to the lateral faces of the first portions may be smaller than a dimension of the first portions which is substantially perpendicular to the side faces of the first portions. Such a configuration makes it possible to have a gate that surrounds the first and third portions more closely, forming a structure close to that of an "Omega" type gate transistor, which improves the electrostatic control of the transistor. At the source and drain, each of the third portions may be in contact or superimposed with one or two third adjacent portions. This configuration improves the electrical conductivity of the transistor source and drain. At the channel, and / or the source and drain, each of the third portions may be in contact or superimposed with one or two adjacent third portions.
    [0010] The grid may cover an upper face of the alternating stack of the first and second portions. The FinFET transistor may comprise several fins each formed by a stack of first and second portions and by third portions. In this case, the transistor channel, source and drain are each formed by a portion of each of the fins. In addition, the grid covers in this case the parts of each of the fins forming the channel of the transistor. The present invention also relates to a method for producing a FinFET transistor comprising at least the steps of: - producing at least one alternating stack of first portions of SiGe rich in silicon and second portions of a dielectric material or semiconductor, making third portions of SiGe rich in germanium at least against side faces of the first portions, such that the alternating stack of the first and second portions and the third portions form a fin intended to form a channel, a source and a drain of the FinFET transistor, - making a gate covering the channel, and such that the gate covers crystalline orientation faces [111] of each of the third portions. The alternating stacking of the first and second portions can be achieved by implementing the following steps: epitaxial production of an alternating stack of 15 first SiGe layers rich in silicon and second layers of semiconductor, etching alternating stacking of the first and second layers such that remaining portions of the first and second layers form the alternating stack of the first and second portions.
    [0011] The semiconductor of the second layers may be different from the SiGe, and the embodiment of the alternating stack of the first and second portions may further comprise, after the etching of the alternating stack of the first and second layers, the steps of: selective etching of the remaining portions of the second layers with respect to the first portions; deposition of portions of the dielectric material in locations formed by the etching of the remaining portions of the second layers such that the portions of the dielectric material form the second portions of the dielectric material; alternating stacking of the first and second portions.
    [0012] The third portions may be produced by epitaxy on the lateral faces of the first portions, the duration of implementation of the epitaxy being able to be chosen as a function of the final geometry of the third portions.
    [0013] The realization of the third portions may comprise the implementation of the following steps: - production of a dummy gate covering the channel, - realization of a first portion of the third portions at parts of the alternating stack of the first and second portions 10 for forming the source and the drain, - deposition of a protective layer covering the source and the drain, - removal of the dummy gate, - realization of a second portion of the third portions at the level of a part alternating stacking of the first and second portions to form the channel. Thus, it is possible that the geometry of the third portions at the channel is different from that of the third portions at the source and the drain.
    [0014] BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be better understood on reading the description of exemplary embodiments given purely by way of indication and in no way limiting, with reference to the appended drawings, in which: FIGS. 1A to 2B show stages of production. A fin of a FinFET transistor of the prior art; FIGS. 3A and 3B show a FinFET transistor, object of the present invention, according to a first embodiment; FIGS. 4A and 4B show a FinFET transistor, object of the present invention, according to a second embodiment; FIGS. 5A and 5B show a FinFET transistor, object of the present invention, according to a third embodiment; FIGS. 6A and 6B show a FinFET transistor, object of the present invention, according to a variant of the first or third embodiment; FIGS. 7A and 8B show steps of a method for producing a FinFET transistor, object of the present invention, according to a particular embodiment; FIGS. 9A and 11B show steps of a method for producing a FinFET transistor, object of the present invention, according to an alternative embodiment; FIG. 12 represents the stress and compression obtained in SiGe as a function of the proportion of germanium in this SiGe. Identical, similar or equivalent parts of the different figures described below bear the same numerical references so as to facilitate the passage from one figure to another. The different parts shown in the figures are not necessarily in a uniform scale, to make the figures more readable. The different possibilities (variants and embodiments) must be understood as not being exclusive of each other and can be combined with one another.
    [0015] DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS Referring first to FIGS. 3A and 3B which show a FinFET transistor 100 according to a first embodiment. FIG. 3A shows a sectional view at the channel 113 of the transistor 100, and FIG. 3B shows a side view of the transistor 100. The fin of the transistor 100 forming the channel 113, the source 114 and the drain 116 of the transistor 100 comprises an alternating stack of first portions 102 of SiGe rich in silicon and second portions 104 of silicon, disposed on a substrate 106, for example silicon. The SiGe of the first portions 102 may comprise a proportion of silicon greater than or equal to about 60%. In addition, the SiGe of the first portions 102 is slightly constrained uniaxially in compression, this stress acting in the direction of the length of the fin (parallel to the Y axis shown in FIGS. 3A and 3B), the value of this constraint being a function of the proportion of germanium in the SiGe of the first portions 102 (see curve 50 of FIG. 12 described later). The height (dimension along the Z axis) of the stack is for example between about 20 nm and 80 nm, and that of each of the first and second portions 102, 104 is for example between about 4 nm and 15 nm. . The width (dimension along the X axis) of the stack (and therefore that of each of the first and second portions 102, 104) is for example between about 4 nm and 15 nm.
    [0016] Third portions 108 of germanium-rich SiGe are disposed on both side faces of each of the first portions 102, i.e. the faces parallel to the (Y, Z) plane and also perpendicular to the face of the substrate 106. on which the portions 102 and 104 are disposed. The SiGe of the third portions 108 may have a proportion of germanium greater than or equal to about 40%. Each of the third portions 108 here has substantially a right prism shape with isosceles triangular bases, that is to say has a profile (section in the plane (X, Z), or section perpendicular to the two lateral faces of the first portions 102 ) of substantially isosceles triangular shape.
    [0017] The two triangular bases of the formed prism are joined by three sides of substantially rectangular shape. One of these three sides of each of the prisms is disposed against one of the side faces of one of the first portions 102 and the other two sides of each of the prisms extend to form a stop opposite the lateral face of one of the first portions 102. The dimension of each of the third portions 108 going from the side which is disposed against the lateral face of one of the first portions 102 to its end (dimension parallel to the X axis, or perpendicular to the lateral face of the first portion 102 on which the third portion 108 is disposed is for example between about 0.4 * a and 1.5 * a, a corresponding to the height of one of the first portions 102 In this first embodiment, the third portions 108 do not cover the second portions 104. In addition, the third portions 108 are not in contact with each other, and therefore the stress of the SiGe of the third portions 108 e uni-axial st in compression in the plane (X, Y) or parallel to the face of the substrate 106 on which is the stack of portions 102 and 104. The stress in the SiGe of the third portions 108 is greater than that in the SiGe rich in silicon of the first portions 102.
    [0018] The curve 50 shown in FIG. 12 corresponds to the stress, in GPa and along the orientation axis [110], obtained in SiGe as a function of the proportion of germanium in this SiGe (in the event that it There is no stress relaxation during the process forming this SiGe). Curve 52 represents the compression obtained, in%, in this SiGe. The stress and compression values obtained in SiGe will therefore be a function of the proportion of germanium in SiGe. In addition, the epitaxy used to form the third portions 108 is such that the SiGe forming the two sides of each of the third portions 108 which are not arranged against the first portions 102 102 has a crystalline orientation [111] which allows, when this semiconductor is covered by the gate of the transistor 100, to have a better mobility of the holes and to reduce the density of the state interfaces (Dit) with respect to crystalline orientation SiGe [110] or [100].
    [0019] The portions of the stack of the first and second portions 102, 104 and the third portions 108 for forming the channel 113 of the transistor 100 (parts visible in FIG. 3A) are covered by a gate 109 comprising a gate dielectric 110, for example a high-k dielectric such as Al 2 O 3, ZrO 2, Ta 2 O 5, HfO 2, ZrSixOy, 11'203 or Ya203, and an electrically conductive material. 112 such as polysilicon and / or a metal (eg Ta, Ti, Ru, etc.). The electrically conductive material 112 may correspond to one or more superposed layers of electrically conductive materials. The gate dielectric 110 covers the upper face of the stack of the portions 102 and 104 (here the upper face of the first portion 102 at the top of the stack), the two sides of each of the third portions 108 which do not are not arranged against the first portions 102, as well as the lateral faces of the second portions 104. The remainder of the stack of the portions 102, 104 and third portions 108 forms the source 114 and the drain 116 of the transistor 100.
    [0020] Finally, spacers 118, comprising for example SiN and arranged against the conductive material 112, also cover a portion of the stack of the first and second portions 102, 104 and third portions 108 at the interfaces between the channel 113. and the source 114 and between the channel 113 and the drain 116.
    [0021] Figures 4A and 4B show the FinFET transistor 100 according to a second embodiment. Fig. 4A is a sectional view at channel 113 of transistor 100, and Fig. 4B is a side view of transistor 100.
    [0022] Compared to the first embodiment previously described, the third portions 108 of the transistor 100 according to the second embodiment cover both the lateral faces of the first portions 102 but also the lateral faces of the second portions 104. Each of the thirds portions 108 is in contact with the at least one adjacent third portion 108. This contact between the third portions 108 may be such that the adjacent third portions 108 overlap. The gate dielectric 110 thus covers the upper face of the stack of the portions 102 and 104 and the two crystal-oriented faces [111] of each of the third portions 108 which are not arranged against the first portions 102, but is not in direct contact with the side faces of the second portions 104. In this second embodiment, the dimension of each of the third portions 108 along the X axis (perpendicular to the side faces of the first and second portions 102, 104) is greater than about 0.7 * (a + b), a corresponding to the height of one of the first portions 102 and b corresponding to the height of one of the second portions 104. Compared with the first embodiment previously described, this second embodiment makes it possible to obtain a larger zone of conduction between the fin of the transistor and the gate, and thus to pass more current into the transistor. FIGS. 5A and 5B show the FinFET transistor 100 according to a third embodiment. FIG. 5A corresponds to a sectional view at the level of the channel 113 of the transistor 100, and FIG. 5B shows a side view of the transistor 100. With respect to the first embodiment previously described, each of the third portions 108 has substantially a a right prism shape with isosceles trapezoidal bases, that is to say that the third portions 108 each have a profile (section in the plane (X, Z), or section perpendicular to the two side faces of the first portions 102) of substantially isosceles trapezoidal shape, the formed trapezoid having its largest base which is disposed against one of the side faces of one of the first portions 102. The two trapezoidal bases of the formed prism are joined by four substantially rectangular shaped sides. One of the four sides of the prism is disposed against one of the side faces of one of the first portions 102, and two others of the four opposing sides form the crystal orientation faces [111]. The side of the prism opposite to that disposed against one of the side faces of one of the first portions 102, i.e. the side of the prism being at the smallest base of the trapezium, has an orientation crystalline [110]. The dimension of each of the third portions 108 along the X axis (perpendicular to the lateral faces of the first and second portions 102, 104), that is to say the distance between the two bases of the trapezoid formed by the profile of each of the third portion 108 is less than about 0.7 * a, a 15 corresponding to the height of one of the first portions 102. This third embodiment has the advantage of increasing the surface of the third portions 108 in contact with the grid 109 , and thus to pass more current in the transistor and to have better electrostatic control.
    [0023] As a variant of each of the three previously described embodiments, the second portions 104 may comprise a dielectric material, for example SiO 2, in place of the semiconductor. Such a variant has the advantage, for the first and third embodiments, of facilitating the selective growth of the SiGe of the third portions 108 only on the first portions 102 and not on the second portions 104. Moreover, for the three modes of embodiment, this variant makes it possible to better control the value of the threshold voltage of the transistor 100 because of the absence of conduction in the second portions 104, and therefore of the absence of threshold voltages for these second portions 104.
    [0024] In the first and third embodiments, it is possible that the width (dimension along the X axis) of the second portions 104 is smaller than that of the first portions 102. Thus, the grid 109 further surrounds the first portions 102. and the third portions 108, which makes it possible to improve the electrostatic control of the transistor 100. The shape of the grid thus obtained is close to that of an "Omega" type grating which surrounds a large part of the channel of a such a transistor. This variant is particularly applicable when the second portions 104 comprise a dielectric material.
    [0025] In the first and third embodiments described above, the third adjacent portions 108 are not contiguous with each other, as much at the channel 113 as at the source 114 and the drain 116. In a variant, it is It is possible for the portions of these adjacent third portions 108 at source 114 and drain 116 to join or overlap each other while the portions of these adjacent third portions 108 are at the channel level. 113 are not joined or overlap with each other. FIG. 6A corresponds to a sectional view taken at the level of the drain 116 of a transistor 100 according to such a variant. Figure 6B is a side view of a transistor 100 according to this variant. A profile sectional view of such a transistor at the channel 113 corresponds for example to that of Figure 3A, 4A or 5A. A method of producing transistor 100 according to the first embodiment is described with reference to FIGS. 7A to 8B.
    [0026] An alternating stack of semiconductor layers, for example silicon, and SiGe rich in silicon is formed on the substrate 106, for example by epitaxy. An etching of the stack of layers is then performed so that remaining portions of this stack of layers form the alternating stack of first portions 102 and second portions 104 (FIGS. 7A and 7B). Alternatively, when the second portions 104 are intended to be formed of a dielectric material, the remaining portions of the silicon layers of the stack can be selectively etched in an isotropic manner with respect to the first portions 102. Portions of the stack of layers connected to the portions intended to form the transistor 100 are preserved and not subjected to this selective etching in order to ensure the mechanical maintenance of the first portions 102 after etching of the remaining portions of the silicon layers of the stack. The dielectric material, for example SiO 2, is then deposited, for example by CVD deposition, in the previously etched locations, forming the second portions 104. The portions of dielectric material deposited outside these locations are etched selectively and isotropically.
    [0027] Doping (for example in situ or by implantation or plasma) of the first portions 102 can be implemented in order to adjust the threshold voltage that will be obtained in these first portions 102, for example at a value similar to that which will be obtained in the germanium-rich SiGe of the third portions 108.
    [0028] When the second portions 104 comprise semiconductor, it is possible to doping this semiconductor to inhibit this semiconductor and to avoid electrical conduction therein. Only the first portions 102 of this stack will then serve to form, from an electrical point of view, the channel, the source and the drain of the transistor.
    [0029] As shown in FIGS. 8A and 8B, the third portions 108 of germanium-rich SiGe are then epitaxially grown on the side faces of the first portions 102. The epitaxial growth employed is controlled so that the third portions 108 each have a triangular shape profile. For the realization of the third portions 108 of the transistor 100 according to the second embodiment, this growth is prolonged until the desired geometry is obtained. In contrast, for the realization of the third portions 108 of the transistor 100 according to the third embodiment, this growth is interrupted earlier so that the third portions 108 obtained each have a trapezoidal profile. The epitaxy forming the third portions 108 may be carried out at a temperature between about 500 ° C and 750 ° C and in the presence of active gases such as SiH4, dichlorosilane, or GeH4. HCI may be used, for example cycled or introduced together with the active gases, to obtain a selectivity as to where the third portions 108 are to be located, for example only on the side faces of the first portions 102. Facets [111] will appear naturally during epitaxy. After or before making the third portions 108, the second portions 104 may be partially etched such that the width of the second portions 104 is smaller than that of the first portions 102, as previously described. The transistor 100 is then completed by depositing the gate dielectric 110 in a conformal manner on the top face of the stack of the first and second portions 102, 104, on the faces of the third portions 108 which are exposed (ie say all the faces except those in contact with the stack of the portions 102, 104) and on the lateral faces of the second portions 104, at the level of the channel 113. In the case of the second embodiment in which the lateral faces of the second Portions 104 are covered by the third portions 108, the gate dielectric 110 only covers the top face of the stack of the first and second portions 102, 104 and the faces of the third portions 108 which are exposed. The gate dielectric 110 is for example formed by an ALD deposit ("Atomic Layer Deposition" or "atomic layer deposition"). The conductive material 112 is then deposited on the gate dielectric 110. The structure obtained corresponds to one of those shown in FIGS. 3A to 5B. A germanium rich SiGe epitaxy may be implemented after the realization of the gate so that at the source 114 and the drain 116, the third portions 108 completely cover the faces of the stack of the first and second portions. 102, 104, as previously described with reference to FIGS. 6A and 6B. An alternative embodiment of the transistor 100 is described below.
    [0030] The steps previously described in connection with FIGS. 7A and 7B are first implemented. Then, a dummy gate 119 is formed, covering the portion of the stack of the first and second portions 102, 104 intended to form the channel 113 of the transistor 100 (FIGS. 9A and 9B). This dummy gate 119 is for example formed by forming a first portion 120 of dielectric material, for example SiO 2, covering this portion of the stack, then depositing on the first portion 120 a second portion 122 of material capable of being etched selectively with respect to the dielectric material of the first portion 120, for example polysilicon. The spacers 118 are also made against the dummy gate 119, at the interfaces between the channel 113 and the source 114 and between the channel 113 and the drain 116. An epitaxy of SiGe rich in germanium is then implemented only at the the source and the drain due to the presence of the dummy gate 119 which protects the part of the stack of portions 102, 104 intended to form the channel 113. The parts of the third portions 118 located at the source 114 and of the drain 116 are thus formed. The source 114 and the drain 116 are then protected by a deposit of a protective layer 124 comprising, for example, SiO 2, then the dummy gate 119 is removed (FIGS. 10A and 10B).
    [0031] A germanium rich SiGe epitaxy is then implemented to form the portions of the third portions 108 at the channel 113 (Figs. 11A and 11B). The process is completed by realizing the gate dielectric 110 and the conductive material 112 at the channel 113, and then removing the protective layer 124 covering the source 114 and the drain 116. Alternatively, the protective layer 124 of the source 114 and drain 116 may be removed prior to the implementation of the germanium-rich SiGe epitaxy step forming portions of the third portions 108 at channel 113, thereby forming germanium-rich SiGe also in the source 114 and the drain 116. In the modes and embodiments described above, the FinFET 100 transistor comprises a single fin forming the channel 113, the source 114 and the drain 116. In a variant, the FinFET 100 transistor may comprise a plurality of fins each formed by a stack of first and second portions and third portions in a manner similar to the previously described fin. In this case, the channel, the source and the drain of the transistor are each formed by a portion of each of the fins. In addition, the grid covers in this case the parts of each of the fins forming the channel of the transistor. In the previously described embodiments and embodiments, the first portions 102 and the second portions 104 have similar dimensions (height along the Z axis, width along the X axis). Alternatively, it is possible that the first portions 102 have dimensions (height and / or width) different from those of the second portions 104, or that the first portions 102 and / or the second portions 104 do not have all the same dimensions (for example by performing the etching of the stack of layers, which forms the alternating stack or stacks of the first portions 102 and second portions 104, with a certain angle so that the stack or stacks 3025654 alternated first portions 102 and second portions 104 have larger sizes at their base and smaller dimensions at their apex, or alternatively protecting the base of the stack or piles while etching reduces dimensions at the top of the or 5 stacks).
    权利要求:
    Claims (14)
    [0001]
    REVENDICATIONS1. A FinFET transistor (100) having at least: a fin forming a channel (113), a source (114) and a drain (116), having an alternating stack of first portions (102) of silicon-rich SiGe and second portions ( 104) of a dielectric or semiconductor material, and third portions (108) of germanium rich SiGe arranged at least against side faces of the first portions (102), - a gate (109) covering the channel (113) and wherein each of the third portions (108) has crystal-facing faces [111] covered by the grid (109).
    [0002]
    A FinFET transistor (100) according to claim 1, wherein, at least at the channel (113), each of the third portions (108) is substantially triangular in shape and has three substantially rectangular sides joining said bases, one of the three sides being disposed against one of the side faces of one of the first portions (102) and the other two of the three sides forming the crystalline orientation faces [111].
    [0003]
    A FinFET transistor (100) according to claim 1, wherein, at least at the channel (113), each of the third portions (108) is substantially trapezoidal-shaped and has four substantially rectangular sides joining said bases, one of the four sides being arranged against one of the lateral faces of one of the first portions (102) and two others of the four opposite sides, forming the crystalline orientation faces [ 111]. 3025654 22
    [0004]
    4. FinFET transistor (100) according to one of the preceding claims, wherein, at least at the channel (113), each of the third portions (108) is disjoint from one or two third portions (108) adjacent such that the SiGe rich in germanium of the third portions (108) 5 is constrained uniaxially in compression.
    [0005]
    5. FinFET transistor (100) according to claim 4, wherein the gate (109) covers at least a portion of the side faces of the second portions (104). 10
    [0006]
    The FinFET transistor (100) according to one of the preceding claims, wherein a dimension of the second portions (104) which is substantially perpendicular to the side faces of the first portions (102) is smaller than a dimension of the first portions (102) which substantially perpendicular to the side faces of the first portions (102).
    [0007]
    The FinFET transistor (100) according to one of the preceding claims, wherein, at the source (114) and the drain (116), each of the third portions (108) is in contact or superimposed with one or two Third portions (108) adjacent thereto.
    [0008]
    8. FinFET transistor (100) according to one of claims 1 to 3, wherein, at the channel (113), and / or the source (114) and the drain (116), each of the third portions (108) ) is in contact or superimposed with one or two adjacent third portions (108).
    [0009]
    9. FinFET transistor (100) according to one of the preceding claims, wherein the gate (109) covers an upper face of the alternating stack of the first and second portions (102, 104). 3025654 23
    [0010]
    10. A method of producing a FinFET transistor (100) comprising at least the steps of: - producing at least one alternating stack of first portions (102) of SiGe rich in silicon and second portions (104) of a Dielectric or semiconductor material, - making third portions (108) of germanium-rich SiGe at least against side faces of the first portions (102), such as alternating stacking of the first and second portions (102, 104) and the third portions (108) form a fin for forming a channel (113), a source (114) and a drain (116) of the FinFET transistor (100), - providing a gate (109) covering the channel (113), and such that the grid (109) covers crystalline orientation faces [111] of each of the third portions (108). 15
    [0011]
    11. The method of claim 10, wherein the alternating stack of the first and second portions (102, 104) is achieved by the implementation of the following steps: - epitaxial production of an alternating stack of first layers of rich SiGe in silicon and second semiconductor layers, etching of the alternating stack of the first and second layers such that remaining portions of the first and second layers form the alternating stack of the first and second portions (102, 104). 25
    [0012]
    The method of claim 11, wherein the semiconductor of the second layers is different from the SiGe, and wherein performing the alternating stack of the first and second portions (102, 104) further comprises, after etching of the alternating stack of the first and second layers, the steps of: - selective etching of the remaining portions of the second layers with respect to the first portions (102), - deposition of portions of the dielectric material in locations formed by the etching of the portions remaining second layers such that the portions of the dielectric material form the second portions (104) of the alternating stack of the first and second portions (102, 104).
    [0013]
    13. Method according to one of claims 10 to 12, wherein the third portions (108) are produced epitaxially on the side faces of the first portions (102), the duration of implementation of the epitaxy being chosen in function of the final geometry of the third portions (108).
    [0014]
    14. Method according to one of claims 10 to 13, wherein the realization of the third portions (108) comprises the implementation of the following steps: - realization of a dummy gate (119) covering the channel (113), - Making a first portion of the third portions (108) at portions of the alternating stack of first and second portions (102, 104) for forming the source (114) and the drain (116), - deposit a protective layer (124) covering the source (114) and the drain (116), removing the dummy gate (119), producing a second portion of the third portions (108) at a portion alternating stack of first and second portions (102, 104) for forming the channel (113).
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    FR3088480B1|2018-11-09|2020-12-04|Commissariat Energie Atomique|BONDING PROCESS WITH ELECTRONICALLY STIMULATED DESORPTION|
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1458487A|FR3025654B1|2014-09-10|2014-09-10|TRANSISTOR FINFET COMPRISING CRYSTALLINE ORIENTATION SIGE PORTIONS [111]|FR1458487A| FR3025654B1|2014-09-10|2014-09-10|TRANSISTOR FINFET COMPRISING CRYSTALLINE ORIENTATION SIGE PORTIONS [111]|
    US14/849,060| US9536951B2|2014-09-10|2015-09-09|FinFET transistor comprising portions of SiGe with a crystal orientation [111]|
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