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    • 专利摘要:
    Memory device comprising at least: - an array of memory cells (102) SRAM each having four first FDSOI transistors (104, 106, 108, 110) forming two inverters mounted head to tail, two second FDSOI transistors (116, 118) of write access, and: each cell also comprises two third FDSOI transistors (126, 128) for read access, the first and second transistors comprising a first well (125) of a first conductivity type and the third transistors comprising a second well (133) of a second conductivity type, or • the second transistors form read access transistors, the N-type transistors comprising the first well and the P-type transistors comprising the second well; means of polarization of the second caissons, able to select a value of at least one polarization potential of the second caissons and to apply said polarization potential to the second caissons.
    公开号:FR3025653A1
    申请号:FR1458488
    申请日:2014-09-10
    公开日:2016-03-11
    发明作者:Olivier Thomas；Bastien Giraud；Adam Makosiej
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] TECHNICAL FIELD AND PRIOR ART The invention relates to the field of static random access memories (SRAMs) operating over a very wide range of values of memory elements. supply voltage, and for example used in portable electronic devices such as smartphones (or smart phones), digital tablets, laptops, etc. For modern portable applications called high performance and low power, it is interesting to use integrated circuits designed to operate over a very wide range of supply voltage values to be able to dynamically adjust the voltage value power these circuits according to their use, and thus optimize the energy efficiency of these circuits and reduce their power consumption to save battery time. In digital integrated circuits, the possible values of the supply voltage of these circuits are generally limited by the memories of these circuits. Indeed, the variability of the CMOS transistors present in the memories prevents them from operating at a supply voltage as low as that of the elements forming the logic of the integrated circuits because the architecture of the memories leads to a degradation of their performances more important for the elements forming the logic when the supply voltage is reduced. For example, by reducing the supply voltage, the access time of the SRAMs increases more rapidly than the propagation time of the logic circuits.
    [0002] 3025653 2 In integrated circuits, several types of memories are used. The closer the memory is to the computing unit, the more its performance and operating conditions are similar to those of the computing unit. Thus, the cache memory L1, which is glued to the computing unit, is generally designed from SRAM memory cells with 6 or 8 transistors (called 6T or 8T). These memory cells are developed to achieve the best compromise of the following criteria: good stability of the stored information, ease of writing, maximum read current (ICELL) for good performance, reasonable cell size to have a high integration density associated with low performance degradations due to metallization of the cell, and a minimal retention current (10FF) to minimize the static power consumed. Dispersions obtained with decananometric CMOS technologies of 28 nm and less, however, make it impossible to guarantee these criteria with a high efficiency (of the order of 5 to 6 sigmas, ie an error rate of about 10-9). . At low voltage, these conditions are even more difficult to achieve. In parallel to these considerations, the reduction of the dimensions of the electronic components requires the use of new technologies for the realization of these integrated circuits. Thus, for the 28 nm and below technological nodes, the FDSOI technology ("Fully Depleted Silicon-On-Insulator" or "silicon on insulator completely deserted") makes it possible to improve the electrostatic control and the dispersions of the MOS transistors. In addition, the threshold voltage of an FDSOI transistor can be adjusted by doping and polarization on the back of the transistor. Wells, N-type or 3025653P can be used for both NMOS and PMOS transistors. This FDSOI technology provides a way to improve the performance of memory circuits without additional design efforts. The document "6T SRAM Design for Wide Voltage Range in 28nm 5 FDSOI" by O. Thomas et al., SOI Conference (S01), 2012 IEEE International, 1-4 Oct. 2012, Napa, CA, pages 1-2, describes a memory cell 6T made of 28 nm FDSOI technology whose architecture mono-P-Well (a single P-type box common to the six transistors of the memory cell) makes it possible to reduce the value of the supply voltage of the transistors of the cell, especially by improving the writing. However, the optimization of the writing and the reading remain dependent on each other. However, the reduction of the supply voltage causes a decrease in the possible reading speed. The "An Area-Conscious Low-Voltage-Oriented 8TSRAM Design under DVS Environment" by Y. Morita et al., VLSI Circuits, 2007 IEEE 15 Symposium on, June 14-16, 2007, Kyoto, JP, pages 256 - 257, discloses a memory cell 8T which comprises, with respect to a memory cell 6T, two additional transistors forming the read port of the cell. This reading port makes it possible to de-correlate the reading of the writing done in the cell because during a reading, the two access transistors used for writing in the cell remain in the off state. As for a 6T memory cell, this alternative can be improved thanks to the FDSOI technology. However, a decrease in the supply voltage of the transistors of the cell still causes a decrease in the reading speed that can be achieved by such a memory cell. In addition, for high performance applications, whether the memory cells have 6 or 8 transistors, the performance of the memory circuits is affected by timing or synchronism errors in reading and writing. A reading timing fault is due to a cell read current that is too low to quickly discharge a bit line in the access time. A write timing fault is due to the time of 3025653 4 switching too long a memory cell to properly store a bit. Reading timing faults can also be caused by a too long write time because in this case, the completion of the logical level "1", that is to say the transition of the potential of the node of the logic level "0". To the logic level "1" when writing, is not complete (the completion can be completed during the next cycle), which limits the read current in this next cycle if it is of a reading because the potential in the node is then lower than the potential corresponding to the logic level "1". However, the number of memory cells exhibiting such a malfunction increases when the supply voltage of the memory cells is reduced. At the level of the matrix of memory cells, column redundancy or cell line solutions have been proposed to overcome these problems, as described for example in the document "Row / Column Redundancy to Reduce SRAM Leakage in Presence of Random Within". -Die 15 Delay Variation "by M. Goudarzi et al., Low Power Electronics and Design (ISLPED), 2008 ACM / IEEE International Symposium on, 11-13 Aug. 2008, Bangalore, pp. 93-98. These redundancies are used to replace the columns or lines of non-functional memory cells, ie the columns or rows of cells whose one or more cells cause timing errors in reading and / or writing. The number of columns or redundant lines possible is however limited because a certain density of the matrix must still be retained. In addition, this solution requires reprogramming the access circuits to the matrix. There are also solutions based on error correction codes, or ECCs. They associate complementary bits with a word that can detect and possibly correct errors. The programming of the complementary bits is done via an encoding logic and verification by a decoding logic. ECCs are very efficient in responding to "software" errors (assumed to be small in quantity) but not 3025653 suitable for low voltage applications where the error rate increases very rapidly. SUMMARY OF THE INVENTION An object of the present invention is to propose a new memory device comprising SRAM memory cells based on FDSOI transistors that can operate over a wide range of supply voltage values, and in particular operate with a low voltage. by greatly reducing the impact of such a drop in supply voltage on the reading speed of the memory cells. An object of the present invention is also to reduce the occurrence of timing errors in reading and writing memory cells even when a low supply voltage is used and without the need to resort to memory cell redundancy solutions or error correction codes. For this, the present invention proposes a memory device 15 comprising at least: a matrix of memory cells of SRAM type, each memory cell comprising at least four first FDSOI transistors forming two inverters mounted head to tail and two second FDSOI transistors forming at least write access transistors, and wherein: each memory cell further comprises two third FDSOI transistors forming read access transistors, the first and second FDSOI transistors comprising a first doped semiconductor well of a first type; and the third FDSOI transistors having a second doped semiconductor well 25 of a second conductivity type opposite to the first conductivity type, OR - the second FDSOI transistors also form read access transistors of the memory cell, the type N transistors 3025653 6 among the first and second transistors comprising the first well and the P-type transistors of the first and second transistors comprising the second well, means for polarizing the second wells, capable of selecting a value of at least one polarization potential of the second wells and applying said bias potential to the second wells. The memory device according to the invention makes it possible to optimize the energy efficiency / efficiency compromise of the memory cells. It represents an effective means in particular to cope with the increase in dispersions of deca-nanometric CMOS technologies (28 nm and below). The approach is made possible by FDSOI technology and the architecture of SRAM 6T or 8T memory cells. The memory device can adjust the reading current of the SRAM cells by playing either on the polarization of the rear face of the reading port transistors in the case of memory cells 8T, or on the polarization of the rear face of the P-type transistors. in the case of 6T memory cells. In the case of memory cells 8T, according to the value of the biasing electric potential selected and applied to the second boxes, the value of the threshold voltage of the transistors of the read ports is modified.
    [0003] By modulating the value of the threshold voltage of the transistors forming the reading ports of the cells, the reading speed of the cells is also modulated, which makes it possible to compensate for the changes in the reading speed generated by a modification of the value of the supply voltage of the cells. Thus, it is possible to reduce the value of the supply voltage of the memory cells, which has the effect of increasing the reading time of the cells, this increase in the reading time being able to be compensated by a drop in the voltage threshold of the transistors of the reading ports of the cells which has the effect of accelerating the discharge time of the read bit lines through the transistors of the read ports.
    [0004] In the case of memory cells 6T, that is to say when the second FDSOI transistors also form read access transistors of the memory cell, the N-type transistors among the first and second transistors comprising the first box and P type transistors among the first and second transistors having the second box, the write performance and stability are improved by selecting the value of the selected bias electric potential and applied to the second boxes. A compromise between raising and lowering the threshold voltage is sought to improve retention and writing.
    [0005] It is possible to control overall polarization potentials applied to the second cells of the memory cells of the matrix, that is to say to apply the same potential on all the second boxes, which allows to adjust the performance memory device according to the needs of speed and consumption of the device.
    [0006] It is also possible to control locally the polarization potentials applied to the second cells of the memory cells of the matrix, that is to say to differentiate, for example by columns or groups of two adjacent columns of memory cells, the potentials. biasing applied on the second boxes, which allows for example to increase the low reading current of some memory cells without affecting the static consumption of the entire memory device. Local control thus achieved provides a means both dense and adjustable (over time) to improve the read performance of memory cells. Moreover, by memorizing the possible polarization states of the second cells, for example for each column or group of two adjacent columns of memory cells, the polarization of the rear face of the transistors of the read ports of the memory cells of the columns can be adjustable over time depending on the conditions of use of the memory.
    [0007] The memory device according to the invention also represents a solution to the problems of variability, or dispersion, of the reading current observed for the FDSOI transistors. Indeed, the problems of variability of the reading current of the transistors are all the more important that the supply voltage of these transistors is low. Thus, by independently controlling, for example for each column or each group of two adjacent columns, the polarization of the transistors of the reading ports of the cells, it is possible to choose, for the columns or groups of two adjacent columns whose cells, or a part of the cells, are the least efficient and / or involve read errors under given read access conditions, a polarization potential of the second boxes of the transistors of the reading ports which is higher than that applied for the others. adjacent columns or groups of columns of the matrix in order to increase the value of the threshold voltage of these transistors.
    [0008] The term "caisson" refers to a doped semiconductor portion under the buried oxide of each FDSOI transistor and forming the ground plane ("Ground Plane" or "Back Plane") of each FDSOI transistor. The memory cells may be arranged next to one another by forming several columns of memory cells, and the second cells of the memory cells of one and the same column may be formed by the same portion of semiconductor doped according to the second type of memory. conductivity. Thus, a single polarization potential can be applied to all the second cells of the same column of memory cells. Advantageously, the third transistors of the memory cells of two adjacent columns or of each group of two adjacent columns may be arranged next to one another such as the second cells of the memory cells of the two adjacent columns or each of the groups of cells. two adjacent columns may be formed by the same portion of semiconductor doped according to the second type of conductivity. Thus, only one polarization potential can be applied to all the second cells of the same group of two adjacent columns of memory cells. The polarization means of the second cells of the memory cells may comprise: a memory circuit able to memorize a state of polarization of the second cells of the memory cells for each column or group of two adjacent columns; a selection circuit coupled to the memory circuit, comprising several inputs on which different polarization potential values are intended to be applied and able to apply on the second cells memory cells of each column or group of two adjacent columns one said selected bias potential values as a function of the polarization state stored in the memory circuit and associated with said column or said group of two adjacent columns.
    [0009] In this case, the selection circuit may comprise several multiplexers each having several inputs on which said bias potential values are intended to be applied and an output connected to the second cells of the memory cells of one of the columns or of a group. two adjacent columns.
    [0010] The memory circuit may comprise at least one memory cell of each column and be such that each of said memory cells may be able to store a polarization state of the second cells of the memory cells of the column to which said memory cell belongs or that two of said memory cells Memory cells may be capable of storing a polarization state of the second cells of the memory cells of a group of two adjacent columns of which said memory cells are part. The polarization means of the second cells of the memory cells may further comprise: a test circuit coupled to the matrix of memory cells and able to detect if one or more memory cells have a reading speed generating reading errors; a control circuit coupled to the test circuit and to the memory circuit and capable of defining the polarization states intended to be stored in the memory circuit as a function of the results provided by the test circuit. Thus, it is for example possible to reduce the supply voltage only of the memory cells of the columns or groups of two adjacent columns of which no cell generates a read error.
    [0011] The first type of conductivity may correspond to the type P and the second type of conductivity may correspond to the type N. The memory device may further comprise polarization means of the first wells of the memory cells capable of applying a zero polarization potential on the first caissons.
    [0012] The invention also relates to a method of biasing a memory device as defined above, comprising steps of: - selecting a value of at least one polarization potential of the second boxes, and - application of said potential polarization on the second 20 boxes. A value of a supply voltage of the memory cells of the memory device and the value of said at least one polarization potential can be chosen according to a desired read speed and power consumption of the memory device.
    [0013] The method may be such that: the memory cells may be arranged next to each other forming several columns of memory cells, the second cells of the memory cells of the same column being able to be formed by the same portion of doped semiconductor according to the second type of conductivity, and / or - the third transistors of the memory cells of two adjacent columns or of each group of two adjacent columns may be arranged next to one another such as the second cells of the cells. The memories of the two adjacent columns or of each of the groups of two adjacent columns may be formed by one and the same portion of semiconductor doped according to the second type of conductivity, the method may also comprise a step of memorizing a state of polarization of the second boxes of memory cells for each column or group of two adjacent columns and the selecting step may perform a selection of one of different polarization potential values as a function of the polarization state stored in the memory circuit and associated with said column or said group of two adjacent columns. In this case, the method may further comprise a step of testing the matrix of memory cells detecting whether one or more memory cells have a read speed generating read errors, and a step of determining the polarization states intended to be stored according to results of the test step. The value of the bias potential applied to at least a portion of the second boxes may be strictly positive. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be better understood on reading the description of exemplary embodiments given purely by way of indication and in no way limiting, with reference to the appended drawings, in which: FIG. 1 schematically represents an 8T memory cell; a memory device object of the present invention; FIG. 2 diagrammatically represents a matrix of memory cells of a memory device that is the subject of the present invention; FIG. 3 diagrammatically represents a memory device, object of the present invention, according to a particular embodiment; FIG. 4 diagrammatically represents a part of a memory device, object of the present invention, according to an alternative embodiment; FIG. 5 schematically represents a memory cell 6T of a memory device that is the subject of the present invention. Identical, similar or equivalent parts of the different figures described below bear the same numerical references so as to facilitate the passage from one figure to another. The different parts shown in the figures are not necessarily in a uniform scale, to make the figures more readable. The different possibilities (variants and embodiments) must be understood as not being exclusive of each other and can be combined with one another.
    [0014] DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS Referring first to FIG. 1 which schematically shows an 8T memory cell 102 of a memory device 100 according to a particular embodiment. The cell 102 comprises two NMOS transistors 104, 106 and two PMOS transistors 108, 110 forming together two inverters mounted head-to-tail corresponding to the memory point of the cell 102, connected to a power supply terminal 112 on which a voltage potential is applied. VDD supply, for example equal to about 1 V, and a reference potential 114 corresponding for example to the ground of the device 100. The cell 102 also comprises two access transistors 116, 118, here of NMOS type, having their gate connected to a write word line 120 on which a write commanding signal in the cell 102 is to be sent, their drain connected to write bit lines 122, 124 on which the data flows. to memorize, and their source connected to the inverters. Transistors 104 to 110, 116 and 118 are FDSOI transistors comprising a first p-type ("P-Well") semiconductor well 125 that forms the ground plane of these transistors. This first well 125 is common to transistors 104 to 110, 116 and 118 of cell 102.
    [0015] A zero electric potential, for example that of the mass of the device 100, is applied to this first box 125. The cell 102 also comprises two NMOS transistors 126, 128 forming a reading port of the cell 102. gate connected to a read word line 130, its drain connected to a read bit line 132 and its source connected to the drain of transistor 128. The gate of transistor 128 is connected to the memory point of cell 102 and the source of transistor 128 is connected to the reference electric potential 114. Prior to reading the bit stored in the cell 102, the electric potential of the read bit line 132 is pre-loaded to VDD.
    [0016] The transistor 126 is then turned on by the application of a read control signal, corresponding for example to a potential pulse equal to VDD, on its gate from the read word line 130. According to the value of the bit stored in the cell 102, the transistor 128 is on (bit in state "1") or not (bit in state "0"), which causes a more or less significant discharge 25 of the read current from the reading bit line 132 through transistors 126, 128 according to the value of the bit stored in cell 102. Transistors 126 and 128 are FDSOI transistors comprising a second common N-type well 133 forming the plane mass of these transistors. An electric potential VNw is applied to the second well 133 of the transistors 126, 128, the value of this potential being between 0 and VDDH, with the value of VDDH which may be greater than or equal to that of VDD, and set in depending on the desired operating mode of the cell 102, i.e., the selected read / consumption rate compromise, as will be described later. In Figure 1, the two boxes 125 and 133 of different types are separated symbolically by dashed lines. The device 100 has several memory cells similar to the cell 102 shown in FIG. 1 and arranged next to one another forming one or more cell matrices. FIG. 2 schematically represents sixteen memory cells 102.1 - 102.16 similar to the cell 102 previously described and arranged forming a 4x4 matrix referenced 134. The memory cells 102.1 - 102.16 are made such that the reading ports of the cells of the same column of the matrix are arranged one above the other. Thus, the transistors 104 to 110, 116 and 118 of the cells of one and the same column are made on the same portion of P-doped semiconductor forming the first wells of the transistors of these cells, and the transistors 126 and 128 forming the read ports of the cells of the same column are formed on an N-doped semiconductor portion forming the second caissons of the transistors of these cells. The configuration shown in Figure 2 is advantageous because the reading ports of the cells of two adjacent columns are arranged next to each other. Thus, the second wells of the transistors 126 and 128 of the cells of these two columns are formed by the same portion of N-doped semiconductor. In the example of FIG. 2, the transistors of the reading ports of the cells 102.1 to 102.8 comprise a single portion of N-doped semiconductor common to these cells and forming the second wells of transistors 126 and 128 of these cells 102.1 - 102.8. The transistors of the read ports of the cells 102.9 to 102.16 include another portion of the N-doped conductive semiconductor forming the second wells of the transistors 126 and 128 of these cells 102.9-102.16. In addition, this configuration also allows transistors 104 to 110, 116 and 118 to have two-column cells whose reading ports are not arranged next to each other to have a single portion of P-doped semiconductor forming the first boxes of these transistors. Thus, in the example of FIG. 2, the transistors 104 to 110, 116 and 118 of the cells 102.5 to 102.12 are made on the same portion of P-doped semiconductor forming the first wells of these transistors. The caissons of the FDSOI transistors of the memory cells 10 correspond to highly doped semiconductor regions arranged beneath the buried dielectrics (BOX) of these transistors and which make it possible, depending on the value of the electric polarization potential applied to them, to modify the value of the threshold voltage of the transistors. By modulating the value of the threshold voltage of the transistors forming the read ports of the cells, the reading speed of the cells is also modulated, which makes it possible to compensate for the changes in the reading speed caused by a modification of the value of the supply voltage of the cells. Thus, it is possible to reduce the value of the supply voltage of the transistors of the memory cells, which has the effect of increasing the reading time of the cells, this increase in the reading time being able to be offset by a decrease in the threshold voltage of the transistors of the read ports of the cells which has the effect of accelerating the discharge of the current from the read bit lines through the transistors of the read ports. Various exemplary modes of operation of the memory cells 102 of the device 100, corresponding to different time / power consumption compromises of the cells, are described below. In a first mode of operation, when the memory cells 102 are intended to operate as quickly as possible in reading, without seeking to reduce the power consumption of these cells, the VDD supply potential of all the transistors of the memory cells is chosen the highest possible, for example equal to about 1.3 V, and the polarization potential V Nw of the second cells of the transistors of the reading ports of the cells is also chosen as high as possible, that is to say equal to VDDH which is for example between 2 and 3 V. In a second mode of operation, when the memory cells 102 are intended to operate with their nominal reading speed, the value of the supply voltage VDD of all the transistors of the memory cells is lowered compared to that used in the first mode of operation, and for example set between about 0.6 V and 1.3 V, and by for example equal to about 1 V. The value of the bias potential V Nw of the second wells of the transistors of the read ports of the cells is also lowered relative to the first operating mode, and for example fixed between approximately VDD and 0 V. Thus, the consumption of the memory cells is lowered compared to that of the first mode of operation, without greatly affecting the reading speed of the memory cells. As a variant, it is possible to lower only the value of VDD and to keep a high value of the potential VNW. In a third mode of operation in which a very low consumption of the memory cells is sought, the supply potential VDD of the transistors is for example set to a value equal to approximately 0.6 V and the potential Vw is set to OV. In a fourth mode of operation in which the memory cells achieve a retention of the values of the stored bits, without reading or writing being performed, the supply potential VDD is chosen as low as possible, for example equal to about 0.4 V, and the value of the bias potential Vw of the second wells of the transistors of the read ports of the cells is negative so that the read transistors are reverse biased, and for example between 0 and about -300 mV.
    [0017] Thus, for performance constraints that are low or when the memory cells are in a storage mode, or information retention, the second wells of the transistors of the read ports of the cells can be biased with a potential of zero polarization, 5 see negatively polarized, which allows to minimize the leakage currents through these transistors. Conversely, for high performance constraints, the second wells of the transistors of the read ports of the cells may be biased with a potential of value equal to or greater than VDD, thereby increasing the value of the read current of the cells via the 10 reduction of the threshold voltage of the transistors of the reading ports. The value of the supply voltage VDD is the same for all the transistors of the memory cells 102 of the device 100. In a first exemplary embodiment, the value of the potential VNW applied to the second cells of the transistors of the reading ports of the cells 102 can be the same for all the cells of the same matrix of cells. In this case, the compromise between read / consumption time is managed globally for the entire matrix of cells 102. In a second exemplary embodiment, when the read ports of the cells of two adjacent columns are arranged next to each other. other, as in the example of Figure 2, the polarization of the second boxes of the transistors of the read ports of such cells can be controlled independently for each group of two adjacent columns. For example, in the case shown in FIG. 2, the bias potential VNW applied to the second wells of the transistors of the reading ports of the cells 102.1 to 102.8 can be chosen independently of that applied to the second wells of the transistors of the reading cells 102.9 to 102.16. In a third exemplary embodiment, when the reading ports of the cells of the columns are not arranged next to one another, the polarization of the second wells of the transistors of the read ports of such cells can be controlled independently for each of the columns. In the second and third exemplary embodiments above, the independent bias for each column or group of two adjacent columns represents a solution to the problems of variability, or dispersion, of the read current observed for the FDSOI transistors. Indeed, the problems of variability of the reading current of the transistors are all the more important that the supply voltage of these transistors is low. Thus, by independently controlling for each column or each group of two adjacent columns the polarization of the transistors of the reading ports of the cells, it is possible to choose, for the columns or groups of two adjacent columns whose cells, or a portion of the cells , are the least efficient and / or involve read errors under given read access conditions, a bias potential of the second boxes 15 of the read port transistors which is higher than that applied for the other columns or groups columns to reduce the value of the threshold voltage of these transistors. When the polarization of the second boxes of the transistors of the read ports is managed globally for all the cells of the same matrix (the polarization potential of the second boxes of the transistors of the read ports being the same for all the memory cells of the matrix) and that the device comprises several matrices of memory cells, the choice of the value of the polarization potential of the second boxes of the transistors of the reading ports can be achieved at the matrix level, that is to say by choosing this value depending on whether or not the matrix in question has less efficient cells and / or involves reading errors under given read access conditions. In the previously described examples, the first P-type boxes of the transistors 104 to 110, 116 and 118 of the memory cells 102, that is to say the transistors other than those of the reading port, can be connected to the mass, which corresponds to the application of an electric potential of zero polarization on these caissons. In a variant, when the second wells of the transistors of the read ports are negatively polarized, the first P-type wells 5 can also be negatively polarized, for example at the same potential level as that applied to the second wells of the transistors of the reading. FIG. 3 diagrammatically represents the memory device 100, and in particular the elements of the device 100 controlling or controlling the polarization of the second boxes of the transistors of the reading ports of the memory cells 102 of the device 100. The device 100 comprises one or more matrices 134 of memory cells 102 similar to that previously described in connection with Figure 1. In the example of Figure 3, a single matrix 134 of memory cells 102 is shown. In addition, only three columns of memory cells 102 of the matrix 134 are shown. The matrix 134 is electrically coupled to a test circuit 136 of the BIST type, or "built-in-self test", making it possible to test each of the memory cells 102 and to characterize their performances.
    [0018] The test circuit 136 is also coupled to a control circuit 138 which, from the results provided by the test circuit 136, determines the polarization states in which the ground planes of the transistors of the read ports of the cells 102 are intended to be polarized. The test circuit 136 may, for example, make it possible to detect the columns of memory cells leading to read errors (under given read access conditions), and from these results, the control circuit 138 determines which the columns of faulty cells which need to keep a polarization of the second wells of the transistors of the read ports with a sufficiently high potential, for example at VDD, to reduce their access time, the second wells of the transistors of the reading ports other columns can be polarized with a lower potential, for example zero, to minimize their consumption. The control circuit 138 is connected to a memory circuit 140 in which the polarization states of the different columns determined by the control circuit 138 are stored. A selection circuit 142, here formed by several multiplexers 144, comprises control inputs connected to the memory circuit 140. Each multiplexer 144 of the selection circuit 142 has several inputs (four in the example of FIG. 3) on which 10 different Polarization potentials, corresponding to the different possible modes of operation of the cells 102, are applied. The output of each multiplexer is connected to the second wells of the transistors of the read ports of one of the columns (or group of two adjacent columns) of memory cells of the matrix 130.
    [0019] Thus, from the polarization states stored in the memory circuit 140, the circuit 142 applies one of the bias potentials to the second wells of the read port transistors of each of the cell columns 102 of the matrix 134. Polarization potential levels applied to the four inputs of each of the multiplexers 144 correspond, for example, to the potentials corresponding to the four modes of operation previously described. In a variant, the circuit 142 may correspond to a single multiplexer receiving as input the different possible polarization levels of the second wells of the transistors of the read ports of the cells 102 and 25 applying the same bias potential to the second wells of the transistors of the reading ports. cells of all the columns of the matrix 134. Alternatively, it is also possible that the number of bias potentials applied at the input of the circuit 142 is different. For example, it is possible for only two bias potentials to be applied at the input of the circuit 142, one of which may correspond to VDD and the other corresponding to a zero electrical potential. Alternatively, it is also possible that the memory circuit 140 is formed by a portion of the cells 102 of the matrix 134. FIG. 4 schematically represents such a configuration, in which each of the cells 146 of one of the cell lines of the matrix 134 is used to memorize the state of polarization in which the second boxes of the transistors of the read ports of the cells of the column to which said cell of this line belongs are intended to be polarized. The memory point of each of the cells 146 of this line is connected to a control input of a multiplexer 144 which furthermore comprises two other data inputs on which two different levels of bias potentials are applied, for example one corresponds to VDD and the other corresponding to zero potential. The output of each multiplexer 144 is connected to the second boxes of the transistors of the reading ports of the cells of the corresponding column such that one of the two potentials applied at the input of each multiplexer 144 is applied to these second boxes, depending on the value stored in the corresponding memory cell.
    [0020] When the read ports of memory cells of two adjacent columns are arranged next to one another and such that the second wells of the transistors of these read ports are formed by the same portion of semiconductor doped, the two bits stored by the two cells of the line dedicated to the storage of the polarization states of these two columns can be used to control a single multiplexer. In this case, it is possible to use a multiplexer having four inputs so that the second boxes of the transistors of the read ports of each group of two columns can be polarized according to one of four possible different levels of polarization.
    [0021] The line of the memory cells 146 used for storing the state of polarization of the second wells of the transistors of the read ports of the memory cells advantageously corresponds to the line of memory cells which is positioned opposite the input / output circuits. (which include read and write circuits) coupled to the cell array. Memory cells called end of bit line are disposed at the ends of the cell columns of the matrix and can be used to polarize the boxes of the transistors of the matrix of memory cells. Metallic lines aligned in the direction of the columns of the array and each connected to the second wells of the transistors of the read ports of the cells of one of the adjacent columns or group of columns can be used to bias these second wells. The polarization of the first boxes of the other transistors of the cells of the matrix can be carried out globally for the entire matrix.
    [0022] Using cells of the matrix 134 to memorize states in which transistors of the read ports are to be biased has the advantage of being able to dynamically change the state of the read ports, and also to implement very dense way the device 100.
    [0023] In addition, the values stored in the cells can be modified according to the needs of the application. Thus, it is possible for the user to choose directly the desired polarization states without using the test circuit 136 and the control circuit 138. In the previously described embodiments, the transistors 126 and 128 of the read ports of the memory cells 102 are FDSOI transistors of NMOS type. Alternatively, it is possible that these transistors are PMOS type. In this case, the source of transistor 128 of each cell 102 is connected to the power supply potential VDD.
    [0024] In addition, according to another variant embodiment, that the transistors 126 and 128 are of the NMOS or PMOS type, it is possible for the second boxes 133 of these transistors to be formed by P-doped semiconductor portions.
    [0025] Finally, according to another variant, it is possible for the polarization potentials applied at the input of the multiplexers 144 to be different from one column to another or from a group of two columns adjacent to the other. The principles outlined above for 8T memory cells can also be applied to 6T memory cells. FIG. 5 represents an exemplary embodiment of such a memory cell 102 comprising six transistors. As for the memory cell 8T, the memory cell 6T comprises the two NMOS transistors 104, 106 and the two PMOS transistors 108, 110 together forming two inverters mounted head to tail corresponding to the memory point of the cell 102, and connected to the terminal The cell 6T also comprises the two access transistors 116, 118 whose gates are connected to the line 120 serving here as both a write word line and a line of reference. reading word. The drains of the access transistors 116, 118 are connected to the lines 122, 124 serving here as both write bit lines and read bit lines. Transistors corresponding to NMOS transistors, here transistors 104, 106, 116 and 118, are FDSOI transistors comprising the first p-type doped semiconductor casing 125 which forms the ground plane of these transistors. A zero electric potential, for example that of the mass of the device 100, is applied to this first box 125. The transistors corresponding to PMOS transistors, here the transistors 108 and 110, are FDSOI transistors comprising the second box 133 of semi N-type doped driver which forms the ground plane of these transistors. An electric potential VNw is applied to the second housing 302 of the transistors 108, 110, the value of this potential being between 0 and VDDH and fixed according to the desired operating mode of the cell 102, that is to say say the compromise of writing speed / consumption chosen. In FIG. 5, the two wells 125 and 133 of different types are symbolically separated by dashed lines. The column arrangement of the memory cells 102 previously described and allowing column and matrix pooling of the second caissons 133 can also be applied for the memory cells 6T.
    [0026] Alternatively, transistors 116 and 118 may be of the same type as transistors 108 and 110, i.e. PMOS in the previously described example. In this case, the bit lines 122, 124 are pre-charged to a low voltage, for example ground. Alternatively, whether the transistors 116 and 118 are of the same type as that of the transistors 104 and 106 or the transistors 108 and 110, the first well 125 may comprise an N-type doped semiconductor and the second well 133 may have a p-type doped semiconductor
    权利要求:
    Claims (14)
    [0001]
    REVENDICATIONS1. Memory device (100) comprising at least: - a matrix (134) of memory cells (102) of the SRAM type, each memory cell (102) comprising at least four first FDSOI transistors (104, 106, 108, 110) forming two inverters mounted head to tail and two second FDSOI transistors (116, 118) forming at least write access transistors, and wherein: - each memory cell (102) further comprises two third FDSOI transistors (126, 128) forming read access transistors, the first (104, 106, 108, 110) and second (116, 118) FDSOI transistors having a first doped semiconductor well (125) of a first conductivity type and the third FDSOI transistors (126, 128) having a second semiconductor casing (133) doped to a second conductivity type opposite to the first conductivity type, or - the second FDSOI transistors (116, 118) also forming read access transistors d e the memory cell (102), the N-type transistors of the first (104, 106, 108, 110) and second (116, 118) transistors comprising the first box (125) and the P type transistors among the first ( 104, 106, 108, 110) and second (116, 118) transistors comprising the second box (133), - means (136, 138, 140, 142) of polarization of the second boxes (133), able to select a value at least one bias potential of the second wells (133) and to apply said bias potential to the second wells (133).
    [0002]
    Memory device (100) according to claim 1, wherein the memory cells (102) are arranged next to each other forming several columns of memory cells (102), and wherein the second cells (133) memory cells (102) of the same column are formed by the same portion of semiconductor doped according to the second type of conductivity. 5
    [0003]
    The memory device (100) according to claim 2, wherein the third transistors (126, 128) of the memory cells (102) of two adjacent columns or of each group of two adjacent columns are arranged next to each other such that the second wells (133) of the memory cells (102) of the two adjacent columns or of each of the groups of two adjacent columns are formed by the same portion of semiconductor doped according to the second type of conductivity.
    [0004]
    4. Memory device (100) according to one of claims 2 or 3, wherein the biasing means of the second boxes (133) of the memory cells (102) comprise: - a memory circuit (140) capable of storing a state biasing the second wells (133) of the memory cells (102) for each column or group of two adjacent columns; a selection circuit (142) coupled to the memory circuit (140), comprising a plurality of inputs on which different polarization potential values are intended to be applied and adapted to apply on the second cells (133) memory cells (102); of each column or group of two adjacent columns one of said bias potential values selected as a function of the polarization state stored in the memory circuit (140) and associated with said column or said group of two adjacent columns.
    [0005]
    Memory device (100) according to claim 4, wherein the selection circuit (142) comprises a plurality of multiplexers (144) 3025653 27 each having a plurality of inputs on which said bias potential values are intended to be applied and a connected output the second cells (133) of the memory cells (102) of one of the columns or a group of two adjacent columns. 5
    [0006]
    6. memory device (100) according to one of claims 4 or 5, wherein the memory circuit (102) comprises at least one memory cell (146) of each column and is such that each of said memory cells (146) is suitable storing a polarization state of the second cells (133) of the memory cells (102) of the column to which said memory cell (146) belongs, or that two of said memory cells (146) are capable of storing a polarization state of the second cells caissons (133) of the memory cells (102) of a group of two adjacent columns of which said memory cells (146) are part. 15
    [0007]
    7. memory device (100) according to one of claims 4 to 6, wherein the biasing means of the second boxes (133) of the memory cells (102) further comprise: - a test circuit (136) coupled to the matrix (134) of memory cells (102) and adapted to detect whether one or more memory cells (102) have a reading speed generating read errors; a control circuit (138) coupled to the test circuit (136) and the memory circuit (140) and adapted to define the polarization states to be stored in the memory circuit (140) according to results provided by the circuit test (136).
    [0008]
    8. memory device (100) according to one of the preceding claims, wherein the first type of conductivity corresponds to the type P and the second type of conductivity corresponds to the type N. 3025653 28
    [0009]
    9. memory device (100) according to one of the preceding claims, further comprising biasing means of the first boxes (125) memory cells (102) capable of applying a zero bias potential on the first boxes (125). 5
    [0010]
    10. Polarization method of a memory device (100) according to one of the preceding claims, comprising steps of: - selecting a value of at least one polarization potential of the second boxes (133), and 10 - applying said bias potential to the second wells (133).
    [0011]
    The method of claim 10, wherein a value of a supply voltage of the memory cells (102) of the memory device (100) and the value of said at least one bias potential are selected according to a speed. desired reading and power consumption of the memory device (100).
    [0012]
    12. Method according to one of claims 10 or 11, in which: - the memory cells (102) are arranged next to each other forming several columns of memory cells (102), the second boxes (133) memory cells (102) of the same column being formed by one and the same portion of semiconductor doped according to the second type of conductivity, and / or - the third transistors (126, 128) of the memory cells (100) of two adjacent columns or each group of two adjacent columns are arranged next to each other such that the second wells (133) of the memory cells (102) of the two adjacent columns or each of two groups of two adjacent columns are formed by the same portion of semiconductor doped according to the second conductivity type, further comprising a step of storing a state of polarization of the second cells (133) of the memory cells (102) for each e column or group of two adjacent columns, and wherein the selecting step performs a selection of one of different polarization potential values as a function of the polarization state stored in the memory circuit (140) and associated with said column or group of two adjacent columns. 10
    [0013]
    The method of claim 12, further comprising a step of testing the memory cell array (134) (102) for detecting whether one or more memory cells (102) have a read speed generating read errors, and a a step of determining polarization states for storage according to results of the testing step.
    [0014]
    14. Method according to one of claims 10 to 13, wherein the value of the bias potential applied to at least a portion of the second boxes (133) is strictly positive.
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    同族专利:
    公开号 | 公开日
    FR3025653B1|2017-12-22|
    EP3002788A3|2016-06-22|
    US9542996B2|2017-01-10|
    US20160078924A1|2016-03-17|
    EP3002788A2|2016-04-06|
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1458488A|FR3025653B1|2014-09-10|2014-09-10|SRAM MEMORY CELL DEVICE HAVING POLARIZATION MEANS FOR MEMORY CELL READING TRANSISTORS|FR1458488A| FR3025653B1|2014-09-10|2014-09-10|SRAM MEMORY CELL DEVICE HAVING POLARIZATION MEANS FOR MEMORY CELL READING TRANSISTORS|
    US14/850,218| US9542996B2|2014-09-10|2015-09-10|Device with SRAM memory cells including means for polarizing wells of memory cell transistors|
    EP15184711.8A| EP3002788A3|2014-09-10|2015-09-10|Device with sram memory cells comprising means for polarising transistor boxes of memory cells|
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