• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
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  • 优先权
    • 专利摘要:
    The invention relates to a method and an electrical device with superposed layers alternating electrically conductive layers and insulating layers. A structure of the mesa structure type is formed, leaving, for at least one conductive layer, an uncovered peripheral portion accessible for a contact recovery. In this portion, an electrically insulating pattern is configured to define an electrically insulated area located in the peripheral portion of said at least one of the electrically conductive layers. Application to electrical capacitances and redistribution layers for microelectronic devices.
    公开号:FR3022072A1
    申请号:FR1455212
    申请日:2014-06-10
    公开日:2015-12-11
    发明作者:Sylvain Pelloquin；Christel Dieppedale；Rhun Gwenael Le；Henri Sibuet
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] TECHNICAL FIELD OF THE INVENTION The present invention generally relates to the formation of multilayer electrical devices alternating insulating and conductive layers and more particularly but not limited to the production of multilayer capacitors or dense routing structures. One possible application is for devices based on semiconductor materials. For example, it makes it possible to produce an electrostatic device by alternating stacking of conductive and dielectric layers that are advantageously connected with a reduced number of lithographic masks. This type of device is particularly adapted to be realized in microelectronic technology which includes nanotechnologies. The invention provides access to a high surface density of electrical accumulation with low cost manufacturing technology. The invention can also be used to carry out redistributions of power lines by using the superposition property of these lines to benefit from a surface gain and therefore from a cost reduction. STATE OF THE ART The microelectronics industry commonly uses layered metal / insulator / metal (MIM) structures in which electrically insulating and electrically conductive layers are stacked, particularly to form high-value capacitors. at reasonable costs because of the surface saving that the superposition of these layers allows. Structures of this type have already been described, in particular those described in document US Pat. No. 5,745,335. This publication describes a process for manufacturing a capacitive system over a substrate. The fabrication begins with alternating full plate deposition of a plurality of stacks each comprising an electrically conductive layer and an electrically insulating layer. This plurality of deposited layers is then etched so as to define, by each stack, an electrode pattern. It follows the creation of several electrode levels above the face of the substrate on which the deposits were made. In this superposition, the electrode patterns are different so as to allow a resumption of contact, for the connection of the conductive layer of each stack, to an outer element. More precisely, one starts by engraving the stack of higher level, giving it a shape and, therefore, a contour and a determined area. Then, we proceed to successive engravings for the stacks of the lower levels. This fabrication in which the electrodes are progressively formed by stepping downwards towards the surface of the substrate, is also referred to as "top down" (ie, from top to bottom) in the literature. These etchings are configured so that, between two successive levels, the upper stack is of strictly smaller surface area than that of the lower stack and so that the upper stack has a contour contained in the perimeter of the lower stack. . The stacked structure is of increasing section towards the substrate above which it is located and is similar to a structure of the "mesa structure" type. Thus, for each stack, it provides a lateral portion not covered with its conductive layer, which allows access for the resumption of contact. The embodiment proposed by US Pat. No. 5,745,335 thus offers a possibility of resumption of lateral contact of the layers to form the capacitance electrodes. The contact resumptions are produced by contact elements passing through a dielectric layer covering the stacked structure and each having an electrical connection end applied to a conductive layer of a stack (at one edge of the layer). conductor not covered by the layers which surmount it) and an external connection end. This type of stacking structure has interests in terms of manufacturing and formation of contact pickups. However, the successive etchings, at the flanks of each stack composed of a conductive layer and an insulating layer, can create electrically defective areas on the etching flanks. These defective areas cause a decrease in performance and a loss of reliability of the device due in particular to the problems of industrial reproducibility of this method of manufacture. It is therefore an object of the invention to describe a device and a production method that make it possible to respond to this problem, advantageously by using traditional means implemented by the microelectronics industry. Other objects, features and advantages of the present invention will be apparent from the following description and accompanying drawings. It is understood that other benefits may be incorporated.
    [0002] SUMMARY OF THE INVENTION A first aspect of the invention relates to a multilayer electrical device successively comprising, on the surface of a substrate, a first electrically conductive layer and at least one stack comprising an electrically insulating layer followed by a second layer. electrically conductive, the stack being of a strictly smaller surface area than that of the electrically conductive layer which is immediately below it and being contained in the perimeter of said immediately lower electrically conductive layer so as to define, in each electrically conductive layer, an exposed portion covered by no stack, the exposed portion traversing the entire contour of said electrically conductive layer.
    [0003] Advantageously, the electrically conductive layer of at least one stack comprises an electrically insulating pattern configured to define a peripheral electrically insulated area located in the exposed portion of said electrically conductive layer. Thanks to the invention, a peripheral zone of the conductive layer in question is isolated so that it is no longer active. However, this peripheral zone is the locus of potential defects, in particular during etchings enabling, in the deposited layers, defining the edges of the patterns to be formed (for example to define the contour of capacitance electrodes). In particular, in the event that a flank etching would cause a redeposition of conductive material on the sides of an insulating layer, which would cause electrical insulation defects, the electrically insulating pattern can restore the insulation between the different layers and avoids the tip effect at the electrode end in the case of capacitors. This additional pattern, preferably forming a guard ring around each conductive layer, can be achieved independently or be performed simultaneously with the etching of the first conductive layer. Another aspect of the invention relates to a method of manufacturing a multilayer electrical device comprising forming, successively on the surface of a substrate: a first electrically conductive layer; at least one stack; comprising an electrically insulating layer followed by a second electrically conductive layer, the stack being formed with an area smaller than that of the immediately lower electrically conductive layer and contained within the perimeter of said immediately lower electrically conductive layer of so as to define, in each electrically conductive layer, an exposed portion covered by no stack, the exposed portion traversing the entire contour of said electrically conductive layer. Advantageously, it comprises forming, in the electrically conductive layer of at least one stack, an electrically insulating pattern configured to define an electrically insulated peripheral area located in the exposed portion of said electrically conductive layer.
    [0004] BRIEF DESCRIPTION OF THE FIGURES The objects, objects, as well as the features and advantages of the invention will become more apparent from the detailed description of an embodiment of the latter which is illustrated by the following accompanying drawings in which: FIG. 1 illustrates a step of forming a plurality of layers in the embodiment of the invention; FIG. 2 shows a lithography and etching step for the formation of a stack; FIGURES 3 and 4 show successive steps similar to that of FIG. 2; FIGURE 5 shows a lithography and etching of a base electrically conductive layer, forming a first layer on the surface of the substrate; FIGURE 6 illustrates the creation of trenches in the electrically conductive layers; FIG. 7 shows, in plan view, the result obtained after the step of FIG. 6 and removal of the mask of FIG. 6; FIGURE 8 shows the formation of an upper insulating layer and openings in this layer; FIG. 9 shows, following FIG. 8, the creation of the elements of contact recovery through the openings; FIG. 10 is a view from above corresponding to the sectional view of FIG. 9.
    [0005] The drawings are given by way of examples and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily at the scale of practical applications. In particular, the relative thicknesses of the different layers are not necessarily representative of reality. DETAILED DESCRIPTION OF THE INVENTION Before proceeding to a detailed review of embodiments of the invention, are set forth hereinafter purely optional features which may optionally be used in combination in any combination between them or alternatively: the insulating pattern is a trench 14, 24, 34 with a closed contour formed in the entirety of the thickness of said electrically conductive layer 12, 22, 32. - the electrically conductive layer 12, 22, 32 of each stack 10, 20, 30 comprises an electrically insulating pattern configured to define an electrically insulating peripheral area 15, 25, 35 located in the exposed portion 8, 18, 28, 38 of said electrically conductive layer 12, 22, 32. - the device comprises for each electrically conductive layer 12 , 22, 32 comprising an electrically insulating pattern, a contact resumption element 17, 27, 37 in electrical continuity with a zo a connection located in the exposed portion 8, 18, 28, 38 of said electrically conductive layer 12, 22, 32, out of the insulated area 15, 25, 35. - the device comprises an electrically insulating layer 9 covering the entire electrically conductive layers 2, 12, 22, 32 and traversed by the contact resumption elements 17, 27, 37. - The method may be such that the formation of the insulating pattern comprises the formation of a trench 14, 24, 34 closed contour formed in the entirety of the thickness of said electrically conductive layer. the trench 14, 24, 34 is formed by definition masking of a trench pattern followed by etching of a trench 14, 24, 34 outside the mask in said electrically conductive layer. - for the electrically conductive layer 12, 22, 32 of each stack 10, 20, 30, an electrically insulating pattern configured to define an electrically insulated peripheral area 15, 25, 35 in the exposed portion 8, 18, 28 is formed. , 38 of said electrically conductive layer 12, 22, 32. - the trenches 14, 24, 34 of the electrically conductive layers 12, 22, 32 are formed during the same steps of masking and etching. the method comprises, for each electrically conductive layer 12, 22, 32 comprising an electrically insulating pattern, the formation of a contact-resumption element 17, 27, 37 in electrical continuity with a connection zone situated in the exposed portion 8 , 18, 28, 38 of said electrically conductive layer 12, 22, 32, out of the insulated zone 15, 25, 35. - the method comprises the formation of an upper electrically insulating layer 9 covering the entirety of the electrically conductive layers 2, 12, 22, 32 and traversed by the contact resumption elements 7, 17, 27, 37. - the formation of a contact resumption element 7, 17, 27, 37 is operated by etching of patterns of contact recovery elements through the upper electrically insulating layer 9, depositing a layer of an electrically conductive material above the upper electrically insulating layer and in said patterns, and then etching the layer of an electrically conductive material so as to define the contact resumption elements 7, 17, 27, 37. - the etching of the layer of an electrically conductive material is configured to electrically isolate one from the other at minus two contact recovery elements. the formation of the first electrically conductive layer 2 and of the at least one stack 10, 20, 30 comprises: - successive full plate deposits, from the substrate surface 1 of a formation layer of the first layer 2 electrically conductive and as many alternations of electrically conductive layers and insulating layers as stacks 10, 20, 30, - for each stack 10, 20, 30, starting with the stack 10, 20, 30 of highest level above the surface of the substrate 1, definition masking of a pattern of said stack 10, 20, 30 and etching of the layers of the alternation corresponding to said stack 10, 20, 30 outside the mask, said etching being configured to preserve the stack 10, 20, 30 immediately below said stack 10, 20, 30 or the formation layer of the first electrically conductive layer 2, after the formation of all the stacks 10, 20, 30, a mask of defined a pattern of the first electrically conductive layer 2 and an etching of the forming layer of the first electrically conductive layer outside the masking 4, the definition masking of a pattern of the first electrically conductive layer 2 is carried out; and the definition masking of the trench patterns 14, 24, 34 during the same step, and the etching of the formation layer of the first electrically conductive layer and the etching of the trenches 14, 24, 34 during a single step. step.
    [0006] It is specified that in the context of the present invention, the terms "on" or "above" do not necessarily mean "in contact with". For example, intermediate layers or intermediate members may be present. In general terms, height is understood to mean a dimension located according to the thickness of the substrate 1. The substrate 1 generally comprises two opposite faces around its thickness, one of the faces being used for carrying out the invention.
    [0007] This face is advantageously flat, in a plane advantageously perpendicular to the thickness of the substrate. The substrate 1 may be solid or multilayer and in different materials such as conducting materials, insulators or semiconductors, for example silicon. The substrate 1 may itself have several layers. For example, the substrate 1 may comprise a dielectric surface layer above which the succession of layers of the invention is carried out. The substrate 1 may also possibly incorporate members such as active or passive electrical elements. The substrate 1 is generally the support portion used during the manufacturing steps of the device and at least a part of which is advantageously retained at the end of manufacture to participate in said device. It can be made or based on monocrystalline silicon and be in the form of thin slice generally qualified by the term "wafer". By electrically conductive means a conductivity material for performing a conduction function of electricity in its application. An electrically insulating material is a material whose electrical resistivity allows it, in its application, to serve as a barrier to the conduction of electricity. The dielectric term is here used in the same sense. The term "pattern" refers to all geometrical configurations for which a reentrant shape is made hollow in the thickness of at least one layer of material.
    [0008] This pattern can be manufactured by a recess, by engraving in particular. The pattern may also be filled, for example with an electrically insulating material. Known techniques of growth, deposition and etching of these materials and all those, conductors or insulators, used in microelectronics are possibly used from substrates most often. The definition of the motifs is done in particular by photolithography from masks, photosensitive resins and by their insolation but also possibly by other means. Typically, it is possible to use specific chemical etchings of each material, for example by a neutral plasma or also with a reactive plasma etching which is formed in an etching reactor where the devices to be etched are exposed to it. In the case of the use of a reactive plasma to make the isolation trenches 14, 24, 34, the insulating layer of each stack can serve as a stop for etching the conductive layer of said stack. It will be noted here that the successive deposits of conductive and insulating materials are preferably adapted to be consistent, that is to say that they make it possible to obtain substantially equal deposition thicknesses over the entire layer in question. The layers formed may themselves consist of one or more sub-layers. The conductive materials that can constitute the conductive layers include in particular the metals or their alloys used in microelectronics: aluminum (Al), gold (Au), copper (Cu), platinum (Pt) and possibly all kinds of metals. naturally conducting or conductive materials, in particular doping materials such as semiconductor materials and in particular doped silicon, or conductive oxides. The deposition of these materials can be done, depending on the material, using one or other of the techniques commonly used by the microelectronics industry and which are most often designated by the terms: PVD, CVD, PECVD and ALD, ECD, acronyms corresponding respectively to "physical vapor deposition", "chemical vapor deposition", "plasma-enhanced chemical vapor deposition", "atomic layer deposition", that is to say "Physical vapor deposition", "chemical vapor deposition", "plasma-assisted chemical vapor deposition", "atomic layer deposition", "electrochemical deposition". Deposition can also be done by "spin coating" that is to say by centrifugation of the deposited material in liquid or viscous form on the surface of the substrate. The deposited thicknesses are typically in a range of values from 10 nm (i.e., 10.10-9 meter) to 2 μm.
    [0009] The materials that can be used to form all or some of the dielectric elements of the invention are, for example, silicon (Si) and its oxide (SiO 2) or nitride (SiN) which are insulators. Other examples are given below: alumina (Al 2 O 3), hafnium oxide (HfO 2), ceramics such as lead titan zirconate (PZT) or titanates of barium and strontium (BST) . They are for example deposited with the same methods as those mentioned above or by PLD, acronym for the English term "pulsed laser deposition", that is to say "pulsed laser ablation deposition". The deposited thicknesses are typically in a range of values from 10 nm (i.e., 10.10-9 meter) to 2 μm. By way of additional example, the insulating layers may be formed by deposits or chemical treatments and in particular oxidation or nitriding. Thus, the deposition phases may for example be limited to the creation of the conductive layers, then between each deposit a portion of their thickness is treated to create insulating layers. According to the invention, a succession of insulating layers and conductive layers is created. It will be described later in detail how this succession preserves in at least one conductive layer a portion not covered by other layers of the succession, in particular by layers which surmount it, in particular upper conductive layers. This portion not covered by other layers is still here called exposed portion. In the invention, the exposed portion advantageously traverses the entire contour of the layer which comprises it, so that, in the case described with reference to the figures, a peripheral portion of the layer, this portion device being exposed, ie not covered by stacks that eventually overcome it. The term "exposed" does not necessarily mean that the portion in question is, in the end, not covered. This may in particular be the case at least partially with an insulating blanket layer. The term "exposed" is therefore understood only in a manner relating to the stacks of the invention.
    [0010] FIGS. 1 to 5 show a first phase of the method of the invention, making it possible to obtain a mesa structure on the surface of the substrate 1. FIG. 1 starts by depositing a succession of layers from a face of the substrate 1. This succession of layers is preferably obtained by a full-plate deposition technique, for example by following the deposition technologies described above. The succession of layers comprises firstly a first electrically conductive layer 2. In the case of capacitance, this layer 2 is able to form a lower electrode. Above the first layer 2, one or more stacks are created. In the example of the figures, 3 stacks are formed successively 10, 20, 30 above the first layer 2. Each stack 10, 20, 30 comprises at least one electrically insulating layer 11, 21, 31 serving to isolate two layers drivers who follow each other. For both the conductive layers and the insulating layers, examples of usable materials have been given above.
    [0011] The step of FIG. 2 reveals an embodiment for defining the final configuration of the stacks, starting with the top level stack marked 30. This step, for example, produces an upper electrode from the stack 30 in FIGS. the case of an ability. A mask 3 is used to define an etching pattern, and more particularly, to define a surface portion of the stack 30 which will not be eliminated by etching. Conventional photolithography techniques can be used. The etching implemented is configured to preserve (at least partially) the electrically conductive layer 22 located under the stack 30. In particular, the etching kinetics can be adapted for this purpose.
    [0012] The result of FIG. 2 is a top stack whose contour is defined by a flank 33.
    [0013] The following steps of FIGS. 3 and 4 are relatively similar to that of FIG. 2. Thus, in FIG. 3, the contour of the second stack 20 is created by etching outside an area covered by a mask 4 whose shape delimits the flank 23 of the stack 20. Similarly, FIG. 4 shows a creation of the stack 10, here a lower stack, by means of etching outside an area defined by a mask 5. The definition technique masks 3, 4, 5 may be identical. As for the case of the etching of the stack 30, it is arranged to preserve the next electrically conductive layer (12 and 2) during the etching of the stacks 20 and 10.
    [0014] Finally, in FIG. 5, the definition of the multilayer system is finalized by a delimitation of the first electrically conductive layer 2. In summary, in the example shown, full-plate deposits followed by lithography, and engravings of similar designs may be sufficient to the creation of this structure. This structure is also of geometric configuration adapted to a contact recovery at a lateral projection of each electrically conductive layer. The masks 3, 4, 5 and 6 are configured, and thus the outline of the layers 2, 12, 22 and 32 so as to preserve, for each of these layers 2, 12, 22, 32, a zone whose surface n is not covered by the rest of the structure. This zone constitutes a peripheral portion 8, 18, 28 of the layers situated under the stack 30, itself easily accessible by its upper surface 38. In order to preserve the peripheral portions 8, 18, 28, it is ensured that, at each succession lithography and etching stages, down to the face of the substrate, the stack 10, 20, 30 created so that its area is smaller than that of the lower stack and its contour is contained in that of the lower stack. This precaution is also taken for the contour and the area of the first conductive layer 2 relative to the first stack 10. Thus, it preserves a peripheral exposed portion 8, 18, 28 not covered. By way of illustration, an area of the layer 22 of the second stack 20 which is covered by the remainder of the device has been identified. The zone 29 and the peripheral portion 28 complement each other to form the entire layer 22. The multilayer structure thus produced can be of various shapes. The top view of Figure 7 shows an example. It also reveals the sectional narrowing to which the conductive layers 2, 12, 22, 32 are alternately alternating with the insulating layers 11, 21, 31. In FIG. 7, the peripheral portion 8 of the first layer 2 presents itself. in the form of a lateral projection along the plane of the substrate face 1. The contour of the remainder of the first layer 2 is here substantially rectangular. The contour of the layer 12, and the rest of the stack 10, is also substantially rectangular. The contour of the layer 22, and of the remainder of the stack 20, is inscribed inside the preceding contour with a part recessed along the plane of the substrate face, to reveal the portion 18 of the layer 12 Finally, the contour of the layer 32, and of the remainder of the stack 30, fits into that of the stack 20, with a withdrawal along the plane of the face of the substrate 1 to reveal the portion 28 of the layer 22. As a preference, the peripheral exposed portion 8, 18, 28 not covered with each intermediate conductive layer 2, 12, 22 is continuous along the contour of the layer in question. Thus, the peripheral portion forms a closed loop surface at the periphery of the layer. Contour definitions, in particular with engravings, are implemented by the invention, so as to delimit the shape of the different layers. Engravings at the flanks 13, 23, 33 can create defects for the end device, and produce electrical problems and / or performance declines. To remedy this, Figure 6 illustrates the formation of reasons for the electrical insulation of the portion of the conductive layers 12, 22, 32 may be impacted by the defect. More specifically, the peripheral portion of each (or at least one) conductive layer 12, 22, 32 of the stacks 10, 20, 30 has a pattern configured to distinguish an insulated area 15, 25, 35 from the rest of the conductive layer. 12, 22, 32. The pattern advantageously comprises a trench 14, 24, 34 making recess over the entire thickness of the conductive layer where it is formed. The space thus created is electrically insulated. It may further be filled with a dielectric material. The insulation pattern is located in the exposed (uncovered) portion 18, 28, 38 of the conductive layer 12, 22, 322. For the layer 32, the exposed portion 38 may in practice cover the entire surface of the layer 32, if this layer is not surmounted by another conductive layer. The pattern also follows the entire contour of the layer 12, 22, 32 where it is formed so as to completely separate the insulated zone 15, 25, 35. The zone 15, 25, 35 forms the periphery or the contour outside the conductive layer considered. It forms a ring-like closed contour surround around the remainder of the conductive layer 12, 22, 32. The trench 14, 24, 34 of the layers 12, 22, 32 can be made during a step of etching after making a mask 6 for defining the trench patterns by photolithography in particular. It is possible to use the mask 6 of the etching step of the first layer 2 or to form two successive masks and to engrave successively. The trench and the isolated area can have a width of 0.5 to 5pm respectively. The result obtained is a definition of an active (ie electrically efficient) part in the conductive layers 12, 22, 32 having eliminated an isolated zone 15, 25, 35 bordered by the flanks 13, 23, 33 stacks. At the same time, in the exposed peripheral portion 8, 18, 28, 38 conductive layers are preserved an area belonging to the active part of the layer and at the same time not covered, for the resumption of contact. These contact resumptions can be produced after deposition of an upper insulating layer 9 and the creation of openings in this layer 9 (for example by photolithography and etching), as can be seen in FIG. 8. Advantageously, the layer 9 also fills the trenches 14, 24, 34. Contact resurfacing elements 7, 17, 27, 37 may then be formed. In particular, a conductive material is deposited on the layer 9 and in the openings, for example a connecting metal such as titanium, nickel, gold or aluminum, with a thickness indicative of 0.5 to 2 μm. This layer is then etched to obtain the contact-resumption elements 7, 17, 27, 37. Some of them can be connected or in one piece from the deposited connection layer, to form interconnections (for example). example those identified 16 and 26 in Figure 10) between the conductive layers. Thus, FIG. 10 shows a capacitance by MIM stacking with connection of the electrodes corresponding to layers 2 and 22 on the one hand, and electrodes corresponding to layers 12 and 32 on the other hand. The method of the invention therefore allows individual contact recoveries on each of the conductive layers. Any possible electrical configuration of the individual capacitors can thus potentially be realized and in particular the paralleling of the latter in order to obtain the maximum capacity for a given occupied surface. In addition to the routing applications described in the introduction, the multilayer structures according to the invention can advantageously be used in the form of capacitances, particularly of high density, as energy accumulators or filter elements in many electronic products such as integrated power supplies, signal amplifiers, radio frequency (RF) circuit filters. and for all kinds of domestic applications, or the automotive and telecommunications industries where miniaturization brings reliability benefits and cost reduction. The devices that can be formed can be part of systems of the type micro-electro-mechanical systems called MEMS. This type of device can be found in household, automotive, telecommunication or other products where miniaturization brings reliability and cost reduction advantages. The present invention is not limited to the embodiments previously described but extends to any embodiment covered by the claims.
    权利要求:
    Claims (16)
    [0001]
    CLAIMS1 multilayer electrical device comprising successively on the surface of a substrate (1): - a first layer (2) electrically conductive, - at least one stack (10, 20, 30) comprising an electrically insulating layer (11, 21, 31) followed by a second electrically conductive layer (12, 22, 32), the stack (10, 20, 30) being of a strictly smaller area than that of the electrically conductive layer which is immediately below it and being contained in the perimeter of said immediately lower electrically conductive layer so as to define, in each electrically conductive layer, an exposed portion (8, 18, 28, 38) covered by no stack (10, 20, 30), the exposed portion scanning the entire contour of said electrically conductive layer, characterized in that the electrically conductive layer (12, 22, 32) of at least one stack (10, 20, 30) comprises an electrically insulating pattern configured to define an electrically insulating peripheral area (15, 25, 35) in the exposed portion (8, 18, 28, 38) of said electrically conductive layer.
    [0002]
    2. Device according to claim 1 wherein the insulating pattern is a trench (14, 24, 34) closed contour formed in the entirety of the thickness of said electrically conductive layer (12, 22, 32).
    [0003]
    3. Device according to one of the preceding claims wherein the electrically conductive layer (12, 22, 32) of each stack (10, 20, 30) comprises an electrically insulating pattern configured to define an electrically insulated area (15, 25, 35) located in the exposed portion (8, 18, 28, 38) of said electrically conductive layer (12, 22, 32).
    [0004]
    4. Device according to one of the preceding claims comprising, for each electrically conductive layer (12, 22, 32) comprising an electrically insulating pattern, a contact resumption element (17, 27, 37) in electrical continuity with a zone of connection located in the exposed portion (8, 18, 28, 38) of said electrically conductive layer (12, 22, 32), out of the isolated area (15, 25, 35).
    [0005]
    5. Device according to the preceding claim comprising an electrically insulating layer (9) covering all of the electrically conductive layers (2, 12, 22, 32) and through which the contact resumption elements (17, 27, 37).
    [0006]
    A method of manufacturing a multilayer electrical device comprising forming, successively at the surface of a substrate (1): a first electrically conductive layer (2), at least one stack (10, 20, 30) comprising an electrically insulating layer (11, 21, 31) followed by a second electrically conductive layer (12, 22, 32), the stack (10, 20, 30) being formed with a smaller area than that of the electrically conductive layer which is immediately below it and being contained in the perimeter of said immediately lower electrically conductive layer so as to define, in each electrically conductive layer, an exposed portion (8, 18, 28, 38) covered by no stack (10, 20, 30), the exposed portion (8, 18, 28, 38) traversing the entire contour of said electrically conductive layer, characterized in that it comprises the formation, in the electric layer, a conductor of at least one stack (10, 20, 30) of an electrically insulative pattern configured to define an electrically insulating peripheral area (15, 25, 35) in the exposed portion (8, 18, 28, 38). ) of said electrically conductive layer.
    [0007]
    The method of the preceding claim, wherein forming the insulating pattern comprises forming a closed contour trench (14, 24, 34) formed in the entire thickness of said electrically conductive layer.
    [0008]
    8. Method according to the preceding claim wherein the trench (14, 24, 34) is formed by defining masking a trench pattern followed by etching a trench (14, 24, 34) outside the mask in said electrically conductive layer.
    [0009]
    9. Method according to one of the three preceding claims wherein is formed, for the electrically conductive layer (12, 22, 32) of each stack (10, 20, 30), an electrically insulating pattern configured to define an electrically insulated area. peripheral (15, 25, 35) located in the exposed portion (8, 18, 28, 38) of said electrically conductive layer (12, 22, 32).
    [0010]
    10. The method according to the preceding two claims in combination wherein the trenches (14, 24, 34) of the electrically conductive layers (12, 22, 32) are formed during the same steps of masking and etching.
    [0011]
    11. Method according to one of claims 6 to 10 comprising, for each electrically conductive layer (12, 22, 32) comprising an electrically insulating pattern, the formation of a contact resumption element (17, 27, 37) in electrical continuity with a connection area located in the exposed portion (8, 18, 28, 38) of said electrically conductive layer (12, 22, 32) out of the insulated area (15, 25, 35).
    [0012]
    12. Method according to the preceding claim comprising the formation of an upper electrically insulating layer (9) covering all of the electrically conductive layers (2, 12, 22, 32) and through which the contact resumption elements (7, 17) pass. , 27, 37).
    [0013]
    13. Method according to the preceding claim wherein the formation of a contact recovery element (7, 17, 27, 37) is operated by etching patterns of contact recovery elements through the upper electrically insulating layer. (9), depositing a layer of an electrically conductive material above the upper electrically insulating layer and in said patterns, and then etching the layer of an electrically conductive material so as to define the recovery elements. contact (7, 17, 27, 37).
    [0014]
    14. Method according to the preceding claim wherein the etching of the layer of an electrically conductive material is configured to electrically isolate from each other at least two contact recovery elements.
    [0015]
    15. Method according to one of claims 6 to 14, wherein the formation of the first layer (2) electrically conductive and the at least one stack (10, 20, 30) comprises: - successive full plate deposits, from of the substrate surface (1), a formation layer of the first electrically conductive layer (2) and as many alternations of insulating layers and electrically conductive layers as of stacks (10, 20, 30). for each stack (10, 20, 30), starting with the stack (10, 20, 30) of the highest level above the surface of the substrate (1), defining masking of a pattern said stack (10, 20, 30) and an etching of the alternating layers corresponding to said stack (10, 20, 30) outside the mask, said etching being configured to preserve the stack (10, 20, 30) immediately less than said stack (10, 20, 30) or the forming layer of the first electrically conductive layer (2) after the formation of all the stacks (10, 20, 30), a definition masking of a pattern of the first electrically conductive layer (2) and an etching of the forming layer of the first electrically conductive layer, outside masking (3).
    [0016]
    16. Method according to the preceding claim in combination with claim 10, wherein the definition of masking a pattern of the first electrically conductive layer (2) is performed and the definition masking of the trench patterns (14, 24, 34). during a same step, and the etching of the formation layer of the first electrically conductive layer and the etching of the trenches (14, 24, 34) in the same step.
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    同族专利:
    公开号 | 公开日
    US9620581B2|2017-04-11|
    EP2963695A3|2016-06-29|
    FR3022072B1|2017-08-25|
    US20150357401A1|2015-12-10|
    EP2963695A2|2016-01-06|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20040152258A1|2002-11-27|2004-08-05|Masahiro Kiyotoshi|Semiconductor device and method of manufacturing the same|
    US5745335A|1996-06-27|1998-04-28|Gennum Corporation|Multi-layer film capacitor structures and method|
    US6411494B1|2000-04-06|2002-06-25|Gennum Corporation|Distributed capacitor|
    US8680649B2|2008-08-22|2014-03-25|Stmicroelectronics Sas|Multi-layer film capacitor with tapered film sidewalls|
    CN102148261B|2010-02-10|2013-01-23|中国科学院微电子研究所|Manufacturing method of capacitor structure|US10332957B2|2016-06-30|2019-06-25|International Business Machines Corporation|Stacked capacitor with symmetric leakage and break-down behaviors|
    JP6737118B2|2016-10-11|2020-08-05|Tdk株式会社|Thin film capacitors|
    JP6805702B2|2016-10-11|2020-12-23|Tdk株式会社|Thin film capacitor|
    JP2018063989A|2016-10-11|2018-04-19|Tdk株式会社|Thin film capacitor|
    法律状态:
    2015-06-25| PLFP| Fee payment|Year of fee payment: 2 |
    2015-12-11| PLSC| Search report ready|Effective date: 20151211 |
    2016-06-29| PLFP| Fee payment|Year of fee payment: 3 |
    2017-06-27| PLFP| Fee payment|Year of fee payment: 4 |
    2018-06-27| PLFP| Fee payment|Year of fee payment: 5 |
    2020-06-30| PLFP| Fee payment|Year of fee payment: 7 |
    2021-06-30| PLFP| Fee payment|Year of fee payment: 8 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1455212A|FR3022072B1|2014-06-10|2014-06-10|MULTILAYER ELECTRICAL DEVICE|FR1455212A| FR3022072B1|2014-06-10|2014-06-10|MULTILAYER ELECTRICAL DEVICE|
    EP15171014.2A| EP2963695A3|2014-06-10|2015-06-08|Multi-layer electric device|
    US14/735,584| US9620581B2|2014-06-10|2015-06-10|Multilayer electrical device|
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