• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Integrated circuit comprising a substrate (1) and at least one component (TR) disposed at least partially within an active region (10) of the substrate (1) bounded by an insulating region (2). This circuit further comprises a capacitive structure (STC) having a first electrode intended to be connected to a first potential (GND), a second electrode intended to be connected to a second potential (Vdd), one of the two electrodes being located at least partly in the insulating region (2); the capacitive structure (STC) is thus configured to also allow a reduction of compressive stresses in said active region.
    公开号:FR3021457A1
    申请号:FR1454552
    申请日:2014-05-21
    公开日:2015-11-27
    发明作者:Syvie Wuidart；Christian Rivero；Guilhem Bouton；Pascal Fornara
    申请人:STMicroelectronics Rousset SAS；
    IPC主号:
    专利说明:

    [0001] Component, for example NMOS transistor, with active region with relaxed compressive stresses, and associated decoupling capacitor The invention relates to integrated circuits, and more particularly to the relaxation of the compressive stresses of an active region, for example that of a NMOS transistor, as well as the generation of embedded decoupling capacitors, that is to say carried out in conjunction with other components of the integrated circuit and on the same chip. In an integrated circuit, the transistors are made in and on a semiconductive active region, for example silicon, surrounded by an electrically insulating region, for example a trench filled for example with silicon dioxide.
    [0002] The fact of making a MOS transistor inside an insulating region leads by nature to obtaining an active region constrained in compression due to the presence at its periphery of the insulating region. And if an active region constrained in compression favors the performance of a PMOS transistor, it causes a degradation of the performance of an NMOS transistor, in particular in terms of carrier mobility. Furthermore, the production of fast transistors imposes small lengths and channel widths and the structures generally produced have a high density, which leads to very small or even minimal active region dimensions for the considered technology. It is therefore extremely difficult, if not impossible, to increase the dimensions of the active regions of the NMOS transistors in order to relax their compression stresses, given the desired density of the structures produced. On the other hand, in an integrated circuit, decoupling capacitors are strongly recommended because they act as a local reservoir of charges, which reduces internal noise and electromagnetic emissions. Usually, these capacitors are designed to be arranged in a "white space" of the integrated circuit, that is to say areas not occupied by elements of the circuit, available on the chip. However, this requires specific designer work, and most of the time, only a small portion of the white space is used. According to one embodiment, it is proposed to reduce as much as possible the compressive stresses in the active region of a component that is unfavorably sensitive to compressive stresses, for example an NMOS transistor, or an active resistance that is to say formed. in an active region whose resistive value can vary with the compressive stresses, without modifying the characteristics of the PMOS transistors, while allowing an embodiment of an on-board decoupling capacitor which is transparent to the designer of the integrated circuit. In one aspect, there is provided an integrated circuit comprising a substrate and at least one component disposed at least partially within an active region of the substrate bounded by an insulating region. According to a general characteristic of this aspect, the integrated circuit further comprises a capacitive structure having a first electrode intended to be connected to a first potential, for example ground, a second electrode intended to be connected to a second potential, for example a supply voltage of the integrated circuit, one of the two electrodes being located at least partly in the insulating region, that is to say at least partially surrounded by a portion of the insulating region; the capacitive structure is thus configured to allow a reduction of compressive stresses in said active region. The active region of the substrate in which said component is disposed is an active region constrained in compression due to the presence of the insulating region. Indeed, generally, the material forming the insulating region, for example silicon dioxide, has a coefficient of thermal expansion much lower than that of the material forming the active region, typically silicon.
    [0003] Therefore, at the end of the transistor manufacturing process, the insulating region is constrained in compression, thereby inducing compressive stresses in the active region. Since at least one of the electrodes of the capacitive structure is located at least partly in the insulating region, the capacitive structure used here therefore has a dual function, namely a capacitor function for producing in particular a decoupling capacitor, but also a capacitor. compressive stress reduction function in said active region, which in particular improves the mobility of the carriers of an NMOS transistor. Moreover, since at least one of the electrodes of the capacitive structure is located at least partly in the insulating region, its realization, and therefore the realization of the capacitive structure, is completely transparent to the integrated circuit designer since this last simply determines the dimensions of the active region and the insulating region without taking care of the contents of this insulating region and possibly the contents of the volume above this insulating region. According to one embodiment, the other electrode may be formed by a portion of the substrate or be contained in the volume located above the insulating region. The component may advantageously be a component that is unfavorably sensitive to compressive stresses. A component that is unfavorably sensitive to compressive stresses is in particular a component in which at least one of its characteristics is modified in the presence of compressive stresses leading to a degradation of its performance, as is the case, for example, for the mobility characteristic of an NMOS transistor.
    [0004] The component that is unfavorably sensitive to the compressive stresses of its active region may be an NMOS transistor or an active resistance that is formed in said active region, without these two examples being limiting.
    [0005] Generally, an integrated circuit further comprises an additional insulating region disposed above the component, the active region and the insulating region. According to a variant, the first electrode comprises a first region formed by a portion of the substrate and locally separating said insulating region into two insulating domains and the second electrode comprises a second electrically conductive region, for example comprising polysilicon, located in the additional insulating region. above said separation region, the two electrodes being separated by a layer of a dielectric material, for example silicon dioxide. Thus, according to this variant, there is provided within the insulating region a separation wall formed by a portion of the substrate whose purpose is to absorb a portion of the stresses generated by the insulating region. Moreover, since this wall, mechanically active, is made within the insulating region, its realization is completely transparent to the designer of the integrated circuit since the latter simply determines the dimensions of the active region and the insulating region without worrying about the content of this insulating region, that is to say in this case the presence of a wall in this insulating region. And, the definition of the location of this wall is advantageously performed directly and automatically during the Boolean generation of the different levels used for the manufacture of the active region mask without intervention of the designer and without this separation wall interferes with the transistor by example. Moreover, since the second electrically conductive region is located above the separation region, and therefore in the volume located above this insulating region, its realization is again completely transparent to the designer of the integrated circuit since this It is not concerned with the contents of the volume immediately above the insulating region. And, when this second electrically conductive region comprises polysilicon, the definition of the location of this second region can be advantageously performed directly and automatically at the level of the generation of the "polysilicon" mask or "poly" mask, that is to say say the mask used for the definition of the gate regions including transistors, without intervention of the designer and without this second region interferes with the transistor for example. According to one embodiment, said separation region has an upper face situated substantially at the same level as said upper face of the active region and opens into a lower region of the substrate.
    [0006] In other words, the depth of this separation wall is substantially equal to the depth of the insulating region. In order to allow a more effective release of the compressive stresses in the active region, the insulating region located closest to said active region has a volume less than or equal to that of the insulating domain furthest from the active region. When the integrated circuit comprises an additional insulating region comprising a lower insulating layer (CESL layer for example) in compression arranged above the component, the active region and the insulating region, this lower insulating layer in compression above the transistor and the insulating region also contributes to the presence of compressive stresses in the active region. Also a release of compressive stresses in said active region can be obtained by the second region (second electrode) which forms an outgrowth disposed above the first electrode (the partition wall) and below said lower insulating layer. compression. In other words, this protrusion locally raises said lower insulating layer in compression, which thus allows a relaxation of compressive stresses in said active region.
    [0007] When the component is an NMOS transistor, said protuberance advantageously has a structure similar to that of the gate region of the transistor. For example, the supply voltage can be applied to this second electrode via a contact that contacts the upper part of this second electrically conductive region, for example made of polysilicon. The first electrode, i.e. the separation region, can then be connected to ground.
    [0008] According to another variant, the substrate forms the first electrode and the second electrode comprises an electrically conductive trench located at least in the insulating region and containing an internal domain configured to allow compression stress reduction in said active region, the second electrode being separated from the first electrode by a dielectric material. Thus, the compressive stresses (releasing these compressive stresses) are reduced in the active zone by reducing the compressive stresses in the insulating region by the presence of said electrically conductive trench. Moreover, since this trench is made within the insulating region, its realization is again completely transparent to the designer of the integrated circuit since the latter simply determines the dimensions of the active region and the insulating region without worrying about the content of the this insulating region, that is to say in this case the presence of an electrically conductive trench in this insulating region. This trench is mechanically active to allow reduction of the compressive and electrically active stresses, since it is connected to the second potential, for example the supply voltage. Said trench is advantageously distinct from a part of the substrate. According to a possible embodiment, the internal domain may contain polycrystalline silicon or polysilicon. Indeed, such a material, obtained after recrystallization of deposited amorphous silicon, is a material in tension which further facilitates the reduction of compression stresses in the insulating region and therefore in the active region. Moreover, such an embodiment has a thermomechanical advantage. Indeed, silicon and polysilicon have identical coefficients of thermal expansion and this results in fewer stresses in the active region when the temperature undergoes changes related to the environment of the product incorporating the integrated circuit. While the trench may be located only within the insulating region, it may, according to one embodiment, have an upper portion located in the insulating region and extended by a lower portion in the substrate and separated from the substrate by a layer dielectric material, said trench internal domain configured to allow a reduction of compressive stresses in said active region then being located in the upper part and in the lower part. With such an embodiment, a greater reduction of the compressive stresses is obtained. According to one embodiment, the integrated circuit may comprise a memory device comprising a memory plane having nonvolatile memory cells and buried gate selection transistors, and a control block of the memory array including in particular transistors. NMOS forming said components adversely sensitive to compressive stresses; said at least one electrically active trench is then located in at least the insulating region limiting the active region of at least one of these NMOS transistors of the control block and at a depth substantially equal to that of the buried grids. Other advantages and characteristics of the invention will appear on examining the detailed description of embodiments, in no way limiting, and the accompanying drawings in which: FIG. 1 diagrammatically illustrates a NMOS transistor of the prior art; FIG. 2 illustrates an embodiment of an integrated circuit according to the invention; FIG. 3 schematically illustrates an embodiment of an insulating region according to the prior art; FIG. 4 illustrates an implementation mode of FIG. a method of producing an insulating region according to the invention, and - Figures 5 to 16 schematically illustrate various embodiments of the invention.
    [0009] In FIG. 1, the reference TRN designates an NMOS transistor whose active region 10 lies within a semiconductor substrate 1, for example made of p-doped silicon. The active region is surrounded by an insulating region 2, for example shallow trench type (STI: "Shallow Trench Isolation").
    [0010] The transistor TRN, forming part of an integrated circuit CI, conventionally comprises a gate region 3 separated from the active region 10 by a gate dielectric OX, for example silicon dioxide. Moreover, the gate region 3, the active region 10 and the insulating region 2 are covered by the gate dielectric layer OX and by an additional insulating region 4 conventionally comprising an insulating lower layer 40, for example made of silicon nitride, The additional insulating region 4 also comprises at least one other layer above the layer 40, for example at least one layer 42 of carbon dioxide, which is also known to the skilled person by the acronym CESL (Contact Etch Stop Layer). silicon. For purposes of simplification of the figure, the source and drain regions located in the active region and N-doped are not shown.
    [0011] The transistor TRN is produced here in a 90 nanometer technology and the distance D between the gate region 3 and the insulating region 2, that is to say the length of the source or drain region, is here equal to 0 , 23 micrometer due to the presence of a contact on this source or drain region.
    [0012] When the component is a capacitor, this region 3 forms an electrode of the capacitor and the distance D can be reduced to 0.15 micrometer in the absence of said contact. The insulating region 2 is generally made of silicon dioxide. Given the fact that the coefficient of thermal expansion of the active region 10 is greater than the coefficient of thermal expansion of the insulating region 2, at the end of the manufacturing process and especially during cooling, the silicon dioxide 2 goes less than the silicon 10 of the active region leading to an insulating region 2 in compression and therefore inducing compressive stresses in the active region 10. With respect to the transistor TRN of FIG. 1, the transistor TRN according to the embodiment illustrated in FIG. 2, comprises, within the insulating region 2, a separation region 11 formed by a portion of the substrate 1, and separating the insulating region 2 into two insulating domains 20 and 21. The separation region is also covered by the OX gate dielectric layer. Moreover, the upper face of the separation wall 11 is located substantially at the same level as the upper face of the active region 10 and this partition wall opens into the lower part of the substrate 1. The width LG1 of the separation region 11 is here equal to the critical dimension CD (Critical Dimension) of the technology in question, in this case 0.11 micrometers. This critical dimension is the minimum dimension of an active region line. The width LG2 of the insulating domain 20 is here equal to the minimum spacing between two active regions defined by the Design Rules Manual (DRM) of the technology in question, in this case 0.14 micrometer for a 90 nanometer technology. This separation region absorbs the stresses produced by the insulating domain 21 and, as a result, the stresses in the active region 10 result essentially only from the insulating region 20 which has a reduced volume relative to the total volume of the insulating region 2 in the configuration of the prior art illustrated in FIG. 1. The presence of such a separation region already makes it possible to obtain a mobility gain of 20% compared to a conventional TRN transistor of the prior art as illustrated in Figure 1.
    [0013] The separation region 11 forms a first electrode of a capacitive structure STC. The second electrode of this capacitive structure here comprises a second region or protrusion 12 having a central portion 120 electrically conductive, for example polysilicon, separated from the first electrode 11 by the gate dielectric layer OX. As illustrated in FIG. 2, when the component TRN is an NMOS transistor, the protrusion 12 advantageously has a structure similar to that of the gate region 3 of the transistor. In 90 nanometer technology for example, the minimum width of the central portion of an outgrowth 12 is equal to 0.1 micrometer. When the lower insulating layer 40 is a compression-stressed layer, the protrusion 12 contributes to releasing the stresses in the active region 10 of the TRN transistor because this protrusion locally lifts the lower insulating layer 40. While the first electrode (separation region 11) is for example connected to the ground, for example by means of a lateral contact region not shown in FIG. 2, the second electrode, in this case the central portion 120 of the protrusion 12, is example connected to the supply voltage Vdd. This connection to the potential Vdd can be obtained in a simple manner, as illustrated in FIG. 2, by a metal contact 9, for example made of tungsten, coming to contact the apex of the central portion 120 of the protrusion 12. FIG. 3 schematically illustrates the embodiment of the insulating region 2 delimiting the active zone 10 of the transistor TRN of FIG.
    [0014] Is deposited on the substrate 1 a bilayer 70 (silicon oxide / silicon nitride) surmounted by a layer of photoresist 71 that is insulated through an MSK mask called "active mask" or "active region mask Which will make it possible to determine the contours of the insulating region 2 and consequently those of the active region. Then, after developing the resin, the bilayer 70 and the substrate 1 are etched using the remaining portion of the resin 71 as a hard mask so as to obtain a trench 6 which will be filled with insulating material so as to form the insulating region 2 of transistor TRN. Compared to this prior art, the method according to an embodiment of the invention provides (FIG. 4) defining at the level of the active mask MSK, the locations of the two insulating domains separated by the separation region (wall of seperation). More precisely, after insolation and development of the resin 71, there remain on the bilayer 70 blocks of resin that will be used as hard masks for making two trenches 60 and 61 in the bilayer 70 and the substrate 1. These two trenches are de facto separated by the separation wall 11 and will be filled with the insulating material to achieve the two insulating domains 20 and 21 of the transistor of Figure 2. It will be noted here that the trenches 60 and 61 are located within the contour of the insulating region 6. And it is this contour that is defined by the designer when he defines the dimension of the active regions. Therefore, providing at the MSK mask two trenches in this insulating region is completely transparent to the designer. The definition of these trenches is advantageously performed automatically during the Boolean generation of the levels used for the manufacture of the active mask taking into account the different dimensions D, LG2, LG1 mentioned above. Once the realization of the insulating domains 20 and 21 has been carried out, the gate dielectric layer OX is formed on the whole of the integrated circuit and the subsequent steps for producing the integrated circuit are carried out in a conventional manner and known per se, in particular the embodiment gate regions of the transistors, lateral spacers of the layer 40 and the insulating region 42. The realization of the protrusion 12 is carried out simultaneously with the production of the gate region 3 and with realization steps identical to those of used for the realization of this grid region. More precisely, after depositing and etching the central portion of the gate region 3 and the central portion 120 of the protrusion 12, these central portions of insulating lateral regions or spacers are flanked. Then the additional insulating region 4 is made with the lower layer 40 in compression. The location and geometry of the polysilicon central portion 120 of the protrusion 12 are defined at the "poly" mask used to define the locations and geometries of the gate regions of the transistors. And again this is done automatically without the intervention of the designer of the circuit and completely transparent to him.
    [0015] The metal contact 9 is made analogously to the metal contacts intended to come into contact with the source, drain and gate regions of the transistor in order to connect them to a metallization level of the interconnection part (BEOL: Back End Of Lines) of the circuit. integrated.
    [0016] The location and the geometry of the contact 9 are defined on the mask "contacts". However, the use of a metal contact 9 directly contacting the second electrode 120 of the capacitive structure is not the only possible solution for connecting this electrode to the supply voltage Vdd as will now be explained in relation with FIGS. 5 and 6. These figures are a partial representation of a ring oscillator produced within the integrated circuit CI. The ring oscillator comprises, in the zone ZZ1 of the integrated circuit, a series of NMOS transistors TRN11-TRN14 (only 4 are represented for purposes of simplification) and in the zone ZZ2 of the PMOS transistors TRP21-TRP24. These NMOS and PMOS transistors are connected together in a conventional manner and known per se to form inverters.
    [0017] Such an inverter structure is found in the zones ZZ3 and ZZ4 of the integrated circuit respectively comprising the PMOS transistors TRP31-TRP34 and the NMOS transistors TRN41-TRN44. We will now describe more particularly the environment of the NMOS transistor TRN11 and the PMOS transistor TRP21, knowing of course that this environment is similar for the other inverters of the oscillator. The active region 10 of the transistor TRN11 is limited by the insulating region 2. The active region 10 comprises the source and drain regions of the transistor TRN11. These source and drain regions are here N + doped regions produced within an underlying substrate or p-type well. The insulating region 2 is locally separated into two insulating domains 20 and 21 by the separation region 11 which here is also an N + doped region opening into the underlying P-type substrate. In the example described here, the polysilicon central portion 120 of the protrusion (second electrode of the capacitive structure) partially covers the separation region 11 and is separated therefrom by the gate oxide layer.
    [0018] The ring oscillator also has on the left of FIG. 5, a zone ZGO also doped N + which contacts the source zone of the transistor TRN11. The separation region 11, part of which is located under the polysilicon portion 120, is extended on the left to contact the zone ZGO. As will be seen in more detail with reference to FIG. 6, this zone ZGO is intended to be connected to ground GND via contact pads CTCO. A zone ZG1, doped N +, situated on the right of FIG. 5, is analogous to the zone ZGO and will allow, as will be seen with reference to FIG. 6, to connect the sources of the NMOS transistors TRN41-TRN44 as well as the regions correspondingly separated partitions 11 to ground via contact pads CTC2. To enable these connections to GND ground, power rails, made for example at the first level of metallization of the integrated circuit, and referenced RZGO and RZG1 cover the corresponding areas ZGO and ZG1 and are connected to them by the corresponding contact pads ( Figure 6). The rails RZGO and RZG1 are intended to be connected to the ground GND.
    [0019] In order to connect the central portion 120 (second electrode) of the capacitive structure to the supply voltage Vdd, an interconnection region 220, also made of polysilicon, is produced above the insulating region 2 limiting the active region of the capacitor. PMOS transistor TRP21.
    [0020] It should be noted here that the two polysilicon regions 120 and 220 are simultaneously made to the gate regions of the transistors using the "poly" mask. A zone ZD1 runs along the transistors TRP21-TRP24 and will allow, as will be seen in more detail with reference to FIG. 6, to connect in particular the sources of the PMOS transistors to the supply voltage Vdd via contact pads CTC1. To enable this connection to the supply voltage Vdd, a supply rail, made for example at the first metallization level of the integrated circuit, and referenced RZD1 covers the zone ZD1 and is connected to it by the corresponding contact pads (FIG. 6). . The rail RZD1 is intended to be connected to the supply voltage Vdd. Moreover, in order to connect the polysilicon regions 220, and consequently the corresponding regions of polysilicon 120, ie the second electrodes of the capacitive structures, to the voltage Vdd, provision is made in this embodiment for a CTC contact connected on the one hand to the polysilicon region 220, and on the other hand to a metallization MTL contacting the rail RZD1.
    [0021] It should be noted that the connection to the ground of the separation regions 11 is simply effected by an extension of these active regions to the zones ZGO and ZG1 already present in the placement scheme (layout) of the conventional oscillator (no equipped with capacitive decoupling structures), while the connection to the voltage Vdd of the second electrodes of the capacitive structures requires the realization of polysilicon regions 220 and metallization MTL to come into contact with the rail RZD1. Reference is now made more particularly to FIGS. 7 to 16 to illustrate another variant of the invention. In this variant, the substrate forms the first electrode and the second electrode of the capacitive structure comprises an electrically conductive trench located at least in the insulating region limiting the active region of the transistor, the electrically conductive trench containing an internal domain configured to allow a reduction. compressive stress in the active region, the second electrode being again separated from the first electrode by a dielectric material. More precisely, with respect to the transistor TRN of FIG. 1, the transistor TRN according to the embodiment illustrated in FIG. 7 comprises a trench 20 having here an upper part 200 situated in the insulating region 2 and extended by a lower part 201 located in the underlying substrate 1 forming the first electrode of the capacitive structure STC, for example connected to ground GND.
    [0022] Furthermore, in this example, the inner walls of the lower portion 201 of the trench are lined with an electrically insulating layer 202, for example silicon dioxide. The internal domain of the trench thus produced contains polycrystalline silicon or polysilicon 203.
    [0023] The upper face of the trench 20 is substantially at the same level as the upper face of the active region 10. This trench is electrically active because it forms the second electrode of the capacitive structure STC and is electrically connected here to the voltage Vdd.
    [0024] This trench 20 also has a mechanical function allowing a reduction of compressive stresses in the active region 10. Indeed, in this embodiment, the polysilicon 202 which is initially amorphously deposited recrystallizes during cooling to become a material. constrained in tension which reduces the compressive stresses especially in the insulating region 2, which consequently makes it possible to reduce compressive stresses in the active region 10. Moreover, such an embodiment has a thermomechanical advantage. Indeed, silicon and polysilicon have identical coefficients of thermal expansion and this results in fewer stresses in the active region when the temperature undergoes changes related to the environment of the product incorporating the integrated circuit. Although in the embodiment of FIG. 7, the trench 20 extends into the underlying substrate, it would have been possible for the trench 20 to be located only within the insulating region 2 without overflowing into the underlying substrate. . And, with such an embodiment, a reduction of about 15% in compressive stress is obtained with respect to the transistor of FIG. 1.
    [0025] That being so, the lower part of the trench 20 located in the underlying substrate also contributes to the reduction of compressive stresses in the active region 10. Thus, the embodiment of FIG. 7 allows a reduction of 30% of the stresses. in compression in the active region with respect to the transistor of FIG. 1. In the upper part, the decoupling capacitor is formed between the polysilicon 203 and the active region 10, the insulating region portion situated between these two electrodes forming the dielectric of the capacitor.
    [0026] In the lower part, the decoupling capacitor is formed between the polysilicon 203 and the substrate 1, the insulating layer 202 forming the dielectric of the capacitor. Furthermore, this layer 202 makes it possible to avoid direct contact between the silicon of the substrate and the polysilicon 203 of the trench, which avoids the creation of point defects in the silicon, which can lead to the appearance of dislocations. The width LG1 of the trench 20 is here equal to the critical dimension CD (Critical Dimension) of the technology in question, in this case 0.15 micrometers. This critical dimension is the minimum dimension of an active region line. The distance LG2 between the edge of the trench 20 and the edge of the active region 10 is here equal to a minimum distance defined by the design rules (DRM) of the technology in question, in this case 0.05 micrometer for a 90 nanometer technology. While in this embodiment, the substrate and the active region 10 are connected to ground GND, the other electrode of the capacitor is connected to the supply voltage Vdd. In this regard, an orifice is provided in the layer 40 to allow the application of this voltage Vdd. This representation is schematic in FIG. 7. One way of making this connection to the supply voltage Vdd is illustrated more particularly in FIGS. 8 and 9. In these embodiments, the electrical connection on the second electrode 20 of the structure capacitive is obtained by a metal contact 9 passing through the additional insulating region 4 to possibly penetrate inside the trench 20 (portion 90 in dashed lines in these figures). D1 (FIG. 8) denotes the minimum distance between the contact region 9 and the edge of the active region. D2 denotes the minimum width of a contact region 9. It should be noted here that such a metal contact also allows a relaxation of the stresses in the active region 10 of the transistor TRN. That being the case, the inventors have observed that even if the metal contact 9 passes only through the insulating region 4, and in particular the CESL layer 40, without penetrating into the trench 20, a relaxation of the compressive stresses in the active region is nevertheless obtained. of the transistor TRN with respect to the compressive stresses of the region 10 of the transistor TRN of FIG. 1. And this is true that the layer 40 is a layer in compression or a layer in tension because in the latter case the material used for the region contact 9 is generally a material itself in tension. And the inventors have observed that the combination of a layer 40 in voltage traversed by a contact region itself in tension used to increase the voltage in the channel region which increases the mobility of electrons.
    [0027] Referring now more particularly to Figures 10 to 13 to illustrate an embodiment of a method for producing the trench 20. More specifically, after having deposited on the substrate 1 a bilayer 70 (silicon oxide / nitride) of silicon) surmounted by a layer of photosensitive resin that is insulated through a mask called "active mask or active region mask", which will allow to determine the contours of the insulating region 2 and therefore those of the active region, after the development of the resin, an etching of the bilayer 70 and the substrate 1 is carried out using the remaining portion of the resin as a hard mask so as to obtain a trench 6 (FIG. 10) which will be filled with insulating material of to form, after mechanochemical polishing and removal of the silicon nitride, the insulating region 2 (Figure 11). Then, as illustrated in FIG. 12, an etching of a first trench is carried out so as to define the upper part 200 and the upper part 201, and the lower part 201 of this first part is re-oxidized. trenched so as to form the electrically insulating layer 202. Thus, at this stage, a trench is obtained, which is here called an initial trench. This initial trench is then filled with polysilicon deposited in the amorphous state at high temperature, the latter being converted, during cooling into polycrystalline silicon, and then etched for example by mechanochemical polishing or dry etching (FIG. 13).
    [0028] Once these operations have been performed, the other operations of making the integrated circuit are carried out in a conventional manner and known per se, in particular the formation of the gate regions of the transistors and the formation of the insulating region 4.
    [0029] Regarding the realization of the metal contact 9, it is made analogous to the metal contacts intended to come into contact with the source, drain and gate regions of the transistor to connect them to a metallization level of the interconnection part. (BEOL: Back End Of Lines) of the integrated circuit. The location and the geometry of the contact 9 are defined on the mask "contacts". However, the use of metal contacts coming into contact with the trench 20 or even entering this trench is not always possible. Indeed, the dimensional constraints to be respected for the realization of a metallic contact vis-à-vis the edge of the active region, may be more severe than those governing the realization of the trench 20.
    [0030] The dimensions D 1 and D 2 in particular are used automatically in the computer tool for generating the mask "contacts" to determine according to the locations of the different active regions 10 and trenches 20, but also as a function of the distance from a possible adjacent region of polysilicon and / or the presence or absence of a metal line at a higher metallization level, the possible locations of the contact region or regions 9 coming to contact or penetrate these trenches as well as the geometries and dimensions of the of these contact regions. And this is done automatically without intervention of the designer of the circuit and completely transparent to him. Reference will now be made more particularly to FIGS. 14 to 16 to illustrate an application of the invention to an integrated circuit comprising a memory device whose memory plane PM has, as illustrated in FIG. 15, non-volatile memory cells CEL. and buried gate selection transistors TSL. More specifically, each CEL memory cell comprises a floating gate transistor TGF formed in and on a P-type semiconductor well separated from an underlying P-type substrate by an N type semiconductor layer. Conventionally, each transistor floating gate comprises a floating gate GF, for example polysilicon, and a control gate CG. Each selection transistor TSL for selecting a row of cells is a MOS transistor whose gate GTSL is a gate buried in the P-type well and electrically isolated from this box by a gate oxide OX, typically silicon dioxide. The N-type buried layer forms the source regions of the TSL selection transistors. It should be noted that the GTSL buried gate is common to the two adjacent TSL selection transistors whose two gate oxides OX are respectively located on the two sides of this buried gate. As is conventional in the art, and illustrated schematically in FIG. 14, the integrated memory device DM within the integrated circuit CI comprises, in addition to the memory plane PM formed by the matrix of memory cells CL, a block or logic block. command including in particular decoders lines and decoders columns. All these elements of the BLC control block include NMOS transistors TRN. And, while because of the density of the memory array it is not possible to dispose of the trenches 20 inside the memory array, but also around this memory array so as to avoid edge effects it is quite advantageous, as illustrated in FIG. 14, to associate with at least some of the NMOS transistors trenches 20 which may in certain cases be located on either side of at least some of these NMOS transistors TRN, way to create capacitive structures. The formation of the trenches 20 of the transistors TRN is performed simultaneously with the formation of the GTSL buried gates of the TSL selection transistors of the memory plane. Indeed, the etching of the trenches intended to receive the buried gates of these transistors and the etching of the first trenches in the insulating region around the transistors TRN and in the underlying substrate are carried out simultaneously and the definition of the locations of these first trenches is defined on the same mask as that allowing the definition of the trenches intended to receive the buried grids. And, this is completely transparent to the designer of the integrated circuit because the locations of the first trench to become the trenches 20 are defined within the insulating regions 2.
    [0031] The depths of the first trenches and those intended to receive the GTSL buried grids are substantially identical. Furthermore, the oxidation of the internal walls of all these trenches leads, on the one hand, to the formation of the gate oxide of the selection transistors and, on the other hand, to the formation of the insulating layer 202. Finally, all these trenches are filled with polysilicon. As illustrated in FIG. 16, CTC contacts are taken on different regions of the memory cells of the memory plane PM. And, by analogy with what has been described above, the formation of these CTC contacts is advantageously carried out simultaneously with the contact regions 9 associated with the transistor TRN using the mask "contacts", which makes it possible to polarize the second electrodes of the capacitive structures.
    权利要求:
    Claims (15)
    [0001]
    REVENDICATIONS1. Integrated circuit, comprising a substrate (1) and at least one component (TR) disposed at least partially within an active region (10) of the substrate (1) bounded by an insulating region (2), characterized in that it furthermore comprises a capacitive structure (STC) having a first electrode intended to be connected to a first potential (GND), a second electrode intended to be connected to a second potential (Vdd), one of the two electrodes being situated at least partly in the insulating region (2).
    [0002]
    2. The integrated circuit of claim 1, wherein the other electrode is formed by a portion of the substrate (1) or is contained in the volume above the insulating region (2).
    [0003]
    An integrated circuit according to claim 1 or 2, wherein said component (TR) is a component adversely sensitive to compressive stresses.
    [0004]
    The integrated circuit of claim 3, wherein the component (TR) is an NMOS transistor.
    [0005]
    5. Integrated circuit according to one of the preceding claims, wherein the first potential is the ground (GND) and the second potential is a supply voltage (Vdd) of the integrated circuit.
    [0006]
    6. Integrated circuit according to one of the preceding claims, further comprising an additional insulating region (4) disposed above the component, the active region (10) and the insulating region (2), and wherein the first electrode comprises a first region (11) formed by a portion of the substrate and locally separating said insulating region (2) into two insulating domains (20, 21) and the second electrode comprises a second electrically conductive region (12) located in the additional insulating region (4) above said separation region, the two electrodes being separated by a layer of a dielectric material (OX).
    [0007]
    The integrated circuit of claim 6, wherein the second region (12) comprises polysilicon (120).
    [0008]
    An integrated circuit according to claim 6 or 7, wherein said first region (11) has an upper face substantially at the same level as said upper face of the active region (10) and opens into a lower region of the substrate (1). .
    [0009]
    9. Integrated circuit according to one of claims 6 to 8, wherein the insulating region (20) located closest to said active region (10) has a volume less than or equal to that of the furthest insulating region (21). of the active region (10).
    [0010]
    The integrated circuit of claims 4 and 7, wherein said layer of dielectric material is analogous to the gate oxide layer (OX) of the NMOS transistor.
    [0011]
    The integrated circuit of claim 10, wherein said second region (12) has a structure similar to that of the gate region of the transistor (TRN).
    [0012]
    Integrated circuit according to one of claims 1 to 5, wherein the substrate (1) forms the first electrode and the second electrode comprises an electrically conductive trench (20) located in at least said insulating region (2) and containing a internal domain configured to allow compressive stress reduction in said active region, the second electrode being separated from the first electrode by a dielectric material (2, 202).
    [0013]
    An integrated circuit according to claim 12, wherein said at least one trench (20) has an upper portion (200) located in said insulating region, and extended by a lower portion (201) in the substrate and separated from the substrate by a layer of dielectric material (202), said inner domain being located in said upper portion and in said lower portion.
    [0014]
    The integrated circuit of claim 12 or 13, wherein said internal domain contains polycrystalline silicon (203).
    [0015]
    15. Integrated circuit according to one of claims 12 to 14, comprising a memory device comprising a memory plane (PM) having nonvolatile memory cells and buried gate selection transistors, and a control block of the memory array comprising NMOS transistors (TRN), said at least one electrically conductive trench (20) being located in at least the insulating region (3) limiting the active region (10) of at least one of these NMOS transistors of the block control and having a depth substantially equal to that of said buried grids.
    类似技术:
    公开号 | 公开日 | 专利标题
    FR3021457A1|2015-11-27|COMPONENT, FOR EXAMPLE NMOS TRANSISTOR, ACTIVE REGION WITH RELEASED COMPRESSION STRESS, AND DECOUPLING CAPACITOR
    JP3825688B2|2006-09-27|Manufacturing method of semiconductor device
    WO2001095392A1|2001-12-13|Damascene architecture electronic storage and method for making same
    FR2782415A1|2000-02-18|HIGH DENSITY SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    US10490632B2|2019-11-26|Integrated circuit comprising components, for example NMOS transistors, having active regions with relaxed compressive stresses
    FR2894069A1|2007-06-01|Metal oxide semiconductor transistor manufacture for random access static memory, by forming vias contacting a gate and source and drain regions on other side of channel region with respect to the gate
    FR3070534A1|2019-03-01|PROCESS FOR PRODUCING CAPACITIVE ELEMENTS IN TRENCHES
    FR3007198A1|2014-12-19|COMPONENT, FOR EXAMPLE NMOS TRANSISTOR, ACTIVE REGION HAVING REPRESSED COMPRESSION STRESSES, AND METHOD FOR MANUFACTURING THE SAME
    FR3070535A1|2019-03-01|INTEGRATED CIRCUIT WITH VERTICAL STRUCTURE CAPACITIVE ELEMENT AND METHOD OF MANUFACTURING THE SAME
    US10453849B2|2019-10-22|Dynamic random access memory structure and method for forming the same
    FR2991502A1|2013-12-06|METHOD FOR MANUFACTURING INTEGRATED CIRCUIT HAVING INSULATION TRENCHES WITH SEPARATE DEPTHS
    EP1586118B1|2008-10-08|Embedded capacitor associated with a sram cell
    FR2910704A1|2008-06-27|Interconnected integrated circuit device e.g. dynamic D flip-flop, forming method for electronic component, involves forming set of interconnection layers connected to semiconductor device and another set of layers, on active layer surface
    FR3003962A1|2014-10-03|METHOD FOR PRODUCING A PHOTOLITOGRAPHY MASK FOR THE FORMATION OF CORRESPONDING CONTACTS, MASK AND INTEGRATED CIRCUIT
    FR3036846A1|2016-12-02|METHOD FOR LOCAL ISOLATION BETWEEN TRANSISTORS MADE ON A SOI SUBSTRATE, ESPECIALLY FDSOI, AND CORRESPONDING INTEGRATED CIRCUIT
    FR3025335A1|2016-03-04|METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT FOR IMPROVING INTEGRATED CIRCUIT RETRO-DESIGN AND CORRESPONDING INTEGRATED CIRCUIT
    US6333254B1|2001-12-25|Methods of forming a local interconnect method of fabricating integrated circuitry comprising an SRAM cell having a local interconnect and having circuitry peripheral to the SRAM cell and method of forming contact plugs
    JP2008071861A|2008-03-27|Semiconductor memory and manufacturing method thereof
    FR3057393A1|2018-04-13|INTEGRATED CIRCUIT WITH DECOUPLING CAPACITOR IN A TYPE TRIPLE CAISSON STRUCTURE
    FR2995139A1|2014-03-07|TRANSISTOR MOS
    FR3050868A1|2017-11-03|MOS TRANSISTOR STRUCTURE, ESPECIALLY FOR HIGH VOLTAGES IN SILICON-INSULATING TYPE TECHNOLOGY
    FR3108206A1|2021-09-17|Integrated capacitive element and corresponding manufacturing process
    JP2006270110A|2006-10-05|Semiconductor device and manufacturing method thereof
    FR3098984A1|2021-01-22|Integrated circuit with double insulation of the deep and shallow trench type
    FR3069369A1|2019-01-25|INTEGRATED CIRCUIT WITH SHARED MASK CONTACT
    同族专利:
    公开号 | 公开日
    US20150340426A1|2015-11-26|
    CN105097803A|2015-11-25|
    FR3021457B1|2017-10-13|
    CN205069638U|2016-03-02|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20050139887A1|2003-12-31|2005-06-30|Dongbuanam Semiconductor Inc.|Methods of fabricating capacitor|
    US20050151183A1|2004-01-14|2005-07-14|Taiwan Semiconductor Manufacturing Co.|Novel random access memory capacitor in shallow trench isolation with improved electrical isolation to overlying gate electrodes|
    DE102011001527A1|2010-06-02|2011-12-08|Infineon Technologies Ag|Shallow trench isolation area with buried capacitor|
    US20120267759A1|2011-04-21|2012-10-25|Shroff Mehul D|Decoupling capacitors recessed in shallow trench isolation|
    US20140131771A1|2012-11-15|2014-05-15|Globalfoundries Inc.|Semiconductor structure including a semiconductor-on-insulator region and a bulk region, and method for the formation thereof|FR3057393A1|2016-10-11|2018-04-13|StmicroelectronicsSas|INTEGRATED CIRCUIT WITH DECOUPLING CAPACITOR IN A TYPE TRIPLE CAISSON STRUCTURE|
    US10818669B2|2017-08-28|2020-10-27|StmicroelectronicsSas|Integrated circuit with vertically structured capacitive element, and its fabricating process|
    US10879233B2|2017-08-28|2020-12-29|StmicroelectronicsSas|Process for fabricating capacitive elements in trenches|
    US10943862B2|2018-01-09|2021-03-09|StmicroelectronicsSas|Integrated filler capacitor cell device and corresponding manufacturing method|
    US10971578B2|2018-10-08|2021-04-06|StmicroelectronicsSas|Capacitive electronic chip component|
    US11004785B2|2019-08-21|2021-05-11|StmicroelectronicsSas|Co-integrated vertically structured capacitive element and fabrication process|US4392210A|1978-08-28|1983-07-05|Mostek Corporation|One transistor-one capacitor memory cell|
    JP3238066B2|1996-03-11|2001-12-10|株式会社東芝|Semiconductor storage device and method of manufacturing the same|
    US5843820A|1997-09-29|1998-12-01|Vanguard International Semiconductor Corporation|Method of fabricating a new dynamic random access memory cell having a buried horizontal trench capacitor|
    US6407898B1|2000-01-18|2002-06-18|Taiwan Semiconductor Manufacturing Company Ltd.|Protection means for preventing power-on sequence induced latch-up|
    US6492244B1|2001-11-21|2002-12-10|International Business Machines Corporation|Method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator devices|
    US6936881B2|2003-07-25|2005-08-30|Taiwan Semiconductor Manufacturing Company, Ltd.|Capacitor that includes high permittivity capacitor dielectric|
    DE102005030585B4|2005-06-30|2011-07-28|Globalfoundries Inc.|Semiconductor device with a vertical decoupling capacitor and method for its production|
    JP4242880B2|2006-05-17|2009-03-25|日本テキサス・インスツルメンツ株式会社|Solid-state imaging device and operation method thereof|
    TWI355069B|2007-11-06|2011-12-21|Nanya Technology Corp|Dram device|
    US8188528B2|2009-05-07|2012-05-29|International Buiness Machines Corporation|Structure and method to form EDRAM on SOI substrate|
    US8159015B2|2010-01-13|2012-04-17|International Business Machines Corporation|Method and structure for forming capacitors and memory devices on semiconductor-on-insulator substrates|
    US8896096B2|2012-07-19|2014-11-25|Taiwan Semiconductor Manufacturing Company, Ltd.|Process-compatible decoupling capacitor and method for making the same|
    FR3007198B1|2013-06-13|2015-06-19|St Microelectronics Rousset|COMPONENT, FOR EXAMPLE NMOS TRANSISTOR, ACTIVE REGION WITH RELEASED COMPRESSION STRESSES, AND METHOD OF MANUFACTURING|
    法律状态:
    2015-04-22| PLFP| Fee payment|Year of fee payment: 2 |
    2015-11-27| PLSC| Publication of the preliminary search report|Effective date: 20151127 |
    2016-04-22| PLFP| Fee payment|Year of fee payment: 3 |
    2017-04-21| PLFP| Fee payment|Year of fee payment: 4 |
    2018-04-23| PLFP| Fee payment|Year of fee payment: 5 |
    2020-02-14| ST| Notification of lapse|Effective date: 20200108 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1454552A|FR3021457B1|2014-05-21|2014-05-21|COMPONENT, FOR EXAMPLE NMOS TRANSISTOR, ACTIVE REGION WITH RELEASED COMPRESSION STRESS, AND DECOUPLING CAPACITOR|FR1454552A| FR3021457B1|2014-05-21|2014-05-21|COMPONENT, FOR EXAMPLE NMOS TRANSISTOR, ACTIVE REGION WITH RELEASED COMPRESSION STRESS, AND DECOUPLING CAPACITOR|
    US14/715,814| US20150340426A1|2014-05-21|2015-05-19|Component, for example nmos transistor, with an active region under relaxed compressive stress, and associated decoupling capacitor|
    CN201510261090.4A| CN105097803A|2014-05-21|2015-05-20|Component with an active region under relaxed compressive stress, and associated decoupling capacitor|
    CN201520328769.6U| CN205069638U|2014-05-21|2015-05-20|Integrated circuit|
    [返回顶部]