• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates to a method for flattening a structure comprising a substrate (20) having an upper surface provided with recesses and coated with a continuous barrier layer (26) surmounted by a layer of continuous copper filling at least the recesses, the method comprising the following successive steps: a) chemical-mechanical polishing of the copper, this polishing being selective with respect to the barrier layer (26) so that copper remains in the recesses (22) recessed relative to the upper surface of the substrate; b) depositing on the exposed surface of the structure a material (34) covering at least the copper at the recesses; and c) chemical-mechanical polishing smoothing of the structure until the substrate (20) is exposed, the copper remaining buried under the material (34).
    公开号:FR3021455A1
    申请号:FR1454578
    申请日:2014-05-21
    公开日:2015-11-27
    发明作者:Maurice Rivoire；Viorel Balan
    申请人:Commissariat a lEnergie Atomique CEA；STMicroelectronics Crolles 2 SAS；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] TECHNICAL FIELD The present application relates to a method for planarizing a structure comprising a face provided with recesses filled with copper. B13295 - 14-GR4-0016 - DD15221CV
    [0002] DISCUSSION OF THE PRIOR ART In various applications, it is desired to produce a flattened structure comprising recesses filled with copper. In an exemplary application, it is expected to assemble two chips or slices of integrated circuits face to face each having such a flattened face so that the chips or slices can be bonded by direct copper-copper bonding. By direct bonding is meant any bonding made without adding adhesive material. These collages can be made at room temperature or not, and be assisted or not an external compression. If no thermocompression is used, the constraints in terms of flatness of the faces to be assembled are important in order to obtain a satisfactory bonding. A structure comprising a face provided with copper-filled recesses flush with this face is generally made by etching the recesses, filling the copper recesses, and smoothing the surface of this recess. B13295 - 14-GR4-0016 - DD15221CV 2 structure so that the copper is flush at this face. FIGS. 1A to 1D are reproductions of FIGS. 1A to 1D of the patent application FR2947481 which describes successive steps of such a planarization process, in the case of recesses having widths of the order of 10 pin. . Figure lA shows a structure 2 before planarization. The structure comprises a silicon wafer 6 covered with a layer of silicon oxide 8 in which recesses 11 have been etched. A diffusion barrier layer 9 of titanium nitride was then deposited on the silicon oxide layer 8 and a copper layer 12 was formed on the barrier layer so that the copper 12 fills the recesses 11. At this stage the upper surface of the copper 15 comprises steps 13. FIG. 1B shows the structure of FIG. 1A after a first polishing step leading to a planar upper surface of the copper 12. For this purpose, a chemical-mechanical polishing with a leveling product is done. FIG. 1C shows the structure of FIG. 1B after a second polishing step to remove the copper resting on the upper surface of the barrier layer 9 and to leave copper studs 10 in the recesses 11. This second step of FIG. The polishing was carried out by chemical-mechanical polishing with a copper-etching material selectively with respect to the barrier layer 9. FIG. 1D shows the structure of FIG. 1C after removal, by chemical mechanical polishing, of the layer Barrier 9 disposed on either side of the pads 10. It turns out that the method described in relation to FIGS. 1A to 1D does not make it possible to obtain the desired results when the dimensions of the recesses and / or spaces between these recesses become less than 5 μm, and more particularly when these dimensions become less than 1 μm.
    [0003] B13295 - 14 - GR4-0016 - DD15221CV 3 Summary Thus, an embodiment provides a method of planarizing a structure comprising a substrate having an upper surface provided with recesses and coated with a continuous barrier layer surmounted by a a continuous copper layer filling at least the recesses, the method comprising the following successive steps: a) chemical-mechanical polishing of the copper, this polishing being selective with respect to the barrier layer so that copper remains in the recesses recessed by relative to the upper surface of the substrate; b) depositing on the exposed surface of the structure a material covering at least copper at the recesses; and c) chemical-mechanical polishing smoothing of the structure until the substrate is exposed, the copper remaining buried beneath said material. According to one embodiment, the method further comprises the following step: d) chemical-mechanical polishing smoothing said material and the substrate, this polishing exposing the copper. According to one embodiment, the material or materials of the barrier layer are selected from the group consisting of titanium, tantalum, titanium nitride and tantalum nitride, chromium, ruthenium, cobalt and molybdenum. In one embodiment, said material is selected from the group consisting of titanium, titanium nitride, tantalum, tantalum nitride, chromium, ruthenium, molybdenum, and tungsten. According to one embodiment, said material is selected from the group consisting of titanium, titanium nitride, tantalum, tantalum nitride, molybdenum, chromium, ruthenium, tungsten, or a dielectric such as oxide or silicon nitride with carbonaceous and or porous compounds.
    [0004] According to one embodiment, the substrate is an insulating layer. According to one embodiment, the insulating layer is a silicon oxide layer.
    [0005] One embodiment provides a chip or semiconductor wafer, one face of which has a layer provided with barrier layer-covered recesses filled with copper, the upper surface of which is recessed with respect to the upper surface of the substrate, the copper being coated with a material. According to one embodiment, the material or materials of the barrier layer are selected from the group comprising titanium, tantalum, titanium nitride and tantalum nitride, cobalt and molybdenum.
    [0006] According to one embodiment, said material is selected from the group comprising titanium, titanium nitride, tantalum, tantalum nitride, molybdenum, tungsten. One embodiment provides face-to-face assembly of two chips or wafers as above having areas of said material of the same topology facing each other. BRIEF DESCRIPTION OF THE DRAWINGS These and other features and advantages will be set forth in detail in the following description of particular embodiments in a non-limiting manner in connection with the accompanying figures, in which: FIGS. 1A-1D, described previously, are reproductions of FIGS. 1A to 1D of FR2947481; Figure 2 is a schematic sectional view showing a structure obtained after the implementation of the flattening process described in relation to Figures lA to 1D; FIGS. 3A and 3B are diagrammatic sectional views showing, on a nanometric scale, a front structure B13295 - 14 - GR4-0016 - DD15221CV and after the application of the flattening process described in connection with FIGS. at 1D; Figs. 4A-4C are schematic sectional views illustrating an embodiment of a planarizing process; Fig. 4D is a schematic sectional view illustrating an additional step of the method described in connection with Figs. 4A-4C; and Figure 5 shows two structures such as those of Figure 4C, contiguous. For the sake of clarity, the same elements have been designated by the same references in the various figures and, in addition, the various figures are not drawn to scale. DETAILED DESCRIPTION Fig. 2 is a schematic sectional view showing a structure of the type of Fig. 1C after the chemical mechanical polishing step described in connection with Fig. 1D has been performed. In this structure the dimensions of the recesses and spaces between the recesses are less than 5 pin. It can be seen that peripheral depressions 15 appear at the edge of the copper of the studs 10. These recesses have a depth that can be between 1 and 50 nm and a width that can be between 1 nm and several μm. FIGS. 3A and 3B show an example of a structure comprising, in a substrate 20, recesses 22 filled with copper 24 with the interposition of a barrier layer 26, respectively before and after the application of the flattening process described in relation to with Figures 1A to 1D. In these figures and in the following figures, the term "substrate" is the material in which the recesses are formed. This substrate 20 may be an insulating layer, for example a layer of silicon oxide deposited on a support or an underlying stack. The barrier layer 26 is, for example, a tantalum nitride coated tantalum layer having a thickness ranging from 1 to 100 nm, preferably from 20 to 20 nm, example equal to 15 nm. The structure shown comprises two regions: - a region 28 dense recesses 22, right in the figures, wherein recesses 22 form a network of recesses, the recesses of the network being spaced from each other less than 5 pin, and a low-density recess region 22, left in the figures, wherein a recess 22 of a non-critical width of 10 nm to 1 mm is spaced at least 5 fun from neighboring recesses. In FIG. 3A, the copper 24 has been deposited on the entire structure and forms a layer whose bottom of the lower parts facing the recesses 22 is situated above the upper surface of the barrier layer 26.
    [0007] In FIG. 3B, a dashed line 32 illustrates the level of the upper surface of the structure in the case of ideal planarization. In practice, as shown in this figure, the upper surface of the structure after planarization by chemical mechanical polishing has, at the nanoscale, many defects, these defects may be: - peripheral recesses 15 at the edge of the copper 24 filling the recesses 22, and - a general erosion of the upper face of the structure, this erosion being greater in the region 28 dense in recesses than in the region 30 not dense recesses. It can be seen that the erosion of the upper surface of the structure increases as the dimensions of the recesses and spaces between these recesses decrease. By way of example, the gap between the line 32 and the upper surface of the region 28 of dense recesses may be greater than 10 nm. For example, for recesses with a width of 3 gm, the difference is about 15 nm in the case where the space between the recesses is 3 gm, and about 50 nm in the case where the space between the recesses 35 is 1 gm.
    [0008] B13295 - 14-GR4-0016 - DD15221CV 7 Such defects on the surface of the structure pose serious technological problems, for example in the case of an assembly of two chips by direct copper-copper bonding. It would therefore be desirable to have a method of flattening a structure of the type of FIG. 1A or 3A, such that the aforementioned defects (peripheral hollows and erosion of the upper face) are eliminated. FIGS. 4A-4C illustrate an embodiment of successive planarization steps of a structure of the type of FIG. 3A. FIG. 4A shows the structure of FIG. 3A after completion of the planarization steps described in relation with FIGS. 1B and 1C, that is to say after chemical-mechanical polishing smoothing and etching the copper 24 selectively. relative to the barrier layer 26. In this embodiment, the chemical mechanical polishing is performed so that the copper 24 filling the recesses 22 is recessed from the level of the lower surface of upper portions 26A of the barrier layer. 26. The gap between the lower surface of the portions 26A and the upper surface of the copper 24 is at least a few tenths of a nanometer, for example 1 nm. It can go up to 5 to 100 nm, depending on the desired final profile, as will be seen below. As will be seen later, this gap will protect the copper 24 during the step of removing the upper portions 26A of the barrier layer 26. Optionally, a step of selective dry etching of the copper can be carried out at this stage to increase slightly this gap. At the step illustrated in FIG. 4B, a material 34 has been deposited. Thus, at each recess 22, the upper face of the copper 24 is coated with a portion 34A of this material 34. The minimum thickness of the material 34 is chosen so that it protects the copper 24 on all areas. Thus, the portions 34A reach a level higher than that of the upper surface of the portions 26A of the barrier layer.
    [0009] The thickness of the material 34 may be between 1 and 100 nm, for example 15 nm. The material 34 is chosen so that it can be polished at the same time as the material forming the barrier layer 26 and that, given the difference between the lower surface of the portions 26A and the upper surface of the copper 24, it remains at least partially present throughout the copper surface during the subsequent step of removing the upper portions 26A of the barrier layer 26. It thus protects the copper throughout this step. By way of example, for a tantalum nitride-coated tantalum barrier layer 26, the material 34 may be titanium, titanium nitride, tantalum, tantalum nitride, molybdenum, oxide or nitride. of silicon. In the step illustrated in FIG. 4C, the upper surface of the structure was flattened by chemical mechanical polishing until the substrate 20 was exposed while maintaining a residue of the material 34 over the entire copper surface. Thus the portions 26A of the barrier layer 26 were removed while the copper was protected by the material 34. The upper surface of each portion 34A coating the copper top 24 of the recesses 22 is flush with the exposed surface of the substrate By way of example, after this step, the thickness of the portions 34A is between 1 and 100 nm, for example 10 nm.
    [0010] According to a first embodiment, it will be possible to stop at the step described in relation with FIG. 4C leaving the portions 34A in place. As illustrated in Figure 5, this first variant allows a bonding between the materials 34 of two chips or slices 50 and 60 of the same type. In this case, the material 34 will have been chosen so that it is electrically conductive and has a diffusion barrier effect with respect to the copper. Thus, in the event of misalignment between the two chips or wafers 50 and 60, as shown, there will be no diffusion of the copper of a stud 24 into the dielectric of the substrate in front. In a second alternative embodiment, the process described in connection with FIGS. 4A-4C is followed by an additional chemical-mechanical polishing step with a smoothing chemical to remove portions 34A. FIG. 4D shows the structure of FIG. 4C after this additional chemical mechanical polishing step has been performed, the polishing having been stopped on the top surface of the copper 24 filling the recesses 22 (or under this surface) so that the exposed surface of the copper 24 is finally flush with the upper surface of the substrate 20. Thus, with respect to the case of the structure of FIG. 4C, there are no portions 34A of the material 34 at the top 15 of the Copper 24 filling the recesses 22. In this second variant, the material 34, which is finally removed can, as indicated above be a dielectric. The structure of FIGS. 4C and 4D has an upper surface free of peripheral depressions 15 at the edges of the material 34 or copper 24 generated by chemical mechanical polishing regardless of the dimensions of the recesses and gaps between recesses. Moreover, in these structures, the upper surface of the dense region of recesses 28 is at the same level as the upper surface of the sparse region in recesses 30. The implementation of the planarization method described in connection with the figures 4A to 4C, or of its variant described in relation to FIGS. 4A to 4D, makes it possible to obtain structures whose upper surface is flat, the differences in level between different regions of this surface not exceeding 5 nm, or even 2 nm. Such structures may, for example, be assembled one on the other by direct bonding of the material 34 or copper flush 24 at the face of one of the structures with the material 34 or copper 24 35 flush with the level of the face of the other structure.
    [0011] B13295 - 14 - GR4-0016 - DD15221CV Specific embodiments have been described. Various variations and modifications will be apparent to those skilled in the art. In particular, although the structure described in relation to FIGS. 3A, 3B, and 4A to 4D comprises two regions 28 and 30 provided with recesses of different dimensions and in different numbers, the number, the dimensions, the arrangement and the topology of the recesses may be chosen by those skilled in the art. For example, it will be possible to make recesses passing through the substrate 20. The topology of the recesses may be adapted to form, for example pads, vias or metal connection lines. Those skilled in the art may choose, for the various layers described in connection with Figures 4A to 4D, other materials than those indicated by way of example. In particular, the material of barrier layer 26 indicated as tantalum nitride coated tantalum may be replaced by other materials selected from the group consisting of titanium coated titanium nitride, tungsten, chromium, ruthenium , molybdenum and cobalt. In addition, in the case of the second variant, the material of the layer 34 may be a dielectric, for example silicon oxide or nitride with carbonaceous and / or porous compounds. Moreover this layer 34 may be composed of several layers of the aforementioned materials. In addition, although recesses have been described in a silicon oxide substrate 20, other dielectric materials may be used, particularly silicon nitride, silicon oxide with porous or non-porous carbon compounds. porous, glass, polymers and other organic compounds.
    [0012] Although an embodiment of successive steps of a planarization method has been described, the number and / or order of these steps may be modified. For example, to obtain the structure of FIG. 4D, the steps described with reference to FIGS. 4C and 4D will preferably be carried out during a single chemical-mechanical polishing B13295 - 14-GR4-0016 - DD15221CV 11 stopping on the upper surface of the copper 24 filling the recesses 22. Those skilled in the art will implement the chemical mechanical polishing processes described here in a known manner. For example, it may use FREX300S industrial equipment from Ebara or Reflexion Low K from Applied Materials. Copper polishing will for example be performed on an IC1000 fabric from Dow Chemical and the so-called Cu DCM-C74 product from Fujimi. The polishing of the barrier will, for example, be carried out with the Cabot 10 B7001 product on a Cabot D200 fabric.
    权利要求:
    Claims (11)
    [0001]
    REVENDICATIONS1. A method of flattening a structure comprising a substrate (20) having an upper surface provided with recesses (22) and coated with a continuous barrier layer (26) surmounted by a continuous copper layer (24) filling at least the recesses, the method comprising the following successive steps: a) chemical-mechanical polishing of the copper (24), this polishing being selective with respect to the barrier layer (26) so that copper remains in the recesses (22) recessed Relative to the upper surface of the substrate (20); b) depositing on the exposed surface of the structure a material (34) covering at least the copper at the recesses; and c) chemical-mechanical polishing smoothing of the structure until the substrate (20) is exposed, the copper remaining buried under said material (34).
    [0002]
    The method of claim 1, further comprising the step of: (d) mechano-chemical polishing smoothing said material (34) and the substrate (20), which polishing exposes the copper (24).
    [0003]
    The method of claim 1 or 2, wherein the barrier layer (26) material (s) is selected from the group consisting of titanium, tantalum, titanium nitride and tantalum nitride, chromium, ruthenium, cobalt and molybdenum.
    [0004]
    4. A process according to claim 1 or 3, wherein said material (34) is selected from the group consisting of titanium, titanium nitride, tantalum, tantalum nitride, chromium, ruthenium, molybdenum, and tungsten.
    [0005]
    The method of claim 2, wherein said material (34) is selected from the group consisting of titanium, titanium nitride, tantalum, tantalum nitride, molybdenum, chromium, ruthenium, tungsten, or Dielectric material such as silicon oxide or nitride with carbonaceous and or porous compounds.
    [0006]
    The method of any one of claims 1 to 5, wherein the substrate (20) is an insulating layer.
    [0007]
    The method of claim 6, wherein said insulating layer is a silicon oxide layer.
    [0008]
    8. A chip or semiconductor wafer having a face having a layer (20) provided with recesses (22) coated with a barrier layer (26) and filled with copper (24), whose upper surface is set back from the upper surface of the substrate (20), the copper being coated with a material (34).
    [0009]
    The chip or wafer of claim 8, wherein the barrier layer material (s) (26) is selected from the group consisting of titanium, tantalum, titanium nitride and tantalum nitride, cobalt and molybdenum. .
    [0010]
    The chip or wafer of claim 8 or 9, wherein said material (34) is selected from the group consisting of titanium, titanium nitride, tantalum, tantalum nitride, molybdenum, tungsten.
    [0011]
    11. Face-to-face assembly of two chips or wafers (50, 60) according to any one of claims 8 to 10 comprising areas of said material (34) of the same topology facing each other.
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    法律状态:
    2015-04-22| PLFP| Fee payment|Year of fee payment: 2 |
    2015-11-27| PLSC| Publication of the preliminary search report|Effective date: 20151127 |
    2016-04-22| PLFP| Fee payment|Year of fee payment: 3 |
    2017-04-21| PLFP| Fee payment|Year of fee payment: 4 |
    2018-04-23| PLFP| Fee payment|Year of fee payment: 5 |
    2019-04-18| PLFP| Fee payment|Year of fee payment: 6 |
    2020-04-22| PLFP| Fee payment|Year of fee payment: 7 |
    2021-04-21| PLFP| Fee payment|Year of fee payment: 8 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1454578A|FR3021455B1|2014-05-21|2014-05-21|PROCESS FOR FLOWING COPPER-FILLED EVIDENTS|FR1454578A| FR3021455B1|2014-05-21|2014-05-21|PROCESS FOR FLOWING COPPER-FILLED EVIDENTS|
    US14/706,579| US9620385B2|2014-05-21|2015-05-07|Method of planarizing recesses filled with copper|
    US15/447,410| US9865545B2|2014-05-21|2017-03-02|Plurality of substrates bonded by direct bonding of copper recesses|
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