• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A method of modifying the state of stress of a block of semiconductor material comprising steps of: - amorphizing a lower region (12a, 22a, 32a) of a block of semiconductor material resting on a substrate while the crystalline structure of a lower region (12b, 22b, 32b) of the block and in contact with the upper region is conserved, - creep annealing according to a thermal budget adapted to allow the creep of the lower region (12b , 22b, 32b) without recrystallizing the material of this lower region, recrystallization annealing of the lower region (12b, 22b, 32b).
    公开号:FR3015768A1
    申请号:FR1363419
    申请日:2013-12-23
    公开日:2015-06-26
    发明作者:Sylvain Maitrejean；Shay Reboh；Romain Wacquez
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] TECHNICAL FIELD AND PRIOR ART The present description relates to the field of semiconductor structures, and more particularly to that of methods for producing such structures comprising a semiconductor structure. or a plurality of steps for changing the state of stress of a block of semiconductor material. To improve the performance of certain microelectronic components, in particular the transistors, it may be advantageous to provide these in part in a layer of semiconductor material on which a mechanical stress or compression is applied. A voltage constraint applied for example on a silicon transistor channel makes it possible to induce an increase in the speed of the electrons, whereas when a silicon channel is subjected to a compressive stress, the speed of conduction by holes is increased. To apply a stress on a block of semiconductor material, it is known to form on this block an amorphous material having an intrinsic stress. US2008 / 0169508 A1 discloses, for example, a method in which an Si block is stressed through a voltage-constrained silicon nitride layer, whereas on the same substrate another block of Si is constrained. via a layer of silicon nitride constrained in compression. Another method for constraining a semiconductor material is to impose the mesh parameter of another semiconductor material.
    [0002] Document US 2012/0068267 A1 for example presents a method in which such a method is used: a localized implantation of a block of Si surmounted by a SiGe zone is carried out to amorphize a lower region of the Si block and to relax this region. The upper region of the Si block undergoes a constraint imposed by the SiGe zone. The lower region of the Si block is then recrystallized using the upper region of this block as seed. The constrained material of the upper region then imposes its mesh parameter on that of the lower region. In some cases, it may also be desired to reduce the stress state of a block of semiconductor material. For example, when a device is made with N-type and P-type transistors from the same semiconductor layer of a voltage-pre-stressed substrate, it is possible to seek to locally relax certain zones of the The problem is to find a new method for modifying the state of stress of a semiconductor block. DISCLOSURE OF THE INVENTION The present invention relates to a method comprising the steps of: a) amorphousizing a lower region of a semiconductor material block resting on a substrate while the crystal structure of an upper region of the block and in contact with the upper region is retained, b) perform at least one creep annealing in a time and temperature adapted to allow creep of the lower region without recrystallizing the material of this lower region, c) perform at least one annealing of recrystallization of the lower region.
    [0003] Thus, according to the invention, creep annealing makes it possible to further modify the stress state of the block of semiconductor material that a process in which a recrystallization is carried out directly after rendering the lower region of this block amorphous.
    [0004] The method can be implemented to relax a block of constrained semiconductor material, or to constrain a block of unconstrained or relaxed semiconductor material, or to increase the stress of a block of constrained semiconductor material.
    [0005] Thus, according to a first possibility of implementing the method, in step a), the block of semiconductor material can be constrained. This semiconductor block may have been formed from, or may belong to, a surface layer of a semiconductor-on-insulator or semiconductor-on-insulator type substrate.
    [0006] According to one possible implementation of the method, trenches are formed in the insulating layer on either side of the semiconductor block. This step can be carried out before or after the amorphization. Between step a) and step b), a step of forming a stress zone of the block of semiconductor material may be provided.
    [0007] The stressing zone of the block of semiconductor material may be based on an amorphous constrained material such as, for example, constrained silicon nitride. According to one possible implementation of the method in which said semiconductor block is based on Si, the creep annealing in step b) can be carried out at a temperature between 300 ° C and 400 ° C. A method as defined above can be implemented in the context of the manufacture of a microelectronic device with transistors. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be better understood on reading the description of exemplary embodiments given, purely by way of indication and in no way limiting, with reference to the appended drawings in which: FIGS. 1A-1D illustrate an example of process for reducing the state of stress of a constrained semiconductor block and in which at least one creep annealing according to the invention of the semiconductor block is produced; FIG. 2 illustrates an alternative method in which the semiconductor block rests on an etched insulating zone; FIGS. 3A-3E illustrate another example of a method according to the invention for constraining a constrained semiconductor block and in which at least one creep annealing according to the invention of the semiconductor block is produced; FIGS. 4A-4E illustrate an alternative method according to the invention implemented on a solid substrate; As is customary in the representation of semiconductor structures, the various sectional views are not drawn to scale. The different parts shown in the figures are not necessarily in a uniform scale, to make the figures more readable, the angles made by the side faces of the various layers used in particular to illustrate the different states of stress of these layers. In addition, in the following description, terms which depend on the orientation of a structure, such as "lower", "upper", apply considering that the structure is oriented as illustrated in the figures. . DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS A first example of a method according to the invention for modifying the stress state of a semiconductor block will now be described with reference to FIGS. 1A-1D. The starting material of this process is, in this example, a semiconductor substrate constrained on insulator, for example of the type sS01 (SOI for "strained silicon on insulator" or "silicon constrained on insulator"). The substrate thus comprises a support layer 10, for example a semiconductor layer which may be based on Si, and an insulating layer 11, for example based on silicon oxide, which is located on and in contact with the layer support 10, and a so-called "superficial" semiconductor layer located on and in contact with said insulating layer 11 and which is constrained, for example in tension (Figure 1A). The stressed surface semiconductor layer may have a thickness of, for example, between 10 nm and 200 nm, preferably between 15 nm and 40 nm. An ion implantation (FIG. 1B) of a semiconductor block 12 of the surface layer which may have been obtained by etching thereof is then carried out.
    [0008] Implantation is performed so as to make a lower region 12a of the semiconductor block 12 amorphous. The implantation profile is such that the upper region 12b retains its crystalline structure. The upper region receives a lower dose than the amorphization threshold which is generally of the order of 10% of atoms displaced in a crystal, ie about 3.6E21 atoms.cm-3 in crystalline Si.
    [0009] In this particular example, the amorphous lower region 12a is in contact with the insulating layer 12 of the substrate, while a seed crystal is preserved on the surface of the semiconductor block 12. The ionic implantation species is preferably a light species. The amorphizing implantation can be carried out using an inert species for the implanted semiconductor material, for example Si atoms when the semiconductor material that is implanted is Si. By "inert species" here we mean a species which is not intended to modify the conduction properties of the implanted semiconductor material. The conditions for amorphous implantation of the semiconductor block 12 can be defined using a simulation tool such as for example a software of the C-TRIM (CTRIM for "Crystal Transport of Ions in Matter") type using Monte Carlo algorithms. In a case where a 30 nm thick region of a block 12 of Si is implanted, the implantation energy may for example be between 15 keV and 30 keV, depending on an implantation dose, for example between 1E14 and 8E14 atoms / cm2. For an implantation of a block of Si, a dose for example of the order of 4E14 with an energy for example of the order of 20 keV or a dose for example of the order of 3E14 with an energy for example of order of 30 keV make it possible to produce a stack comprising an amorphous lower region of the order of 20 nm thick surmounted by a crystalline upper region of the order of 10 nm thick. Next, creep annealing is carried out (FIG. 1C). Creep annealing is performed at a temperature and time selected to allow the amorphous lower region 12a to flow while preventing recrystallization of that region. The temperature of this creep annealing is thus chosen to be less than the recrystallization temperature of the semiconductor material of the semiconductor block 12, for example less than 500 ° C. when the semiconductor block 12 is based on Si.
    [0010] In one case, for example, of a block 12 based on another semiconductor material, such as SixGel_x or Ge, it is possible to choose the creep temperature as a function, for example, of recrystallization temperature data such that in O. Hellman, Materials Science and Engineering: R: Reports Volume 16, Issue 1, 1996.
    [0011] The thermal budget of the creep annealing is furthermore provided sufficiently large to allow a relaxation of the initially constrained lower region 12b of the semiconductor block 12, and in particular a relaxation such that the lower region 12b of the semiconductor block 12 undergoes a stress variation of at least 300 MPa.
    [0012] The document "viscosity and elastic constants of amorphous Si and Ge", by Witvrouw et al., Journal of Applied Physics 74, 1993, for example, gives Si relaxation conditions. On the basis of the data of the preceding document, it is possible to determine a table giving results of stress measurements as a function of an annealing time exerted on a block of Si after it has undergone a creep annealing at a chosen temperature of the order of 350 ° C. To relax this Si semiconductor block having an initial stress for example of the order of 1 GPa, a creep annealing time of the order of 1 hour may be provided. A second table below gives a correspondence between the annealing temperature of an Si block and the annealing time necessary to allow creep, with an associated viscosity value. 15 200 1.3E + 18 5E + 07 225 1.5E + 17 6E + 06 250 2.1E416 9E + 05 275 3.5E + 15 1E + 05 300 6.9E + 14 3E + 04 325 1.6E + 14 7E + 03 350 4.0E-F13 2E + 03 20 375 1.2E + 13 5E + 02 400 3.6E + 12 2E + 02 425 1.2E + 12 5E + 01 450 4.5E + 11 2E + 01 475 1.8E + 11 8E + 00 500 3E + 00 7.5E + 10 525 3.3E + 10 1E + 00 550 1.5E + 10 7E-01 25 575 7.6E + 09 3E-01 600 3.8E + 09 2E-01 625 2.0E + 09 9E-02 650 14E409 5E-02, 5 10 60 120 600 1200 360010 To maintain a reasonable annealing time with respect to implementation constraints from an industrial point of view, an annealing temperature of at least 300 ° C is preferably provided. In the case where the block 12 is based on Si, the creep annealing temperature can be advantageously chosen between 300 ° C and 400 ° C while the duration can be, for its part, fixed for example between several tens of seconds and several hours. Then, after performing creep annealing, a recrystallization annealing of the lower region 12a of the semiconductor block 12 is carried out, using the upper region 12b of the semiconductor block as a starting zone at a recrystallization front. (Figure 1D). To carry out the recrystallization of the semiconductor block 12, when it is based on Si, the annealing is carried out at a temperature preferably greater than 500 ° C., which may be for example between 600 ° C. and 1150 ° C. The annealing time can be provided for example greater than 2 min for an annealing temperature of the order of 600 ° C. A high thermal budget, giving better recrystallization, annealing at a temperature of the order of 1100 ° C. for a period of 30 minutes can advantageously be implemented. According to an alternative embodiment given in FIG. 2, during the formation of the semiconductor block 12 by etching the surface layer, this etching can be prolonged in the insulating layer 11 by stopping on or in the support layer 10 Trenches 17 are thus formed on either side of the semiconductor block 12, around an area 18 of the insulating layer of the substrate on which this block rests. The edges of the insulating zone 18 are here located in the extension of the lateral flanks of the semiconductor block. This can make it possible to further modify the stresses exerted on the semiconductor block. Alternatively, these trenches can be formed after amorphization. In this case, the etching conditions, and in particular the temperature, are provided so as not to cause crystallization of the block.
    [0013] Another example of a process according to the invention is given in FIGS. 3A-3E. This method aims this time to increase the state of stress of a semiconductor block. The starting material is, in this example, a semiconductor-on-insulator type substrate, for example of the SOI (SOI) type, which differs from that of the preceding example of "silicon on insulator" (SOI). by the superficial semiconductor layer 12 located on and in contact with the insulating layer 11 which, this time, has no intrinsic stress. Then, by ion implantation, a lower region 22a of a semiconductor block 22 of the superficial semiconductor layer is rendered amorphous while retaining the crystalline structure of an upper region 22b of this block (FIG. 3B). Then a stressing zone 24 is formed on the upper region 22b of the semiconductor block. The stressing zone 24 may be based on a constrained, amorphous material, such as, for example, SiXNy. The stressing zone 24 may for example be based on SixNy constrained in compression in order to stress the semiconductor block 22 in tension. Creep annealing is then carried out according to a thermal budget sufficient to allow the amorphous region 22b to be rendered amorphous. to flow and planned so as not to recrystallize this region (Figure 3D). This creep annealing is performed at a temperature below the recrystallization temperature of the semiconductor material of the block 12 and sufficiently large to allow this semiconductor material to relax. In the case of a semiconductor block 12 based on Si, the creep annealing can be carried out for example at a temperature of between 300 ° C. and 400 ° C., for a duration of for example between several seconds and several hours. . A recrystallization annealing of the lower region 22a of the semiconductor block 22 is then carried out at a temperature which can be, for example, between 500 ° C. and 1150 ° C. and with a duration of for example greater than 2 minutes.
    [0014] Then, the stressing zone 24 is removed (FIG. 3E). In the case where this zone is based on SiXNV, this shrinkage can be carried out for example by etching with ortho-phosphoric acid H 3 PO 4, at a temperature for example between 50 ° C. and 100 ° C.
    [0015] An alternative embodiment provides for implementing the method which has just been described starting from a bulk substrate ("bulk" according to the English terminology), for example on which a semiconductor block 32 based on Si is formed (Figure 4A). A lower region 32a of the semiconductor block 32 is rendered amorphous while retaining the crystal structure of an upper region 32b of this block (FIG. 4B). Next, a stressing zone 34 is formed on the upper region 32b of the semiconductor block (FIG. 4C). The zone 34 may for example be a compression zone of the semiconductor block 32 based on silicon nitride. Creep annealing is then carried out according to a temperature and duration pair adapted to allow the amorphous lower region 32a to flow without recrystallizing (FIG. 4D). Thus, the thermal budget is provided sufficiently low to prevent recrystallization of the lower region 32a and sufficiently large to allow this semiconductor material to flow, and undergo a stress variation of at least 300 MPa. In the case of a semiconductor block 12 based on Si, the temperature of this creep annealing may be for example between 300 ° C. and 400 ° C., while the duration of the annealing may be, for its part, for example between several tens of seconds and several hours. A recrystallization annealing of the lower region 32a of the semiconductor block 32 is then carried out at a temperature which may be, for example, between 500 ° C. and 1150 ° C., for a duration of for example between 2 min and several hours.
    [0016] Then, the stressing zone 34 is removed (FIG. 4E).
    权利要求:
    Claims (8)
    [0001]
    REVENDICATIONS1. A method of modifying the stress state of a block of semiconductor material comprising the steps of, in that order: a) amorphousizing a lower region (12a, 22a, 32a) of a block of semi-conductive material; conductor resting on a substrate while the crystalline structure of an upper region (12b, 22b, 32b) of the block and in contact with the upper region is preserved, b) creep annealing at a time and a temperature adapted to allow the creep of the lower region (12b, 22b, 32b) without recrystallizing the material of this lower region, c) performing a recrystallization annealing of the lower region (12b, 22b, 32b) of the semiconductor block.
    [0002]
    The method of claim 1, wherein said semiconductor block whose lower region is made amorphous in step a) is a block of constrained semiconductor material.
    [0003]
    The method according to claim 1 or 2, wherein the substrate is a semiconductor-on-insulator substrate comprising a support layer, an insulating layer resting on the support layer and a superficial semiconductor layer lying on the layer. insulator, said semiconductor block belonging to said surface layer.
    [0004]
    4. The method of claim 3, wherein forming trenches in the insulating layer on either side of the semiconductor block.
    [0005]
    5. Method according to one of claims 1 to 4, further comprising between step a) and step b), a step of forming a stressing zone of the block of semiconductor material. ALP-G 12
    [0006]
    6. The method of claim 5, the stressing zone of the block of semiconductor material being based on an amorphous constrained material.
    [0007]
    7. Method according to one of claims 1 to 6, wherein said semiconductor block is based on Si, the creep annealing in step b) being carried out at a temperature between 300 ° C and 400 ° C .
    [0008]
    8. A method for producing a microelectronic device transistor (s) comprising the implementation of a method according to one of claims 1 to 7.
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    法律状态:
    2015-12-31| PLFP| Fee payment|Year of fee payment: 3 |
    2016-12-29| PLFP| Fee payment|Year of fee payment: 4 |
    2018-01-02| PLFP| Fee payment|Year of fee payment: 5 |
    2019-12-31| PLFP| Fee payment|Year of fee payment: 7 |
    2020-12-28| PLFP| Fee payment|Year of fee payment: 8 |
    2021-12-31| PLFP| Fee payment|Year of fee payment: 9 |
    优先权:
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    FR1363419A|FR3015768B1|2013-12-23|2013-12-23|IMPROVED METHOD OF MODIFYING THE STRAIN STATUS OF A BLOCK OF SEMICONDUCTOR MATERIAL|FR1363419A| FR3015768B1|2013-12-23|2013-12-23|IMPROVED METHOD OF MODIFYING THE STRAIN STATUS OF A BLOCK OF SEMICONDUCTOR MATERIAL|
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