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    • 专利摘要:
    Procedure and circuit for the reception of data packets according to the IEEE 802.15.4 (MSK) standard. The present invention consists of a method and its realization in the form of a circuit for the reception of data packets constructed according to the IEEE 802.15.4 standard and in particular the packets that use OQPSK modulation with a shaping pulse whose shape is half a sine cycle (MSK) in the 2.45 GHz band. More specifically, the present invention describes the synchronization of these packets where the synchronization concept comprises chip synchronization, symbol synchronization and frame synchronization. The procedure is based on the use of a digital filter that processes the phase differences obtained from a phase receiver. This filter provides two outputs from which the chip and symbol synchronism is detected simultaneously. (Machine-translation by Google Translate, not legally binding)
    公开号:ES2673669A1
    申请号:ES201631658
    申请日:2016-12-22
    公开日:2018-06-25
    发明作者:Alexis LÓPEZ RIERA；Francisco DEL ÁGUILA LÓPEZ；Rosa GIRALT MAS
    申请人:Universitat Politecnica de Catalunya UPC；
    IPC主号:
    专利说明:

    Procedure and circuit for receiving data packets according to the IEEE 802.15.4 IMSKI standard
    SECTOR OF THE TECHNIQUE
    The present invention is related, in general, to transmission systems
    10 of data by radiofrequency. In particular, the invention relates to the reception of data packets that comply with the IEEE 802.15.4 standard, in particular packages that employ OQPSK modulation with a shaping pulse whose shape is half sine cycle (MSK) in the 2.45 band. GHz, and specifically to the synchronization of these packets. 15 BACKGROUND OF THE INVENTION
    Certain communication systems use frequency modulations for various reasons, including the potential simplicity in both transmission 20 and reception. On the other hand, certain communication systems use displaced phase quaternary modulations (OQPSK) with a shaping pulse whose shape is half a sine cycle, which can be interpreted as a particular form of frequency modulation (Minimum Shift Keying or MSK) with a data coding determined, the IEEE 802.15.4 [1] standard being an example
    25 remarkable. The MSK modulation has a frequency deviation equal to half of the chip frequency, the chip being the basic transmission unit. One way to detect these types of signals is to observe the instantaneous phase at a frequency equal to the chip frequency, that is, once per chip. In particular if it is sampled
    30 this signal at the end of each chip and the phase difference is made with respect to the previous phase differences of 900 and _900 are obtained depending on whether a 1 or an o has been transmitted. A receiver capable of detecting MSK signals in this way is the MSK superregenerative receiver presented to [ES 2 554 992 82).
    The digital communications can be classified in packet mode, the one used in this invention, or in continuous mode or "streaming" and, therefore, each one will have a different way to synchronize. In package mode, each package is preceded by a sequence of "training" (which we will call a preamble) to achieve synchronization. In some cases, synchronization is maintained until the end of the package thanks to the stability of the oscillator crystals.
    5 In the literature there are different methods of synchronism. Basic material can be found in [2] and [3] while more recent results can be seen in [4] and in their references. These publications present techniques that sample the basic unit of information, chip, of the MSK signal at different frequencies. For example, in [5] the chip sampling frequency is 8 times more
    10 larger than that of the chip itself, [6] describes a perfect method to implement digitally and that uses a frequency twice as large as the chip frequency. Another case for example is that of [7]. On the other hand, there are techniques to synchronize with the carrier that operate at the chip frequency but do not achieve the high level synchronization (chip, symbol and frame) required in the IEEE standard
    15 802.15.4.
    [1] IEEE Sld 802.15.4-2011 (Revision 01 IEEE Sld 802.15.4-2006), pp. 1-314, 2011.
    [2] H. Meyr and G. Ascheid, Synchronization in Digital Communications, ser. Wiley Series in Telecommunications. Wiley, 1990
    [3] F. Xiong, Digital Modulation Techniques, ser. Artech House telecommunications 20 library. Artech House, 2006.
    [4] E. Hosseini, "Synchronization techniques for burst-mode continuous phase modulation," Ph.D. dissertation, University of Kansas, Feb 2013. [Online). Available: https: /Ioatd.org/oatd/record Record = hand le% 3A 1808% 2F12963
    [5] D. A. Gudovskiy, L. Chu, and S. Lee, "A novel nondata-aided synchronization
    25 algorithm for MSK-type-modulated signals, "IEEE Communications Letters, vol. 19, no. 9, pp. 1552-1555, Sep 2015.
    [6] A. N. D'Andrea, U. Mengali, and R. Reggiannini, "A digital approach to clock recovery in generalized minimum shift keying," IEEE Transactions on Vehicular Technology, vol. 39, no. 3, pp. 227-234, Aug 1990.
    30 [7] A. A. D'Amico, A. N. D'Andrea, and U. Mengali, "Feedforward joint phase and timing estimation with OQPSK modulation," IEEE Transactions on Vehicular Technology, vol. 48, no. 3, pp. 824-832, May 1999. [EN 2 554 992 82] Patent: Procedure and circuit for signal demodulation
    frequency modulated. Palé and others, 06/23/2014.
    EXPLANATION OF THE INVENTION
    The present invention consists of a method and its implementation in the form of a circuit for the reception, and in particular the synchronization, of data packets that comply with the IEEE 802.15.4 standard (in particular the packages that employ MSK modulation in the band of 2.45 GHz). The standard defines that for this frequency band the transmitted symbols are transformed into 32 chips each. Therefore, the chips are the basic unit of transmission with duration Tx seconds and these chips are modulated with MSK and transmitted. This type of signals can be detected
    10 calculating the phase difference obtained as the difference between the instantaneous phase of a chip and the instantaneous phase of the chip that precedes it. These phase differences range from _900 to 900 (passing through 0 °) depending on the sampling time. If the phase is sampled at the end of each chip, only _90 ° and 90 ° phases will be obtained depending on whether an O or a 1 has been transmitted.
    15 The standard defines that the preamble consists of eight zero symbols. The zero symbol corresponds to the following chip sequence: 1 1 O 1 1 OO 1 1 1 OOOO 1 1 O 1 O 1 OO 1 OOO 1 O 1 1 1 O. To synchronize with a frame of this standard, eight times are available this sequence of chips and then, there are two symbols (expressed in hexadecimal first the 7 and then the A, from now 7A) that
    20 indicate the frame start delimiter (SFO). When talking about synchronization with this standard, it must be taken into account that there are several levels of synchronization. In this case, as mentioned, it is convenient to sample the signal at the end of each chip (to see only phase differences of _90 ° and 90 °) And therefore, an objective during the preamble is to find the end of
    25 each chip. This is called chip synchronization. On the other hand, to be able to decode the symbols properly we will have to find the beginning of the symbols and thus group the 32 corresponding chips. This procedure is called symbol synchronization. Finally, once the receiver is synchronized at these two levels, the frame synchronization is done simply by waiting for the
    30 consecutive 7 A symbols that correspond to the SFO. From this moment the useful data of the package is extracted from the symbols that make up the rest of the package. This synchronization method uses an instantaneous phase detector, which samples the phase of each chip once. From these phases, the phase difference between consecutive chips is calculated, so that their value is mapped in the range of -180 ° to 180 °.
    35 These phase differences constitute the input of a filter with two coefficient vectors, the (q) and the (i).
    The vector (q) is used to obtain information on the synchronization of the symbol and the vector
    (i) for chip synchronization. Both the vectors of filter coefficients and the difference vector of received phases have a length of N, a multiple of 32. With the filter output (Q) the symbol synchronization moment is decided since a maximum is obtained when the symbols of the preamble "fit" with the vector (q), regardless of chip offset. To decide this synchronization moment, the value of the filter output (Q) is compared with a threshold for each new phase difference received. Once the threshold is exceeded, the symbol synchronization ends. In this position, K, the value of the filter output of (1) is taken and the offset value, delta, with respect to the end of the chip is calculated. From the previous operations, the chip and symbol synchronization is performed. The chips are decoded by assigning an 1 to the positive phases and an O. From this chip decoding, and their grouping into groups of 32 from the K position, the received symbols are decoded and the arrival of the chip is expected. SFD frame start delimiter. Upon receipt, the synchronization process is completed. If the SFD wait exceeds the duration of the preamble, the synchronization process is restarted.
    The present invention consists of the following essential parts schematized in Figure 1: a system (1) with an input signal (3), from which samples of its instantaneous phase (2) are taken, sampled once per chip by means of the phase detector
    (4) in an instant that can be modified by the control signals (12) and (13). From phase (2), the phase difference (5) between two consecutive phases (the current minus the previous one) is calculated using a phase differential decoder (6). This phase difference (5) enters the main block of the synchronizer. the filter (7), where the outputs (a) (8) and (1) (9) are calculated in parallel from the coefficient vectors (q) and (i) (shown in detail in Figure 2) . With the result of the output (Q) (8) it is decided whether there is symbol synchronization by comparing it, by means of the comparator (10), with a threshold (11). The result of the comparison is the control signal (12), whose activation indicates that the symbol synchronization has been achieved. Once this threshold is exceeded, at time K, the control signal (12) allows, from the filter output (1) (9), to calculate the displacement, delta (13), between the current sampling time K and the desired one in chip synchronization using the equation implemented in block (14):
    delta = Tx (1 _ (I) K)
    2 Imax
    where Tx is the chip period, (I) K is the filter output (1) at the instant K and Imax is the maximum value of the output (1) when reception occurs in an ideal situation (with chip synchronism and absence of noise). If the threshold (11) is also considered, block (14) implements the equation with correction:
    delta = Tx (1 _ ~) 2 to Imal (5 where a (which can take values between O and 1) is the correction factor on the maximum value lmax of the filter output (1). The delta offset (13) , together with the control signal (12), it allows chip synchronization, delaying the sampling time of the phase detector (4) a delta time.10 On the other hand, from the phase difference (5) it is determined the value of the chip received
    (15) by means of the chip decoder (1 6), which assigns value '1' if the phase difference is positive and 'O' if it is negative. The chips (15) constitute the input of the symbol decoder (17), which uses the control signal (12) to correctly group the blocks of 32 chips that constitute the received symbols (18).
    15 The symbols (18) constitute the input of the SFD frame start detector (19), which when it detects this frame start (formed by symbols 7 A) activates the control signal (20) that allows the symbols ( 18) after the start of the frame they are received by the data receiver block (21). Note that the activation of (20) involves the completion of synchronization at all levels: chip, symbol and frame.
    20 Figure 2 shows the detail of the filter (7). The phase differences (5) are entered in a shift register (23) of length N, a multiple of 32. To obtain the output of the filter (Q) (8), the results of multiplying each of the phases of this shift register by a coefficient. The grouping of
    25 these coefficients in a vector constitute the vector of coefficients (q) (25). To obtain the filter output (1) (9), the results of multiplying each phase of this shift register by a coefficient are added together. The grouping of these coefficients into a vector constitutes the vector of coefficients (i) (24). The coefficients of the vectors (q) and (i) depend on the preamble with which we want
    30 synchronize, and take value O, 'c' or '-c', being usual c = 1. The value of 'c' determines the threshold (11), which being variable is bounded by the maximum value that the output (Q) can take under ideal conditions (chip synchronism and no noise).
     22-1 2-2016
    BRIEF DESCRIPTION OF THE DRAWINGS
    To complement the description that is being made and in order to help abetter understanding of the features of the invention, is accompanied as part5 member of said description, a set of drawings where illustrative andnon-limiting, the following has been represented:
    Figure 1.- Shows a block diagram of the system that performs the procedure object of the present invention.
    10 Figure 2.- Shows in detail the filter (5) with two outputs (O) e (1) consisting of phase samples that are multiplied by the coefficient vectors (q) and (i). Figure 3.- Shows the details of the preferred embodiment.
    15 PREFERRED EMBODIMENT OF THE INVENTION
    The preferred embodiment is described in Figure 3. The system is formed by a phase receiver, for example, the [ES 2 554 992 82] super-regenerative receiver (26) that already provides a phase difference (5) of the signal MSK (3) sampled. Note that the receiver (26) includes the phase detector (4) and the differential decoder (6) of Figure 1. This phase difference (5) is quantified at 360 µM intervals. In this embodiment the intervals are 18 ° since M = 20. The intervals are coded in an orderly manner starting at -10 (180 °) and ending at 9 (180 ° -18 ° = 162 °), passing by -5 (_90 °) and 5 (90 °). The phase difference (5) constitutes the input of the filter 25 (7), which stores this input in a shift register of length N, N being a multiple of the number of chips, 32, which form a symbol. The outputs (O) (8) and (1)
    (9) of this filter are calculated from the phases of this shift register andof the vectors of coefficients (q) and (i).Vectors (q) and (i) are obtained by repeating vectors (qO) and (iO) Ns times
    30 following,
    qO = [O 1 O O 1 O -1 O 1 1 0-1 -1 -1 O 1 O O O O O -1 O O -1 -1 O O O 1 1 O)andiO = [1 0-11 0-1 01 00-100010-11-11-101-1001-11 00-1)
    where Ns can take integer values from 1 to 8 and in the preferred embodiment it is chosen Ns = 7 (which is equivalent to N = 7x32 = 224). The objective is to achieve symbol synchronization by receiving only 7 consecutive zero symbols, so
    that there is enough time (a symbol) to execute chip synchronization before receiving the start of the frame. These two coefficient vectors, (q) e (i) or (qO) e (iO), are orthogonal to each other. With the result of the output (Q) (8) it is decided whether there is symbol synchronization by comparing it, by means of the comparator (10), with a threshold (11). The result of the comparison is the control signal (12), whose activation indicates that the symbol synchronization has been achieved. Once this threshold is exceeded, at time K, the control signal (12) allows, from the filter output (1) (9), to calculate the displacement, delta (13), between the current sampling time K and the desired one in chip synchronization using the equation implemented in block (14) incorporating the correction:
    delta = TX (l_ ~) 2 to Imax
    where a is the correction factor, which in the preferred embodiment takes the value a = 0.65, Tx is the chip period, (I) K is the filter output (1) at the moment K and Imax is the maximum value of the output (1) when reception occurs in an ideal situation (with chip synchronism and no noise), that is, Imax = (18 * 7) * 5 = 126 * 5 = 630. With the calculated delta value (13) and the symbol synchronization indicator (12), the receiver's sampling time is actuated, indirectly through the generator (27) of the quench signal (28) which is the one that controls The sampling time. By delaying the quench signal for a delta time, the sampling time is at the end of the chip, achieving chip synchronization. On the other hand, from the phase difference (5) the value of the received chip is determined
    (15) by means of the chip decoder (16), which assigns value '1' if the phase difference is positive and 'O' if it is negative. The chips (15) constitute the input of the symbol decoder (17), which uses the control signal (12) to correctly group the blocks of 32 chips that constitute the received symbols (18). The symbols (18) constitute the input of the SFD frame start detector (19), which when it detects this frame start (formed by symbols 7 A) activates the control signal (20) that allows the symbols (18 ) after the start of the frame, they are received by the data receiver block (21), which is part of the MAC layer, which is responsible, among other functions, for calculating the end of the frame and activating the reset control signal ( 22) which restarts synchronization. Note that the activation of (20) involves the completion of synchronization at all levels: chip, symbol and frame.
    权利要求:
    Claims (10)
    [1]
    one. Procedure for receiving data packets according to the IEEE standard
    [802]
    802.15.4, in particular packets that use OQPSK modulation with a
    5 shaping pulse whose shape is half sine cycle (MSK) in the 2.45 band
    GHz, and specifically the synchronization procedure of these packets where
    The concept of synchronization includes chip synchronization, the
    symbol synchronization and frame synchronization characterized by the fact
    of what,
    10 a) a front-end provides a phase sample per chip,
    b) the phase difference between the two chip phase samples is calculated
    consecutive
    c) the phase difference is processed by a filter (Q) whose coefficients are
    represented by a vector (q),
    fifteen d) the phase difference is also processed by a filter (1) whose coefficients
    are represented by a vector (i),
    e) the values of the vector (q) are such that the output of the filter (a) provides
    information for symbol synchronization, regardless of
    possible chip desynchronization,
    twenty f) the values of the coefficients of (i) are such that the filter output (1)
    provides chip sync information,
    g) when the output of (Q) exceeds a threshold, synchronization has been achieved
    of symbol,
    h) at the same time that symbol synchronization has been achieved,
    25 from the value of the filter output (1) the correction, delta, is calculated that the
    front-end must do about the instant of sampling to get the
    chip sync,
    i) once the symbol and chip synchronization have been achieved, they are discarded
    the successive symbols received until the reception of the symbols that
    30 correspond to the beginning of the frame (SFD), at which time the
    frame synchronization,
    j) after getting the symbol, chip and frame synchronism, the data
    Package tools are extracted from the symbols that make up the rest of the package.
    [2]
    2. Method according to claim 1, characterized in that the vectors (q) and
    35 (i) they are orthogonal between them.
    [3]
    3. Method according to claim 2, characterized in that the coefficients of the vectors (q) and (i) are obtained by repeating the vectors qO = [O 1 OO 1 O -10110-1-1-10100000-100-1- Ns times repeating 100011 O) eiO = [1 0-11 0-1 01 00100 O 1 0-1 1 -1 1 -1 O 1 -1 O01 -1 10 O -1] respectively.
    Method according to claim 1, characterized in that in the calculation of the correction, delta, the threshold is taken into account.
    [5]
    5. Method according to claim 1, characterized in that the phase differences are mapped in the range of -180 ° to 180 °.
    [6]
    Method according to claim 1, characterized in that the operations 10 necessary for symbol and chip synchronization are performed in parallel.
    [7]
    7. Circuit for the reception of data packets according to the IEEE 802.15.4 standard, in particular packets that use OOPSK modulation with a shaping pulse whose shape is half sine cycle (MSK) in the 2.45 GHz band, and specifically the synchronization circuit of these packages where the concept
    Synchronization 15 comprises chip synchronization, symbol synchronization and frame synchronization characterized by the fact that, a) a front-end provides a phase sample per chip, b) the phase difference between the samples is calculated two chip phase
    consecutive, 20 c) the phase difference is processed by a filter (O) whose coefficients are represented by a vector (q), d) the phase difference is also processed by a filter (1) whose coefficients are represented by a vector (i), e) the values of the vector (q) are such that the output of the filter (O) provides information for the symbol synchronization, regardless of the possible chip synchronization, f) the values of the coefficients of (i ) are such that the output of the filter (1) provides information on the chip synchronization, g) when the output of (O) exceeds a threshold, the symbol synchronization 30 has been achieved,
    h) at the same time that the symbol synchronization has been achieved, from the value of the filter output (1) the correction is calculated, delta, which the front-end must make over the sampling time to achieve the chip sync,
    35 i) once the symbol and chip synchronization have been achieved, the successive symbols received until the reception of the symbols corresponding to the start of the frame (SFD) are discarded, at which time the frame synchronization is achieved,
    D after achieving the symbol, chip and frame synchronism, the useful data of the package is extracted from the symbols that make up the rest of the package.
    Circuit according to claim 7, characterized in that the vectors (q) and (i) are orthogonal to each other.
    [9]
    9. Circuit according to claim 8, characterized in that the coefficients of the vectors (q) and (i) are obtained by repeating the vectors qO = [O 1 OO 1 0-1 O 1 1 O -1 -1 -1 O 1 OOOOO -1 OO -1 -1 OOO 1 1 O) and iO = [1 O -1 1 O -1 O 1 OO -1
    10 O O O 1 0-1 1 -1 1 -1 O 1 -1 O O 1 -1 1 O O -1] respectively.
    [10]
    10. Circuit according to claim 7, characterized in that in the calculation of the correction, delta, the threshold is taken into account.
    [11]
    eleven. Circuit according to claim 7, characterized in that the phase differences are mapped in the range of -180 ° to 180 °.
    A circuit according to claim 7, characterized in that the operations necessary for symbol and chip synchronization are performed in parallel.
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    同族专利:
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    引用文献:
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