Amplification system for telecommunication signals (Machine-translation by Google Translate, not leg

专利摘要:
The present invention relates to a system for the amplification of telecommunication signals (sa), in particular for the amplification of radio, television and/or data signals, comprising an input (in), an output (out), an amplification module (1), a switching module (2), a bypass module (3) and an internal and/or external polarization network (4), which has two operating modes: a first mode of operation in which the signal present at the input (in) is located at the output (out) through the bypass module; and a second operating mode in which the signal present at the input (in) is located at the output (out) amplified through the amplification module. (Machine-translation by Google Translate, not legally binding)
公开号:ES2645521A1
申请号:ES201600474
申请日:2016-06-03
公开日:2017-12-05
发明作者:Gumersindo López Arca；Ana María PELAEZ PEREZ；Jesús Ricart Fernández
申请人:Televes SA；
IPC主号:

专利说明:

 TELECOMMUNICATION SIGNAL AMPLIFICATION SYSTEM DESCRIPTION 5 TECHNICAL SECTOR 10 The present invention relates to a system for the amplification of telecommunication signals, in particular for the amplification of radio, television and / or data signals according to claim number 1 .  BACKGROUND OF THE INVENTION A low noise amplifier (also called LNA, "Low Noise Amplifier") is a critical element in any communication reception system, since it is the first active element of the system 15 after the antenna.  Therefore, to increase the sensitivity of the receiver and reduce the contribution of the LNA to the total system noise, it is necessary to have a low noise figure and a high gain.  However, in environments where the input signal to the receiver is strong, it is not necessary to have such a high gain and higher noise levels are permissible.  It is even desirable not to have any gain to avoid causing saturation effects in the remaining 20 elements of the system, which can degrade the signal as a result of intermodulation originated in the active device.  In the latter case it is desirable that the LNA has a switching system that allows the input signal to pass through without being amplified.  This element is called bypass circuit.  Numerous LNA configurations with Bypass are known.  However, one of the main disadvantages they present is the fact that the Bypass circuit consumes power when activated, as occurs in the circuit described in US 6,977,552.  Another disadvantage is that, as in the circuit described in US 6,930,546, although the bypass circuit does not consume power, it also needs a bias / control voltage to be activated.  This is a disadvantage since it implies that in the Bypass mode, which is a passive mode, an additional external element is needed to control the device.  Although solutions have been proposed to solve the above disadvantages such as that described in EP 1199771, in which the main drawback lies in the limited gain that can be obtained at the output of the amplifier.  This is due to the fact that the maximum gain of the LNA is limited by the isolation between the input and the output of the amplifier that is possible to obtain from the Bypass circuit, this means that the majority of LNA embodiments with Bypass circuit are limited to single stage or moderate gain amplifiers.  EXPLANATION OF THE INVENTION The object of the present invention is a system for the amplification of telecommunication signals, in particular for the amplification of radio, television and / or data signals, with an input and an output, which has two operating modes: a first mode in which said signal, after being amplified, passes to the output and a second mode that allows the passage of a signal present at the input to the output without being amplified.  This objective is achieved with a system as described in the claims.  This system for the amplification of telecommunication signals, in particular for the amplification of radio, television and / or data signals has a plurality of advantages.  In an example according to the invention the system for the amplification of telecommunication signals in particular for the amplification of radio, television and / or data signals, comprises an input, an output, an amplification module configured in such a way that it has two operating modes, a first mode called amplification mode and a second mode called 5 cut mode; a switching module that has two modes of operation, a first mode called signal passing mode and a second mode called isolation mode; a bypass module that has two modes of operation, a first mode called signal passing mode and a second mode called isolation mode and a polarization network that generates from an input voltage between one different control voltage values.  10 The telecommunication signal amplification system has two operating modes that are selectable based on any of the control voltage values.  In the first mode of operation, called amplification mode, the control voltage value (s) are such that the amplification module is in amplification mode, the switching module is in signal step mode and the Bypass module 3 is in isolation mode, and the signals present at the input of the amplification system are amplified through the amplification module and placed at the output of the amplification system.  In the second mode of operation, called the signal step mode, the control voltage value (s) are such that the bypass module is in signal step mode, the switching module is in 20 mode Isolation and signals at the input of the amplification system are not amplified and are placed at the output of the amplification system through the bypass module.  This example has the advantage of having two independent operating modes, amplification and step, selectable by control voltages without the need to physically act on the system (for example with a switch).  This arrangement of the different modules allows high gain values to be obtained in the amplification mode, thanks to the rejection obtained by the bypass module that prevents oscillation effects, due to feedback from the exit to the entrance, at the same time allows obtain very low attenuation values in the signal step mode by having a switching module that, in the step mode, provides a connection between the output of the amplifier module and the system output and, in isolation mode, isolates the output of the amplifier module of the system output.  In another example according to the invention, the amplification system is in signal step mode when any of the control voltage value (s) is zero volts.  This example has the advantage of requiring a lower number of control voltages in the second mode of operation, thereby improving its energy efficiency.  In another example according to the invention, the amplification system is in signal passing mode 40 when the or all control voltage value (s) is (are) zero volts.  This example has the advantage that in the second mode of operation, the power consumption is zero and the control voltages are equal to zero Volts, making it a passive system that does not need an external power supply and additionally does not need to vary The 45 polarization network.  In another example according to the invention, at least one of the modules that make up the amplification system, that is, the amplification module and / or the switching module and / or the bypass module, are constituted by blocks, called blocks of amplification, switching blocks 50 and bypass blocks respectively.  This example has the advantage of making the design of the different amplifier, switching and bypass modules more flexible, in order to meet different global requirements of the amplifier system (such as gain, isolation between input and output or output impedance) simply withvary the number of amplification and / or switching and / or bypass blocks.  In another example according to the invention, the amplification blocks have two modes of operation, a first mode of operation called amplification mode in which the signal is amplified at the input of the block and a second mode of operation called the cut mode in which It is not allowed to pass the signal to the entrance of the block towards its exit.  This example has the advantage that it allows the possibility of adapting the response of each of the amplification blocks (and consequently of the amplification module) to the different modes of operation of the amplifier system, improving the overall performance of the system.  In another example according to the invention, the switching blocks are of a first type called serial switching block or of a second type called parallel switching block, both with a first mode of operation called step mode and a second mode of operation 15 called cut mode  20 This example has the advantage that, having two types of serial and parallel block allows greater flexibility in the design to adjust the electrical properties (insertion and insulation losses respectively) of the switching module to the requirements established.  In another example according to the invention, at least the last switching block of the switching module is a serial type switching block.  This example has the advantage of increasing the isolation between the output of the bypass module and the output of the switching module when it is in isolation mode, improving the performance of the amplification system in its step mode.  In another example according to the invention, the bypass blocks are of a first type called serial bypass block or of a second type called parallel bypass block, both with a first operating mode 30 called step mode and a second operating mode called cut mode  This example has the advantage that, in the signal step mode of the amplification system, a connection between the input and the output of the amplifier system is available, while in isolation mode the input of the amplifier system of the amplifier system is isolated. amplifier system output so that any signal present at the amplifier system input is channeled to the amplifier module input, without loss of performance.  In addition, having two types of block (series and parallel) has the advantage that it allows greater flexibility in the design to adjust the electrical properties (insertion and insulation losses respectively) of the bypass module to the requirements set.  In another example according to the invention, the bypass module contains at least three bypass blocks.  Of these, at least the first and the last bypass block are of the serial type, and at least one other block located between them is of the parallel type.  This example has the advantage of having a bypass module that, in signal passing mode, provides a low insertion loss connection between the input and the output of the amplifier system.  In addition, the bypass module in isolation mode provides high isolation between the input and output of the amplifier system that prevents unwanted effects of feedback 50 when the amplification system is in amplification mode.  In another example according to the invention, each amplification block contains a transistor in PHEMT technology ("Pseudomorphic High e / ecUon mobi / ity transistor") and one or two capacitors, whose operation is controlled by three control voltages generated by the mains network. Polarization.  This example has the advantage that the mode of operation of each amplification block can be controlled through the polarization of the transistor that contains no additional control voltages, which improves the efficiency of the assembly by using the same voltage for the control and the 5 polarization of the transistors.  In another example according to the invention, each series switching block contains three resistors and a transistor in PHEMT ("Pseudomorphic High electron mobility transistor") technology, whose operation is controlled by two control voltages generated by the polarization network.  In the case of a parallel bypass block, each block contains a resistor, a transistor in PHEMT technology ("Pseudomorphic High electron mobility transistor") and a capacitor, whose operation is controlled by a control voltage generated by the polarization network .  This example has the advantage that the mode of operation of each switching block can be controlled through the polarization of the transistor that contains no additional control voltages, which improves the efficiency of the assembly by using the same voltage for the control and polarization of transistors.  In another example according to the invention, the drain and spout terminals of the switching block transistor 20 can be interchanged.  This has the advantage of having greater flexibility in the design of the switching block.  In another example according to the invention, each serial bypass block contains two resistors and a transistor 25 in PHEMT ("Pseudomorphic High electron mobility transistor") technology, whose operation is controlled by two control voltages generated by the polarization network.  In the case of a parallel bypass block, each block contains a resistor, a transistor in PHEMT technology ("Pseudomorphic High electron mobility transistor") and a capacitor, whose operation is controlled by a control voltage generated by the polarization network.  30 35 40 45 This example has the advantage that the operating mode of each bypass block can be controlled through the polarization of the transistor that contains no additional control voltages, which improves the efficiency of the assembly when using the Same voltage for control and polarization of transistors.  In another example according to the invention, the drain and spout terminals of the bypass block transistor can be interchanged.  This has the advantage of having greater flexibility in the bypass block design.  In another example according to the invention, the PHEMT transistors can be of the enhancer or depletion type, so that if the transistor type of the serial switching blocks must be of the same type as that of the parallel bypass blocks , and the transistor type of the parallel switching blocks must be the same type as that of the serial bypass blocks.  This example has the advantage that it is possible to use different types of PHEMT transistors interchangeably.  In another example according to the invention, the amplification system is formed by an input adaptation block of the amplification module, consisting of an inductance, an amplification module containing exactly two amplification blocks an output adaptation block which is a connection line a switching module that contains exactly one serial switching block,5 10 an input decoupling block of the bypass module which is a decoupling capacitor a bypass module containing three bypass blocks, the first and third serial type and the second parallel type and an output decoupling block of the bypass module which is a decoupling capacitor.  This embodiment has the advantage of obtaining a high gain in the amplification mode and low insertion losses in the signal passing mode.  All this with the minimum number of amplification, switching and bypass blocks, in addition to a reduced number of control voltages.  BRIEF DESCRIPTION OF THE DRAWINGS To complement the description of the invention and in order to help a better understanding of the characteristics and advantages, a set of 15 drawings is attached as an integral part of said description, where for illustrative and non-limiting purposes, has represented the following: Figure 1. - General block diagram of the SA amplification system according to the invention Figure 2. - Block diagram of the SA amplification system according to the invention with identification of the blocks that constitute each module 20 Figure 3. -Example of switching module 2 according to the invention Figure 4. -Example of bypass module 3 according to the invention Figure 5. -Example of amplification block BAi according to the invention Figure 6. -Example of BCjS switching block of the serial type according to the invention Figure 7. - Example of a parallel type BCjP switching block according to the invention Figure 8. - Example of a serial type BBkS bypass block according to the invention Figure 9. - Example of parallel type BBkP bypass block according to the invention Figure 10. -Example embodiment according to the invention Figure 11. -Response graph of the embodiment of the amplification system according to claim number 22 PREFERRED EMBODIMENT OF THE INVENTION In view of the aforementioned figures, and in accordance with the numbering adopted, an example of a preferred embodiment of the invention can be observed in them, which includes the parts and elements indicated and described in detail below.  Thus, and as shown in Fig.  1, a possible preferred embodiment of the system for the amplification of telecommunication signals SA, in particular for the amplification of radio, television and / or data signals, essentially comprises the following elements and functional characteristics: An IN input An output OUT, An amplification module 1, with an input 11 and an output 10, which is configured such that it has two modes of operation, a first mode called amplification mode and a second mode called cut mode.  When operating in amplification mode, the amplification module 1 places the signal present at the amplified input 11 at output 10.  When operating in cut mode, amplification module 1 isolates output 10 of amplification module 1 from input 11 of amplification module 1.  50 A switching module 2 with an input 21 and an output 20, which is configured in such a way that it has two modes of operation, a first mode called signal passing mode and a second mode called isolation mode.  When operating in signal step mode, switching module 2 connects output 20 of switching module 2 to input 21 of switching module 2.  When operating in isolation mode, switching module 2 isolates output 20 of switching module 2 from input 21 of switching module 2.  A bypass module 3 with an input 31 and an output 30, and which has two modes of operation, a first mode called signal step mode and a second mode 5 called isolation mode When operating in step mode, the bypass module 3 connect output 30 of bypass module 3 of input 31 of bypass module 3 When operating in isolation mode, bypass module 3 isolates output 30 of bypass module 3 from input 31 of bypass module 3 10 A network of polarization 4 which generates from an input voltage Vp between one and an integer s of control voltage values Vc1,. . .  , You see.  As a possible value of these voltages, that of O volts is included, therefore considering the ground connection as a possible voltage generated by the polarization network 4.  In this preferred embodiment, the telecommunication signal amplification system SA has two operating modes that are selectable based on any of the control voltage values VC1,. . .  , You see generated by the polarization network 4.  In the first mode of operation of this first preferred embodiment, called amplification mode, the control voltage value (s) Vc1,. . .  , You see are such that the amplification module 1 is in amplification mode, the switching module 2 is in signal step mode and the bypass module 3 is in isolation mode, and the signals present at the IN input of the amplification system SA are amplified through amplification module 1 and set to output OUT of amplification system SAo 25 In the second mode of operation of this first preferred embodiment, called signal step mode, the value (s) ) of control voltage Vc1,. . .  You see that the bypass module 3 is in the signal step mode, the switching module 2 is in isolation mode and the signals at the IN input of the amplification system SA are not amplified and are set to the 30 OUT output of the SA amplification system through bypass module 3.  In another embodiment according to the invention, the amplification system SA is in signal step mode when any of the control voltage value (s) Vc1,. . .  , Ves is zero volts.  In another embodiment according to the invention, the amplification system SA is in signal step mode when the or all control voltage value (s) Vc1,. . .  , Ves is (are) zero volts.  Other possible embodiments are those shown in Figure 2.  In them, at least one of the modules that make up the SA amplification system, that is, the amplification module 1 and / or the switching module 2 and / or the bypass module 3, are constituted by blocks.  An amplification module 1 consisting of blocks according to Figure 2 comprises a BAlA input adaptation block of the amplification module 1 having a BAIAI input and a BAIAO output.  This block corresponds, simply from an inductance to a complex adaptation circuit.  a BAOA output adaptation block of the amplification module 2 that has a BAOAI input and a BAOAO output, the BAOAO output constituting the output 10 of the amplification module 1.  This block can correspond, for example, from a connection line to a complex adaptation circuit.  50 An integer between one and n of amplification blocks BA1,. . .  , BAn, each of which has a BA11 input,. . .  , BAnl and a BAlO output,. . .  , BAnO respectively, and whose operation is controlled by one or more control voltages Vc1,. . .  , Vcs generated by the palate network 4.  In this amplification module 1 according to figure 2, the BAIAI input of the BAlA input adaptation block of the amplification module 1 constitutes the input 11 of the amplification module 1, the BAl1 input of the first amplification block BA1 is connected to the BAIAO output of the 5 input adaptation block BAlA of the amplification module 1, the BAiO output of the i-th amplification block (BAi) is connected to the BAi + 11 input of the amplification block i + 1-th BAi + 1 for all value integer of i between 1 and n-1, the BAnO output of the nth BAnO amplification block is connected to the BAOAI input of the BAOA output adaptation block of amplification module 1, 10 the BAOAO output of the adaptation block of BAOA output of the amplification module 1 constitutes the output 10 of the amplification module 1, A switching module 2 consisting of blocks according to figure 2 comprises an integer between 1 and m bl switching oques BC1,. . .  , BCm, each of which has an entry 15 BC11,. . .  , BCml and one output BC10,. . .  , BCmO respectively, and whose operation is controlled by one or more control voltages Vc1,. . .  , Vcs generated by the polarization network 4.  In this switching module 2 according to FIG. 2, the BClI input of the first switching block BC1 constitutes input 21 of the switching module 2, the output BCjO of the switching block j-th BCj is connected to the input (BCj + 11) of the switching block j + 1-th BCj + 1 for any integer value of j between 1 and m-1, and the BCmO output of the last switching block BCm constitutes the output 20 of the switching module 2.  A bypass module 3 consisting of blocks according to figure 2 comprises a BDIB input decoupling block of the bypass module 3 which has a BDIBI input 30 and a BDIBO output.  This input decoupling block may simply consist of a capacitor or a complex decoupling circuit, an integer between 1 and r BB1 bypass blocks,. . .  , BBr that have a BB11 input,. . .  , BBrl and one BB10 output,. . .  , BBrO respectively, and whose operation is controlled by one or more control voltages Vc1,. . .  , Vcs generated by the polarization network 4, 35 a BDOB output decoupling block of the bypass module 3 which has a BDOBI input and a BDOBO output.  This input decoupling block may simply consist of a capacitor or a complex decoupling circuit.  In this bypass module 3 according to figure 2 40 the BDIBI input of the BDIB input decoupling block of the bypass module 3 constitutes input 31 of the bypass module 3, the input BBI1 of the first bypass block BB1 is connected to the output BDIBO of the BDIB input decoupling block of bypass module 3, the BBkO output of the k-th BBk bypass block is connected to the BBk + 11 input of the k + 1-th BBk bypass block 45 for all value integer of k between 1 and rl.  Between these blocks, it is necessary to introduce a capacitor in the case where the control voltages are different, the BBrO output of the last bypass block BBr is connected to the BDOBI input of the BDOB output decoupling block of the bypass module 3, and 50 the BDOBO output of the BDOB output decoupling block of the bypass module 3 constitutes the output 30 of the bypass module 3 In another embodiment of the invention according to Figure 2, the i-th amplification block BBi, for any number integer i between 1 and n has two modes of operation, a first mode ofoperation called amplification mode and a second mode of operation called cut mode.  in the amplification mode, the i-th amplification block BAi and places at its output (BAiO) the 5 signal present at the amplified BAiI input, and in the cut mode, the i-th amplification block BAi places its BAiO output at its output the signal present to the amplified BAiI input, the signal present at the BAil input to the BAiO output 10 not allowing the passage, in this way, and according to another embodiment that is shown in Figure 2, so that the amplification module 1 is in amplification mode of operation, each and every one of the amplification blocks BA1,. . .  , Ban must be in amplification mode.  Alternatively, for the amplification module 1 to be in the cutting operation mode of the amplification module 1, it will be sufficient that the first amplification block BAl of the amplification blocks 15 BA1,. . .  , BAn is in cut mode.  In another embodiment of the invention also shown in Figure 2, the jth switching block BCj, for any integer value of j between 1 and m, is of a first type called BCjS series switching block, with a BCjSI input and an output BCjSO, or of a second type called 20 parallel switching block BCjP, with an input BCjPI and an output BCjSO.  25 30 A BeS series type switching block, with a BeSI input and a BeSO output, has two modes of operation: a first mode of operation called step mode and a second mode of operation called cut mode.  In a BeS series type switching block in step mode, a connection is established between its BeSO output and its BeSI input.  By connection in this case it is understood to enable a low impedance path, so that it favors the passage of the direct signal between the BeSI input and the BeSO output with respect to any alternative path.  In a BeS series type switching block in cut mode, the BeSO output of the BeSI input is isolated.  It is understood as isolating the fact that preventing the signal present at the BeSI input from passing to the BeSO output.  35 A switching block of the parallel type Bep has two operating modes: a first operating mode called step mode and a second operating mode called cut mode.  In a switching block of parallel type Bep in step mode, a ground path is enabled for the signal present at the Bepl input.  Enabling a path to land is understood in this context as establishing a very low impedance connection between the BePI input and the ground, favoring the passage of the signal with respect to any other alternative path.  In a switching block of parallel type Bep in the cut mode, a connection is established between the BepO output and the Bepl input.  By connection in this case it is understood to enable a low impedance path, so that it favors the passage of the direct signal between the BeSI input and the BeSO output with respect to any alternative path.  In another embodiment according to Figure 2, at least the last switching block Bem of the switching module 3, the last switching block being understood as the one whose Bern output constitutes the output 30 of the switching module 3 is connected, is a block of BeS series type switching.  Thus, and in another embodiment according to Figure 2, so that the switching module 2 isfind in the signal step mode, all switching blocks of the BC1S series,. . .  , BCmS must be in step mode, and all BC1P parallel type switching blocks,. . .  , BCm-1P must be in cut mode.  Otherwise, for the switching module 2 to be in isolation mode, at least one BC1S series switching block,. . .  , BCmS which is closer to the output of the switching module 20 than the parallel type switching block BClP,. . .  , BCm-1P closest to the output of the switching module (20) and which is in step mode, is in cut mode.  10 This is illustrated by an example such as that shown in Figure 3, in which a switching module 2 is shown as described above formed by three switching blocks, two BClS and BC3S series type blocks, and one of the type parallel BC2S.  In order for the switching module 2 to be in signal step mode, it is strictly necessary that the BClS and BC3S series switching blocks are in step mode and that the parallel switching blocks BC2P are in cut mode.  20 25 30 On the other hand, switching module 2 is in isolation mode in the following cases: 1.  If the parallel switching block BC2P is in step mode and the BC3S series switching block is in cut mode.  2.  If the parallel switching block BC2P is in cut mode and at least one of the BC1S series switching blocks, BC3 is in cut mode.  In another embodiment of the invention also shown in Figure 2, the k-th BBk bypass block, for every integer value of k between 1 and r, is of a first type called BBkS series switching block, with a BBkSI input and a BBkSO output, or a second type called a parallel switching block BBkP, with a BBkPI input and a BBkSO output A BBS series bypass block, with a BBSI input and a BBSO output, has two operating modes: a first mode of operation called step mode and a second mode of operation called cut mode.  35 In a BBS series type bypass block in step mode, a connection is established between its BBSO output and its BBSI input.  By connection in this case it is understood to enable a low impedance path, so that it favors the passage of the direct signal between the BBSI input and the BBSO output with respect to any alternative path.  40 In a BBS series bypass block in cut mode, the BBSO output of the BBSI input is isolated.  It is understood as isolating the fact that preventing the signal present at the BBSI input from passing to the BBSO output.  A parallel type BBP bypass block has two modes of operation: a first mode of operation called step mode and a second mode of operation called mode cut-off.  In a parallel type BBP bypass block in step mode, a ground path is enabled for the signal present at the BBPI input.  Enabling a path to land is understood in this context as establishing a very low impedance connection between the BBPI input and the ground, favoring the passage of signal 50 with respect to any other alternative path.  In a parallel type BBP bypass block in cut mode, a connection is established between the BBPO output and the BBPI input.  By connection in this case it is understood to enable a low impedance path, so that it favors the passage of the direct signal between the BBPI input and the BBPO outputRegarding any alternative path.  In another embodiment according to Figure 2, the bypass module 3 contains at least three bypass blocks.  Oe them, at least the first bypass block BB1 and at least the last bypass block BBr are of the first type of bypass block called serial bypass block (BBS), and at least one bypass block (BBk) located between the first bypass block BB1 and the last bypass block BBr is of the second type called parallel bypass block BBP.  The first bypass block BB1 is understood as the one whose input BB11 is connected to the output of the BOIBI input decoupling block of the BOIB bypass module, and the last BBr bypass block is understood as the one whose output is connected to the BOOBI input of the output decoupling block of the BOOB bypass module.  15 Listen to this mode, and in another embodiment according to Figure 2, so that the bypass module 3 is in signal step mode, all 105 BB1S series bypass blocks,. . .  , BBrS must be in step mode, and all 105 bypass blocks of parallel type BB2P,. . .  , BBr-1P must be in cut mode.  In another case, for the bypass module 3 to be in isolation mode, it must be fulfilled that at least one parallel bypass block BB2P,. . .  , BBr-1P is in step mode, at least one BB1S series bypass block,. . .  , BBrS that is closer to the input of the bypass module 31 than the parallel type bypass block BB1P,. . .  , BBr-1P closest to the input of bypass module 31 and which is in step mode, is in cut mode, and that at least one BB1S series bypass block,. . .  , BBrS that is closer to the output of the bypass module 30 than the parallel type bypass block BB1P,. . .  , BBr-1P closest to the output of bypass module 30 and which is in step mode, is in cut mode.  This is illustrated by an example such as that shown in Figure 4, in which a 30 bypass module 3 is shown as described above formed by a BDIB bypass input decoupling block, four BB1S series bypass modules , BB2S, BB4S and BB6S, two parallel bypass blocks BB3P and BB5P, and a BOOB bypass output decoupling block.  In this case, in order for the bypass module 3 to be in signal passing mode, it is strictly necessary that 105 BB1S, BB2S, BB4S and BB6S series bypass blocks be in step mode and that 105 BB3P parallel bypass blocks and BB5P are in cut mode.  40 On the other hand, for the bypass module 3 to be in isolation mode, the following conditions must be met: 1.  If BB3P is in step mode and BB5P is in cut mode, at least BB1S or BB2S must be in cut mode and at least BB4S or BB6S must be cut.  2.  If BB3P is in cut mode and the bypass block BB5P is in step mode, at least BB1S or BB2S or BB4S must be in cut mode and BB6S must be cut.  45 3.  If both BB3P and BBSP are in step mode, at least BB1S or BB2S must be in 50 cut mode and BB6S must be cut.  Figure 5 shows a non-limiting example of the i-th BAi amplification block, where i is an integer between 1 and n.  This block contains a BAil input, a BAiO output, a TRBAi transistor of PHEMT technology whose operating area is controlled by a first control voltage Vcai1, a second control voltage Vcai2 and a third voltage.5 10 15 Vcai3 control and which has a GTRBAi gate terminal, a DTRBAi drain terminal and a STRBAi drain terminal a CBADi drain capacitor connected by one of its terminals to the DTRBAi drain terminal of the TRBAi transistor a capacitor of CBASi dispenser connected by one of its terminals to the STRBAi supplier terminal of the TRBAi transistor, and by another ground terminal.  In this i-th amplification block according to figure 5, the BAil input is the gate terminal of the GTRBAi transistor, the BAiO output is a terminal of the drain capacitor CBADi not connected to the drain terminal DTRBAi of the TRBAi transistor the first control voltage Vcail , the second control voltage Vcai2 and the third control voltage Vcai3 are control voltages Vcl,. . .  , Vcs generated by the polarization network 4, the first control voltage Vcail is applied to the GTRBAi gate terminal of the TRBAi transistor, the second control voltage Vcai2 is applied to the DTRBAi drain terminal of the TRBAi transistor, and the third control voltage Vcai3 is applied to the STRBAi pump terminal of the TRBAi transistor.  20 For this particular embodiment of the ith amplification block BAi, in the mode called amplification, the value of the first control voltage Vcail, the value of the second control voltage Vcai2 and the value of the third control voltage Vca3 are such that the TRBAi transistor of the ith amplification block BAi is polarized in the active zone.  In the cut-off mode, the value of the first control voltage Vcail, the value of the second control voltage Vcai2 and the value of the third control voltage Vca3 are such that the transistor TRBAi of the ith amplification block BAi is It is polarized in the cutting area.  30 35 By way of non-limiting examples of possible voltage values applied: for voltage values Vcail = l, 7V, Vca2 = 4V and Vca3 = 1, the TRBAi transistor is in the active operating zone and the amplification block BAi is is in amplification mode.  for voltage values Vcail = O V, Vca2 = lV and Vca3 = lV, the TRBAi transistor is in the cut-off operating zone and the BAi amplification block is in the cut mode.  for voltage values Vcail = O V, Vca2 = OV and Vca3 = OV, the TRBAi transistor is in the cut-off operating zone, and the BAi amplification block is in the cut mode.  40 If the value of Vca3 is zero Volts, it is possible to dispense with the CBAiS capacitor.  Figure 6 shows a non-limiting example of the j th serial switching block (BCjS), where j is an integer between 1 and m.  This block contains a BCjSI input, a BCjSO output, a TRBCjS transistor of PHEMT technology whose operating area is controlled by a first Vccjsl control voltage and a second Vccjs2 control voltage, and which has a GTRBCjS gate terminal, of a terminal A ATRBCjS and a terminal B BTRBCjS, a resistor called gate RBCjSG connected by one of its terminals to the terminal 50 of gate GTRBCjS of the transistor TRBCjS, a resistor called A RBCjSA connected by one of its terminals to terminal A ATRBCjS of the TRBCjS transistor, and a resistor called B RBCjSB connected by one of its terminals to terminal B BTRBCjS of the TRBCjS transistorIn this j-th series switching block according to figure 6 the BCjSI input of the j-th series switching block BCjS is terminal A of amplifier 5 ATRBCjS the BCSjO output of switching block series BCjS is terminal B of amplifier BTRBCjS the first control voltage Vccjsl and the second control voltage Vccjs2 are control voltages Vcl,. . .  , Vcs generated by the polarization network 4, the first control voltage Vccjsl is applied to a terminal of the 10-gate resistor called RBCjSG not connected to the GTRBCjS gate terminal of the TRBCjS transistor, and the second control voltage Vccjs2 is applied to a resistor terminal called A (RBCjSA) not connected to terminal A ATRBCjS of the TRBCjS transistor and a resistor terminal named B RBCSjB not connected to terminal B BTRBCjS of the TRBCjS transistor.  15 For this specific embodiment of the j th serial switching block (BCjS), in the step mode the value of the first control voltage Vccjsl and the value of the second control voltage Vccjs2 are such that the transistor TRBCjS is polarized at linear zone  In the cut-off mode, the value of the first control voltage Vccjsl and the value of the second voltage of control Vccjs2 are such that the TRBCjS transistor of the jth switching block, of the BCjS series type, is polarized in the zone of cut.  By way of non-limiting examples of possible voltage values applied: 25 for voltage values Vccjsl = 2V and Vccjs2 = lV the TRBCjS transistor is in a linear operating area and the BCjS series switching block is in step mode.  for voltage values Vccjsl = OV and Vccjs2 = lV the TRBCjS transistor is in the cut-off operating zone and the BCjS series switching block is in the cut-off mode.  for voltage values Vccjsl = O V, Vccjs2 = O V the TRBCjS transistor is in the cut-off zone and the BCjS series switching block is in the cut mode.  The ATRBCjS terminal of the TRBCjS transistor may correspond either with the drain terminal of the transistor or with the transistor dispensing terminal, in which case the B BTRBCjS terminal will correspond, respectively, with the transistor dispensing terminal or with the terminal of the TRBCjS transistor drain.  Figure 7 shows a non-limiting example of the j-th parallel switching block BCjP, where j is an integer between 1 and m.  This block contains: a BCjPI input, a BCjPO output, a TRBCP transistor of PHEMT technology whose operating area is controlled by a Vccjpl control voltage, and which has a GTRBCjP gate terminal, an ATRBCjP terminal, and a a BTRBCjP B terminal connected to ground, a so-called RBCjPG resistor connected by one of its terminals to the gate terminal 45 of the GTRBCjP transistor and 50 a CBCjP capacitor connected by one of its terminals to the ATRBCjP terminal of the TRBCjP transistor In this j- The same parallel switching block according to Figure 7, the BCjPI input and the BCjPO output of the parallel switching block BCjP are a terminal of the CBCjP capacitor not connected to the A ATRBCjP terminal of the TRBCjP transistor, the control voltage Vccjpl is one of the control voltages Vcl . . .  , Vcs generated by the polarization network 4, andThe control voltage Vccjpl is applied to a terminal of the so-called gate resistor (RBCjPG) not connected to the GTRBCjP gate terminal of the TRBCjP transistor. For this specific embodiment of the j-th parallel switching block BCjP, in the step 5 mode The control voltage Vccjpl is such that the TRBCjP transistor is polarized in a linear zone.  In the cut-off mode, the value of the control voltage Vccjpl is such that the transistor TRBCjP of the jth switching block, of the parallel type BCjP, is polarized in the cutting zone.  10 By way of non-limiting examples of possible voltage values applied: 15 20 25 30 35 for voltage values Vccjpl = -2V the transistor TRBCjP is in a linear operating area and the parallel switching block BCjP is in cut mode.  for voltage values Vccjpl = OV the transistor TRBCjP is in the cut-off operating zone and the parallel switching block BCjP is in step mode.  The ATRBCjP terminal of the TRBCjP transistor may correspond either with the drain terminal of the transistor or with the transistor dispensing terminal, in which case the B BTRBCjP terminal will correspond, respectively, with the transistor dispensing terminal or with the TRBCjP transistor drain terminal.  Figure 8 shows a non-limiting example of the k-th series bypass block BBkS, where k is an integer between 1 and r.  This block contains a BBkSI input, a BBkSO output, a TRBBkS transistor of PHEMT technology whose operating area is controlled by a first control voltage Vcbksl and a second control voltage Vcbks2, and which has a gate terminal (GTRBBkS) , of a terminal A (ATRBBkS) and of a terminal B (BTRBBkS), a called gate resistor (RBBSkG) connected by one of its terminals to the gate terminal GTRBBkS of the TRBBkS transistor and a resistor called AB RBBkSAB connected by one of its terminals to terminal A ATRBBkS of the TRBBkS transistor and on the other to terminal B BTRBBkS of the TRBBkS transistor In this k-th serial switching block according to figure 8 the BBkSI input is terminal A ATRBBkS of the TRBBkS transistor, the BBkSO output is terminal B BTRBBkS of the TRBBkS transistor, the first control voltage Vcbksl and the second control voltage Vcbks2 are control voltages Vcl,. . .  , Ves generated by the polarization network 4, 40 the first control voltage Vcbksl is applied to a terminal of the so-called gate resistor RBBkSG not connected by one of its terminals to the gate terminal GTRBBkS of the transistor TRBBkS, and the second voltage of control (Vcbks2) is applied to terminal B BTRBBkS of the TRBBkS transistor 45 For this specific embodiment of the k-th BBkS series bypass block, in step mode the value of the first control voltage Vcbksl and the value of the second control voltage Vcbks2 are such that the TRBBkS transistor is polarized in a linear zone.  In the cut mode, the value of the first control voltage Vcbksl and the value of the second voltage of control Vcbks2 are such that the TRBBkS transistor is polarized in the cutting zone.  By way of non-limiting examples of possible voltage values applied: for voltage values Vcbksl = 2V and Vcbks2 = lV the TRBBkS transistor is in a linear operating area and the BBkS series bypass block is in step mode.  5 10 15 20 25 30 35 for voltage values Vcbksl = OV and Vcbks2 = OV the TRBBkS transistor is in the cut-off operating area and the BBkS series bypass block is in step.  for voltage values Vcbksl = OV and Vcbks2 = 3V the TRBBkS transistor is in the cut-off operating zone and the BBkS series bypass block is in the cut mode.  The A ATRBBkS terminal of the TRBBkS transistor may correspond either with the drain terminal of the transistor or with the transistor dispensing terminal, in which case the B BTRBBkS terminal will correspond, respectively, with the transistor dispensing terminal or with the TRBBkS transistor drain terminal.  Figure 9 shows a non-limiting example of the k-th parallel bypass block BBkP, where k is an integer between 1 and r.  This block contains: a BBkPI input, a BBkPO output, a TRBBkP transistor of PHEMT technology whose operating area is controlled by a Vcbkpl control voltage, and which has a GTRBBkP gate terminal, an ATRBBkP terminal, and a terminal B BTRBBkP connected to ground, a gate resistor RBBkPG connected by one of its terminals to the gate terminal GTRBBk of the TRBBk transistor and a CBBkP capacitor connected by one of its terminals to the A ATRBBkP terminal of the TRBBkP transistor In this k-th block of Parallel switching according to Figure 9 the BBkPI input and the BBkPO output of the parallel bypass block BBkP are a terminal of the CBBkP capacitor not connected to the A ATRBBkP terminal of the TRBBkP transistor the control voltage Vcbkpl is a control voltage VC1,. . .  , Vcs generated by the polarization network 4 and the control voltage Vcbkpl is applied to a terminal of the so-called gate resistor RBBkPG not connected to the gate terminal GTRBBkP of the TRBBkP transistor.  For this specific embodiment of the k-th parallel bypass block BBkP, in the step mode the value of the control voltage Vcbkpl is such that the transistor TRBBkP is polarized in a linear zone.  In the cut-off mode the value of the first control voltage Vcbkpl is such that the TRBBkP transistor is polarized in the cutting zone.  By way of non-limiting examples of possible voltage values applied: 40 for voltage values Vcbkpl = lV the transistor TRBBkP is in a linear operating area and the parallel bypass block BBkP is in step mode.  for voltage values Vcbkpl = OV the TRBBkP transistor is in the cut-off operating zone and the parallel bypass block BBkP is in the cut mode.  45 The A ATRBBkP terminal of the TRBBkP transistor can correspond either with the transistor drain terminal or with the transistor dispensing terminal, in which case the B BTRBBkP terminal will correspond, respectively, with the transistor dispensing terminal or the drain terminal of the TRBBkP transistor.  In another embodiment of the SA amplification system, the TRBCjS transistor of the j-th series switching block BCjS shown in Figure 6 is of the enhancer type for any integer value of j between 1 and m, the TRBCjP transistor of the j- The same parallel type switching block BCjP shown in Figure 7 is of the depletion type for any integer value of j between 1 and m, the TRBBkS transistor of the k-th BBkS series type bypass block shown in Figure 8 is of kinddepletion for any integer value of k between 1 and r, and the TRBBkS transistor of the k-th parallel type switching block BBkP shown in Figure 9 is of the enhancer type, for every integer value of k between 1 and r.  5 In another embodiment of the amplification system SA according to Figure 10 the input adaptation block of the amplification module BAlA is an inductance LA1, the BAIAI input of the input adaptation block of the amplification module BAlA being one of the terminals of the inductance LA1, and the BAIAO output of the 10 input adaptation block of the amplification module BAlA another of the inductance terminals LA1, the amplification module 1 contains exactly two amplification blocks BAl and BA2, the output adaptation block of the BAOA amplification module is a connection line switching module 2 contains exactly one BCl switching block of the first type of switching block called the BClS series switching block, within which the resistance of terminal B RBC1SG, the block is suppressed input decoupling of the BDIB bypass module is a CBI input decoupling capacitor, the input being gives BDIBI of the input decoupling block of the BDIB bypass module one of the terminals of the CBI input decoupling capacitor, and the BDIBO output of the input decoupling block of the BDIB bypass module another of the terminals 20 of the decoupling capacitor CBI input module bypass 3 contains a first bypass block BB1, a second bypass block BB2 and a third bypass block BB3, the first block being BBl and the third block BB3 of the first type of bypass block called block of the BB1S and BB3S series bypass, and the second block BB2 being the second type of bypass block called parallel bypass block BB2P and the output decoupling block of the BDOB bypass module is a CBO output decoupling capacitor, being the BDOBI input of the output decoupling block of the BDOB bypass module one of the CBO output decoupling capacitor terminals, and the BDOBO output 30 of the output decoupling block of the module BDOB bypass another of the CBO output decoupling capacitor terminals.  Figure 11 shows the response of the amplification system embodiment according to this embodiment.  As can be seen, the amplification mode achieves a gain greater than 30 dBs at the same time as in the signal step mode it is achieved that the insertion losses are less than 2 dBs.  40 These insertion gain / loss characteristics can be adapted to specific requirements simply by including additional blocks in the amplification and / or switching and / or bypass modules.  LIST OF REFERENCES SA IN 5 OUT 1 11 10 2 10 21 20 3 31 30 15 4 Vdc Vc1,. . .  , Vcs BAlA 20 BAIAI BAIAO LA1 25 BAOA BAOAI BAOAO 30 BA1,. . .  , BAn BA11,. . .  , BAnl BAlO,. . .  , BAnO BAi 35 BAil BAiO TRBAi GTRBAi 40 OTRBAi STRBAi CBAOi 45 CBASi Vcai1, Vcai2, Vcai3 BOIB BOIBI 50 BOIBO CBI BOOB BOOBI Amplifier system Input of the amplifier system Output of amplifier system Amplification module input Output of the amplification module Module switching input Switching module input Switching module output Bypass module Bypass module input Bypass module output Polarization network Input voltage Control voltage Input adaptation block of the amplification module Input adaptation block input of the amplification module Output of the input adaptation block of the amplification module Inductance of the amplification module Output adaptation block of the amplification module Input of the output adaptation block of the amplification module Output of the output adaptation block of the amplification module amplification ion Amplification block 1,. . .  , n Input of amplification block 1,. . .  , n Output of amplification block 1,. . .  , n th amplification block Input of the ith amplification block Output of the ith amplification block Transistor of the ith amplification block Transistor gate terminal of the ith amplification block Transistor drain terminal of the i-th amplification block Transistor dispenser terminal of the ith-amplification block Drain condenser of the ith amplification block Supplier condenser of the ith amplification block Control voltage of the operating zone of the transistor TRBAi of the i-th amplification block Input decoupling block of the bypass module Input of the input decoupling block of the bypass module Output of the input decoupling block of the bypass module Input decoupling capacitor of the bypass module Disconnecting block of bypass module output of the bypass module Input of the output decoupling block of the bypass module5 10 BDOBO CBO BCl,. . .  , BCm BCll,. . .  , BCml BClO,. . .  , BCmO BCj BCjI BCjO BCS BCSI BCSO BCjS 15 BCjSI BCjSO TRBCjS GTRBCjS 20 ATRBCjS BTRBCjS RBCjSG 25 RBCjSA RBCjSB 30 Vccjsl, Vccjs2, Vccjs3 BCP BCPI 35 BCPO BCjPBCj PBCJPJ BCJ BCJ BCJPJJPJJPJJPJPJJJPJJPJJPJJJPJPJPJJJPJPJJJPJG . .  , BBr BBll,. . .  , BBrl Output of the output decoupling block of the bypass module Output decoupling capacitor of the bypass module Switching block l,. . .  , m Switching block input l,. . .  , m Switching block output l,. . .  , m J th control block J th control block input J th control block output Serial type switching block Generic series switching block input Serial type switching block block j -th switching block, serial type Input of the jth switching block, serial type Output of the jth switching block, serial type Transistor of the jth switching block, serial type Transistor gate terminal of the jth switching block, serial type Terminal A of the transistor of the jth switching block, serial type Terminal B of the transistor of the jth switching block, serial type Door resistance of the jth block of switching, serial type Terminal resistance A of the jth switching block, serial type Terminal resistance B of the jth switching block, serial type Operating zone control voltages TRBCjS transistor ionization of the jth switching block, serial type Generic switching block, parallel type Switching block input, parallel type Switching block output, parallel type j-th switching block, type parallel Input of the jth switching block, parallel type Output of the jth switching block, parallel type Transistor of the jth switching block, parallel type Transistor gate terminal of the jth switching block, parallel type Transistor terminal A of the jth switching block, parallel type Transistor terminal B of the jth switching block, parallel type Gate resistance of the jth switching block, parallel type J capacitor -th switching block, type Control voltage of the operating area of the TRBCjP transistor of the j-switching block, parallel type Bypass block l. . .  , r Bypass block input l,. . .  rBBlO,. . .  , BBrO BBk BBkl BBkO 5 BBkS BBkSI BBkSO TRBBkS 10 GTRBBkS ATRBBkS series BTRBBkS 15 series RBBkSG RBBSkSAB BBkP 20 BBkPI BBkPO TRBBkP GTRBBkP ATRBBkP 25 BTRBBP RBBP parallel block 30, RBBP parallel block RBBBP block RBBBP parallel block . .  , r K-th bypass block Input of the k-th bypass block Output of the k-th bypass block k-th serial bypass block, serial type Input of the k-th bypass block, serial type Output of the k- th bypass block, serial type Transistor of the k-th bypass block, serial type Door terminal of the transistor of the k-th bypass block, serial type Terminal A of the transistor of the k-th bypass block, Type B terminal of the k-th bypass block, Type Door resistance of the k-th bypass block, series type AB resistance of the k-th bypass block, series type K-th bypass block, parallel type Input of the k-th bypass block, of the parallel type Output of the k-th bypass block, of the parallel type Transistor of the k-th bypass block, of the parallel type Transistor gate of parallel bypass block Terminal A of the transistor of the k-th bypass block, parallel type Terminal B of the t k-th bypass block ransistor, parallel type Door resistance of the k-th bypass block, type Condenser of the k-th bypass block, parallel type 

权利要求:
Claims (1)
[1]
5 10 15 20 25 30 35 40 45 50 CLAIMS 1. Telecommunication signal amplification system (SA), in particular for the amplification of radio, television and / or data signals, comprising an input (IN) an output ( OUT) An amplification module (1) with an input (11) and an output (10), configured in such a way that it has two operating modes, a first mode called amplification mode and a second mode called cut mode. switch (2) with an input (21) and an output (20), configured in such a way that it has two operating modes, a first mode called signal passing mode and a second mode called isolation mode, A bypass module (3) with an input (31) and an output (30),), configured in such a way that it has two operating modes, a first mode called signal passing mode and a second mode called isolation mode, A polarization network (4) that generates from an input voltage (V p) at least one control voltage value (Vc1, ..., Ves) where the amplification module (1) in amplification mode places the signal present at the input at the output (10) of the amplification module (1) (11) of the amplification module (1) amplified the amplification module (1) in cut mode isolates the output (10) of the amplification module (1) from the input (11) of the amplification module (1), the module switch (2) in signal pass mode connects the output (20) of the switch module (2) to the input (21) of the switch module (2), the switch module (2) in isolation mode isolates the output (20) of the switching module (2) of the input (21) of the switching module (2) the bypass module (3) in step mode connects the output (30) of the bypass module (3) to the input (31) of the bypass module (3) the bypass module (3) in isolation mode isolates the output (30) of the bypass module (3) from the input (31) of the bypass module (3) the input ( 11) of the module amplification (1) is connected to the input (31) of the bypass module (3), constituting the input (IN) of the system for the amplification of telecommunication signals (SA), the output (10) of the amplification module (1 ) is connected to the input (21) of the switching module (2), the output (20) of the switching module (2) is connected to the output (30) of the bypass module (3), constituting the output (OUT ) of the system for the amplification of telecommunication signals (SA) characterized in that it has a first operating mode and a second operating mode selectable depending on the value of the at least one control voltage (Vc1, ... Vcs ) where in the first operating mode, called amplification mode, the amplification module (1) is in amplification mode, the switching module (2) is in signal passing mode and the bypass module (3) is in in isolation mode, and the signals at the input (IN) of the amplification (SA) are amplified through the amplification module (1) and put at the output (OUT) of theamplifier system (SA) and in the second operating mode. called signal pass mode. the bypass module (3) is in signal pass mode. the amplification module (1) is in cutoff mode and the switching module (2) is in isolation mode. and the signals at the input (IN) of the amplification system (SA) are not amplified and are put at the output (OUT) of the amplification system (SA) through the bypass module (3) 2. System according to claim number 1 characterized by that the amplifier system (SA) is in signal passing mode in the event that the value of at least one voltage of the at least one control voltage (Vc1 • ... • Vcs) is zero Volts . System according to previous claims characterized in that the amplifier system (SA) is in signal passing mode the second operating mode in the event that all the values of the at least one control voltage (Vc1 • ... • Vcs) are zero Volts. 20 25 30 35 40 45 50 4. System according to previous claims characterized in that the amplification module (1) comprises and / or an input adaptation block (BAlA) of the amplification module (1) that has an input (BAIAI ) and an exit (BAIAO). an output adaptation block (BAOA) of the amplification module (1) that has an input (BAOAI) and an output (BAOAO). at least one amplification block (BA1 • ... • BAn) that has an input (BA11 • ... • BAnl) and an output (BAlO • ... • BAnO). and whose operation is controlled by at least one of the at least one control voltage (Vc1 • ... • Vcs) where the input (BAIAI) of the input adaptation block (BAlA) of the amplification module (1) constitutes the input (11) of the amplification module (1). the input (BAI1) of the first amplification block (BA1) is connected to the output (BAIAO) of the input adaptation block (BAlA) of the amplification module (1). the output (BAiO) of the i-th amplification block (BAi) is connected to the input (BAi + 11) of the i + 1-th amplification block (BAi + 1) for any integer value of i between 1 and nl . the output (BAnO) of the nth amplification block (BAnO) is connected to the input (BAOAI) of the output adaptation block (BAOA) of the amplification module (1). and the output (BAOAO) of the output adaptation block (BAOA) of the amplification module (1) constitutes the output (10) of the amplification module (1). that the switching module (2) comprises at least one switching block (BC1 • ... • BCm) that has an input (BC11 • ... • BCml) and an output (BClO • ... • BCmO). and whose operation is controlled by at least one voltage of the at least one control voltage (Vc1 • ... • Vcs). the input (BClI) of the first switching block (BCl) constitutes the input (21) of the switching module (2).5 10 15 20 25 30 35 40 45 50 and / or the output (BCjO) of the j-th switch block (BCj) is connected to the input (BCj + 11) of the j + 1-th switch block (BCj + 1) for any integer value of j between 1 and m-1, and the output (BCmO) of the last switching block (BCm) constitutes the output (20) of the switching module (2). that the bypass module (3) comprises where an input decoupling block (BDIB) of the bypass module (3) that has an input (BDIBI) and an output (BDIBO), at least one bypass block (BB1 , ..., BBr) that has an input (BB11, ..., BBrl) and an output (BB10, ..., BBrO), and whose operation is controlled by at least one control voltage (Vc1, ..., Vcs), and an output decoupling block (BDOB) of the bypass module (3) that has an input (BDOBI) and an output (BDOBO). the input (BDIBI) of the input decoupling block (BDIB) of the bypass module (3) constitutes the input (31) of the bypass module (3), the input (BB11) of the first bypass block (BB1) is connected to the output (BDIBO) of the input decoupling block (BDIB) of the bypass module (3), the output (BBkO) of the k-th bypass block (BBk) is connected to the input (BBk + 11) of the block k + 1-th bypass (BBk + 1) for every integer value of k between 1 and r-1, the output (BBrO) of the last bypass block (BBr) is connected to the input (BDOBI) of the block of output decoupling (BDOB) of the bypass module (3). and the output (BDOBO) of the output decoupling block (BDOB) of the bypass module (3) constitutes the output (30) of the bypass module (3) 5. System according to claim number 4 characterized in that the i-th block of amplification (BAi) of the at least one amplification block (BA1, .., BAn), for every integer value of i between 1 and n, it can have two operating modes, a first operating mode called amplification mode and a second operating mode called cut mode where in amplification mode, the i-th amplification block (BAi) places the signal present at the amplified input (BAil) at its output (BAiO), and in cut mode, the i- th amplification block (BAi) places at its output (BAiO) the signal present at the amplified input (BAil), not allowing the signal present at the input (BAil) to the output (BAiO) to pass through 6. System according to claim number 5 characterized by and that in the amplification mode of the amplification module n (1), all the amplification blocks of the at least one amplification block (BA1, ..., BAn) are in amplification mode than in the cut mode of the amplification module (1), at least the first block of amplification (BA1) of the at least one amplification block (BA1, ..., BAn) are in cut-off mode 7. System according to claims 4 to 6 characterized by5 10 15 20 25 30 35 40 45 50 and that the j-th switch block (BCj) of the at least one switch block (BC1, ..., BCm) for every integer value of j between 1 and m is of a first type called serial switching block (BCjS), with one input (BCjSI) and one output (BCjSO), or of a second type called parallel switching block (BCjP), with one input (BCjPI) and one output ( BCjSO) that the j-th switching block, of serial type (BCjS), of the at least one switching block (BCl, .., BCm), for every integer value of j between 1 and m, has two modes of operation, a first operating mode called step mode and a second operating mode called cut mode where in step mode, a connection is established between the output (BCjSO) of the j-th switching block, of series type (BCjS), and at the input (BCjSI) of the j-th switching block, of the series type (BCjS), and in cut mode, the output (BCjSO) of the j-th b is isolated switching block, of serial type (BCjS), of the input (BCjSI) of the j-th switching block, of serial type (BCjS) than the j-th switching block, of parallel type (BCjP), from the to minus one switching block (BCl, .., BCm), for any integer value of j between 1 and m, has two modes of operation, a first mode of operation called step mode and a second mode of operation called cut mode where in In step mode, a ground path is enabled for the signal present at the input (BCjPI) of the j-th switching block, of parallel type (BCjP), and in cut mode, a connection is established between the output (BCjPO ) of the j-th switching block, of parallel type (BCjP), and the input (BCjPI) of the j-th switching block, of parallel type (BCjP). 8. System according to claim number 7 characterized in that at least the last switching block (BCm) is of the first type of switching block called serial switching block (BCmS) 9. System according to claim number 8 characterized by and that in the signal passing mode of the switching module (2), all the serial-type switching blocks (BClS, ..., BCmS) of the at least one switching block (BC1, ..., BCm) are in mode step, and all the parallel type switching blocks (BC1P, ..., BCm-1P) of the at least one switching block (BC1, ..., BCm) are in cut mode than in the isolation mode of the switch module (2), at least one serial switch block (BC1S, ..., BCmS) of the at least one switch block (BC1, ..., BCm), which is closer to the output of the switch module (20) than the parallel type switch block (BClP, ..., BCm-1P) of the at least one switch block (BC1, ..., BCm) plus close to the output of the switching module (20) and located in the5 10 15 20 step mode, you are in cut mode. 10. System according to claims numbers 4 to 9 characterized in that the k-th bypass block (BBk) of the at least one bypass block (BB1, ..., BBk) for every integer value of k between 1 and r is of a first type called serial switching block (BBkS), with one input (BBkSI) and one output (BBkSO), or of a second type called parallel switching block (BBkP), with one input (BBkPI) and one output ( BBkSO) that the k-th bypass block, of serial type (BBkS), of the at least one bypass block (BB1, .., BBr), for every integer value of k between 1 and r, has two modes of operation, a first operating mode called step mode and a second operating mode called cut mode where in step mode, a connection is established between the output (BBkSO) of the k-th bypass block, serial type (BBkS) and the input (BBkSI) of the k-th bypass block, of serial type (BBkS), and in cut mode, the output (BBkSO) of the k-th is isolated m or bypass block, of series type (BBkS) of the input (BBkSI) of the k-th bypass block, of series type (BBkS) 25 And than the k-th switching block, of parallel type (BBkP), of the at least one switching block (BB1, .., BBr), for every integer value of k between 1 and r, has two modes of operation, a first mode of operation called step mode and a second mode of operation called mode cut where in step mode a ground path is enabled for the signal present at the input (BBkPI) 35 of the k-th switching block, parallel type (BBkP), and in cut mode, a connection is established between the output (BBkPO) of the k-th switching block, of parallel type (BBkP) and input (BBkPI) of the k-th switching block, of parallel type (BBkP) 40 11. System according to claims number 10 characterized in that it contains at least three bypass blocks (BB1, ..., BBr), where at least the first bypass block (BB1) and at least e The last bypass block (BBr) are of the first type of bypass block called serial bypass block (BBkS) and at least one bypass block (BBk) located between the first bypass block (BB1) and the last Bypass block (BBr) is of the second type called parallel bypass block (BBkP) 50 12. System according to claim number 11 characterized in that in the signal passing mode of the bypass module (3), all bypass blocks of the type series (BB1S, ..., BBrS) of the at least one bypass block (BB1, ..., BBr) are in step mode, and all parallel type bypass blocks (BB2P, ..., BBr -1P) of the at least one switching block (BB1, ..., BBr) are in cut mode.5 10 15 that in the isolation mode of the bypass module (3) -at least one parallel type bypass block (BB2P, ..., BBr-1P) of the at least one bypass block (BB1, ... , BBr) is in step mode, -at least one serial bypass block (BB1S, ..., BBrS) of the at least one bypass block (BB1, ..., BBr), which is closer at the input of the bypass module (31) than the parallel type bypass block (BB1P, ..., BBr-1P) of the at least one bypass block (BB1, ..., BBr) closest to the input of the bypass module (31) and which is in step mode, is in cut mode and - at least one serial bypass block (BB1S, ..., BBrS) of at least one bypass block (BB1 , ..., BBr), which is closer to the output of the bypass module (30) than the parallel type bypass block (BB1P, ..., BBr-1P) of the at least one bypass block pass (BB1, ..., BBr) closest to the output of the bypass module (30) and which is in pass mode, is in mo do cut. System according to claims number 4 to 12, characterized in that at least the i-th amplification block (BAi) of the at least one amplification block (BA1, .., BAn), for any integer value of i included between 1 and n contains an input (BAil) an output (BAiO) a transistor (TRBAi) of PHEMT technology whose operating area is controlled by a first control voltage (Vcail), a second control voltage (Vcai2) and a third control voltage (Vcai3) and that has a gate terminal (GTRBAi), a drain terminal (DTRBAi) and a source terminal (STRBAi) a drain capacitor (CBAiD) connected by one of its terminals to the terminal (DTRBAi) of the transistor (TRBAi) 30 a source capacitor (CBAiS) connected by one of its terminals to the source terminal (STRBAi) of the transistor (TRBAi), and by another terminal to ground. where the input (BAil) is the gate terminal of the transistor (GTRBAi) the output (BAiO) is a terminal of the drain capacitor (CBAiD) not connected to the drain terminal (DTRBAi) of the transistor (TRBAi) the first voltage of control (Vcail), the second control voltage (Vcai2) and the third control voltage (Vcai3) are at least the at least one control voltage (Vc1, ..., Ves) generated by the polarization network (4) , the first control voltage (Vcail) is applied to the gate terminal (GTRBAi) of the transistor 40 (TRBAi), the second control voltage (Vcai2) is applied to the drain terminal (DTRBAi) of the transistor (TRBAi) and the third control voltage (Vcai3) is applied to the source terminal (STRBAi) of the transistor (TRBAi). 14. System according to claim 13, characterized in that in the amplification mode of the i-th amplification block (BAi) for any integer value of i between 1 and n, the value of the first control voltage (Vcail), the value of the second control voltage (Vcai2) and the value of the third control voltage (Vcai3) are such that the transistor (TRBAi) of the i-th amplification block (BAi) is polarized in the active zone, and in cut mode of the i-th amplification block (BAi) for every integer value of i between 1 and n, the value of the first control voltage (Vcail), the value of the secondcontrol voltage (Vcai2) and the value of the third control voltage (Vcai3) are such that the transistor (TRBAi) of the i-th amplification block (BAi) is polarized in the cut-off zone. 5 15. System according to claims 7 to 14 characterized in that the first type called serial switching block (BCjS) contains an input (BCjSI), an output (BCjSO), 10 a transistor (TRBCjS) of PHEMT technology whose operating area It is controlled by a first control voltage (Vccjs1) and by a second control voltage (Vccjs2), and it has a gate terminal (GTRBCjS), a terminal A (ATRBCjS) and a terminal B (BTRBCjS), a so-called gate resistor (RBCjSG) connected by one of its terminals to the gate terminal (GTRBCjS) of the transistor (TRBCjS), 20 25 30 35 and 40 45 50 a resistor named A (RBCjSA) connected by one of its terminals to the terminal A (ATRBCjS) of the transistor (TRBCjS) a resistor called B (RBCjSB) connected by one of its terminals to terminal B (BTRBCjS) of the transistor (TRBCjS) where the input (BCjSI) of the j-th series switching block (BCjS ) is the A terminal of the amplifier (ATRBCjS) the s Output (BCSjO) of the series switching block (BCjS) is the B terminal of the amplifier (BTRBCjS) the first control voltage (Vccjs1) and the second control voltage (Vccjs2) are at least the at least one control voltage (Vc1 , ..., Vcs) generated by the bias network (4), the first control voltage (Vccjs1) is applied to a terminal of the so-called gate resistor (RBCjSG) not connected to the gate terminal (GTRBCjS) of the transistor (TRBCjS), and the second control voltage (Vccjs2) is applied to a terminal of the resistor named A (RBCjSA) not connected to the terminal A (ATRBCjS) of the transistor (TRBCjS) and to a terminal of the resistor named B (RBCSjB) not connected to terminal B (BTRBCjS) of transistor (TRBCjS). that the second type called parallel switching block (BCjP) contains an input (BCjPI), an output (BCjPO), a transistor (TRBCjP) of PHEMT technology whose operating area is controlled by a control voltage (Vccjp1), and that It has a gate terminal (GTRBCjP), a terminal A (ATRBCjP), and a terminal B (BTRBCjP) connected to ground, a so-called gate resistor (RBCjPG) connected by one of its terminals to the gate terminal of the transistor (GTRBCjP) and a capacitor (CBCjP) connected by one of its terminals to terminal A (ATRBCjP) of the transistor (TRBCjP) where the input (BCjPI) and the output (BCjPO) of the parallel switching block (BCjP) are a terminal of the capacitor (CBCjP) not connected to terminal A (ATRBCjP) of the transistor (TRBCjP) the control voltage (Vccjp1) is at least the at least one control voltage (Vc1, ..., Vcs) generated by the bias network ( 4) and the control voltage (Vccjp1) is applied to one terminal of the resistor so-called gate signal (RBCjPG) not connected to the gate terminal (GTRBCjP) of the transistor (TRBCjP)5 10 15 20 25 30 35 40 45 50 16. System according to claims 15, characterized in that in the step mode of the j-th switching block, of the series type (BCjS), for any integer value of j between 1 and m, the value of the first control voltage (Vccjsl) and the value of the second control voltage (Vccjs2) are such that the transistor (TRBCjS) of the j-th series-type switching block (BCjS) is polarized in linear zone, which in the cut-off mode of the j-th switching block, of the series type (BCjS), for any integer value of j between 1 and m, the value of the first control voltage (Vccjsl) and the value of the second control voltage (Vccjs2) are such that the transistor (TRBCjS) of the j-th switching block, of the series type (BCjS), is polarized in the cut-off zone, which in the step mode of the j-th switching block , of parallel type (BCjP), the value of the control voltage (Vccjpl) is such that the transistor (TRBCjP) of the j-th bl that of the parallel type switching (BCjP) is polarized in the linear area, and that in the cut-off mode of the j-th switching block, of the parallel type (BCjP), the value of the control voltage (Vccjpl) is such that the transistor (TRBCjP) of the j-th switching block, of the parallel type (BCjP), is polarized in the cut-off zone. 17. System according to claims numbers 15 and 16 characterized by or that the terminal A (ATRBCjS, ATRBCjP) of the transistor (TRBCjS, TRBCjP) of the j-th switching block (BCjS, BCjP) corresponds to the drain terminal of the transistor (TRBCjS, TRBCjP) of the j-th switch block (BCjS, BCjP) and terminal B (BTRBCjS, BTRBCjP) of the transistor (TRBCjS, TRBCjP) of the j-th switch block (BCjS, BCjP) corresponds to the source terminal of the transistor ( TRBCjS, TRBCjP) of the j-th switching block (BCjS, BCjP). that terminal B (BTRBCjS, BTRBCjP) of the transistor (TRBCjS, TRBCjP) of the j-th switch block (BCjS, BCjP) corresponds to the drain terminal of the transistor (TRBCjS, TRBCjP) of the j-th switch block (BCjS, BCjP) and terminal A (ATRBCjS, ATRBCjP) of the transistor (TRBCjS, TRBCjP) of the j-th switch block (BCjS, BCjP) corresponds to the source terminal of the transistor (TRBCjS, TRBCjP) of the j-th switch block ( BCjS, BCjP). 18. System according to claims numbers 10 to 17 characterized in that the first type called serial bypass block (BBkS) contains an input (BBkSI), an output (BBkSO), a transistor (TRBBkS) of PHEMT technology whose operating area is controlled by a first control voltage (Vcbksl) and by a second control voltage (Vcbks2), and which has a gate terminal (GTRBBkS), a terminal A (ATRBBkS) and a terminal B (BTRBBkS), a resistor called gate (RBBSkG) connected by one of its terminals to the gate terminal (GTRBBkS) of the transistor (TRBBkS) and a resistor called AB (RBBkSAB) connected by one of its terminals to terminal A (ATRBBkS) of the transistor (TRBBkS) and on the other to terminal B (BTRBBkS) of the transistor (TRBBkS) where the input (BBkSI) is the terminal A (ATRBBkS) of the transistor (TRBBkS), the output (BBkSO) is the terminal B (BTRBBkS) of the transistor (TRBBkS), the first control voltage (Vcbksl) and the second control voltage ntrol (Vcbks2) are at least the at least one control voltage (Vc1, ..., Vcs) generated by the polarization network (4) the first control voltage (Vcbksl) is applied to a terminal of the resistance called de gate (RBBkSG) not connected by one of its terminals to the gate terminal (GTRBBkS) of the transistor (TRBBkS), and5 10 15 20 25 30 35 40 the second control voltage (Vcbks2) is applied to terminal B (BTRBBkS) of the transistor (TRBBkS) that the second type called parallel bypass block (BBkP) contains one input (BBkPI), one output (BBkPO), a PHEMT technology transistor (TRBBkP) whose operating area is controlled by a control voltage (Vcbkp1), and which has a gate terminal (GTRBBkP), a terminal A (ATRBBkP), and a terminal B (BTRBBkP) connected to ground,, a gate resistor (RBBkPG) connected by one of its terminals to the gate terminal (GTRBBkP) of the transistor (TRBBkP) and a capacitor (CBBkP) connected by one of its terminals to terminal A (ATRBBkP) of the transistor (TRBBkP) where the input (BBkPI) and the output (BBkPO) of the parallel bypass block (BBkP) are a terminal of the capacitor (CBBkP) not connected to the terminal A (ATRBBkP) of the transistor (TRBBkP) the control voltage (Vcbkp1) is at least the at least one control voltage (Vc1, ..., Ves) generated by the bias network (4) and the control voltage (Vcbkp1) is applied to a terminal of the so-called gate resistor (RBBkPG) not connected to the gate terminal (GTRBBkP) of the transistor (TRBBkP). 19. System according to claim 18, characterized in that in the step mode of the k-th bypass block, of the series type (BBkS), of the at least one bypass block (BB1, .., BBr), for all integer values of k between 1 and r, the value of the first control voltage (Vcbks1) and the value of the second control voltage (Vcbks2) are such that the transistor (TRBBkS) of the k-th bypass block, series type (BBkS), is polarized in a linear area, and that in cut mode the k-th bypass block, of the series type (BBkS), of at least one bypass block (BB1, .., BBr), to any integer value of k between 1 and r, the value of the first control voltage (Vcbks1) and the value of the second control voltage (Vcbks2) are such that the transistor (TRBBkS) of the k-th switching block, of series type (BBkS), it is polarized in the cut-off zone that in the step mode of the k-th switching block, parallel type (BBkP), of the at least one co-block nmutation (BB1, .., BBr), for every integer value of k between 1 and r, the value of the control voltage (Vcbkp1) is such that the transistor (TRBBkP) of the k-th switching block, of parallel type ( BBkP), is polarized in a linear area, and that in the cut-off mode of the k-th switching block, of parallel type (BBkP), of at least one switching block (BB1, .., BBr), for all Integer value of k between 1 and r, the value of the first control voltage (Vcbkp1) is such that the transistor (TRBBkP) of the k-th switching block, of parallel type (BBkP), is polarized in the cut-off zone 20. System according to claims numbers 13 to 16, characterized in that terminal A of the transistor (ATRBBkS, ATRBBkP) of the k-th bypass block (BBkS, BBkP) corresponds to the drain terminal of the transistor (TRBBkS, TRBBkP) of k -th bypass block (BBkS, BBkP) and terminal B (BTRBBkS, BTRBBkP) of the k-th bypass block (BBkS, BBkP) corresponds to the source terminal of the transistor (TRBBkS, TRBBkP) of the k-th bypass block (BBkS, BBkP) 50 or that the terminal B of the transistor (BTRBBkS, BTRBBkP) of the k-th bypass block (BBkS, BBkP) corresponds to the drain terminal of the transistor (TRBBkS, TRBBkP) of the k-th bypass block (BBkS, BBkP) and terminal A (ATRBBkS, ATRBBkP) of the k-th bypass block (BBkS, BBkP) corresponds to the source terminal of the transistor (TRBBkS, TRBBkP) of the k-th block ofbypass (BBkS, BBkP) 21. System according to claims numbers 18 to 20 characterized in that the transistor (TRBCjS) of the j-th series-type switching block (BCjS) of at least one switching block (BCl, .. . BCm) is of type enhacement, for every integer value of j between 1 and m, that the transistor (TRBCjP) of the j-th parallel type switching block (BCjP) of the at least one switching block (BC1,. .. BCm) is of the depletion type, for every integer value of j between 1 and m, 10 that the transistor (TRBBkS) of the k-th series bypass block (BBkS) of the at least one bypass block (BB1 , ... BBr) is of the depletion type, for every integer value of k between 1 and r, 15 20 25 30 35 40 45 and that the transistor (TRBBkS) of the k-th parallel-type switching block (BBkP) of the at least one switching block (BB1, ... BBr) is of the enhacement type, for any integer value of k between 1 and r, 22.-System according to claims no. 4 to 21 characterized by and that the input adaptation block of the amplification module (BAlA) is an inductance (LA1), the input (BAIAI) of the amplification module input adaptation block (BAlA) being one of the terminals of the inductance (LA1), and the output (BAIAO) of the input adaptation block of the amplification module (BAlA) another of the terminals of the inductance (LA1), which the amplification module (1) contains exactly two amplification blocks (BA1, BA2), that the amplification module output adaptation block (BAOA) is a connecting line that the switching module (2) contains exactly one switching block (BC1) of the first type of commutation block named serial commutation block (BClS), within which the resistance of terminal B (RBC1SG) is suppressed, that the bypass module input decoupling block (BOIB) is an input decoupling capacitor (CBI) , where the entry (BOIBI) of e he bypass module input decoupling block (BOIB) one of the input decoupling capacitor terminals (CBI), and the output (BOIBO) of the bypass module input decoupling block (BOIB) another of the terminals of the input decoupling capacitor (CBI) that the bypass module (3) contains a first bypass block (BB1), a second bypass block (BB2) and a third bypass block (BB3), the first being block (BB1) and the third block (BB3) of the first type of bypass block called serial bypass block (BB1S, BB3S), and the second block (BB2) of the second type of bypass block called bypass block parallel (BB2P) that the bypass module output decoupling block (BOOB) is an output decoupling capacitor (CBO), the input (BOOBI) of the bypass module output decoupling block (BOOB) being one the output decoupling capacitor terminals (CBO), and the output (BOOBO) of the output decoupling block output of the bypass module (BOOB) other of the output decoupling capacitor terminals (CBO).

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同族专利:

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公开号 | 公开日

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ES2645521B2|2018-03-28|

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PL3252948T3|2021-01-25|

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ES2806349T3|2021-02-17|

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PT3252948T|2020-07-29|

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EP3252948A1|2017-12-06|

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EP3252948B1|2020-05-06|

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申请号 | 申请日 | 专利标题

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ES201600474A|ES2645521B2|2016-06-03|2016-06-03|Telecommunication signal amplification system|ES201600474A| ES2645521B2|2016-06-03|2016-06-03|Telecommunication signal amplification system|

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PL17174392T| PL3252948T3|2016-06-03|2017-06-02|Amplification system for telecommunication signals|

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EP17174392.5A| EP3252948B1|2016-06-03|2017-06-02|Amplification system for telecommunication signals|

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ES17174392T| ES2806349T3|2016-06-03|2017-06-02|Telecommunication signal amplification system|

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PT171743925T| PT3252948T|2016-06-03|2017-06-02|Amplification system for telecommunication signals|