• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Voltage regulation of processor sub-domains supplied by the same voltage domain power rail. The voltage to certain logical units inside the voltage domain can be reduced in relation to other logical units of the voltage domain, reducing the waiting time at high power. In one embodiment, a first regulated voltage sub-domain includes at least one execution unit (eu), while a second regulated voltage sub-domain includes at least one texture sampler to provide flexibility in the establishment of the power point - performance of the graphics core beyond the modulation of the active eu count through a control (control by gate) of power domain. In some embodiments, a sub-domain voltage is regulated by a dldo on board for fast voltage switching. The clock frequency and the sub-domain voltage can be switched faster than the voltage of the voltage domain supply rail, allowing granulated power management in a finer way that can be sensitive to the demand of eu workload. . (Machine-translation by Google Translate, not legally binding)
    公开号:ES2540651A2
    申请号:ES201431706
    申请日:2014-11-19
    公开日:2015-07-10
    发明作者:Subramaniam Maiyuran；Muhammad M. Khellah；James W. Tschanz
    申请人:Intel Corp；
    IPC主号:
    专利说明:

    image 1
    image2
    image3
    image4
    image5
    image6
    image7
    image8
    image9
    image10
    image11
    image12
    image13
    image14
    image15
    image16
    image17
    image18
    image19
    image20
    image21
    image22
    image23
    image24
    image25
    image26
    image27
    image28
    image29
    image30
    image31
    image32
    image33
    image34
    权利要求:
    Claims (1)
    [1]
    image 1
    image2
    image3
    image4
    image5
    image6
    image7
    类似技术:
    公开号 | 公开日 | 专利标题
    ES2540651A2|2015-07-10|Graph processor sub-domain voltage regulation |
    US9696771B2|2017-07-04|Methods and systems for operating multi-core processors
    GB2506286A|2014-03-26|Reducing power consumption of uncore circuitry of a processor
    TW200739330A|2007-10-16|Data path controller with integrated power management to manage power consumption of a computing device and its components
    JP2018501569A5|2018-12-13|
    GB2518101A|2015-03-11|Configuring power management functionality in a processor
    MX352450B|2017-11-24|Dynamic management of heterogeneous memory.
    GB201311046D0|2013-08-07|Static random access memory | write assist circuit with leakage suppression and level control
    JP5776124B2|2015-09-09|A strategy for starting clocks in power management.
    TW201612905A|2016-04-01|Storage element, storage device, and signal processing circuit
    TWI621010B|2018-04-11|Integrated circuit device and method of generating power traces
    GB2479452B|2012-07-18|Hardware automatic performance state transitions in system on processor sleep and wake events
    GB2512004A|2014-09-17|Low latency variable transfer network for fine grained parallelism of virtual threads across multiple hardware threads
    TW201342209A|2013-10-16|Migrating threads between asymmetric cores in a multiple core processor
    JP2013250962A5|2016-05-19|
    JP2017528837A|2017-09-28|Dynamic frequency scaling in multiprocessor systems.
    US20130024707A1|2013-01-24|Information processing apparatus and control method
    US9310878B2|2016-04-12|Power gated and voltage biased memory circuit for reducing power
    TW201337527A|2013-09-16|Reconfigurable graphics processor for performance improvement
    GB2509855A|2014-07-16|Rate scalable IO interface with zero stand-by power and fast start-up
    Gupta et al.2012|GNOMO: Greater-than-NOMinal V dd operation for BTI mitigation
    Grenat et al.2016|4.2 Increasing the performance of a 28nm x86-64 microprocessor through system power management
    JP2015165654A5|2018-03-01|Semiconductor device
    BR112018069953A2|2019-02-05|low power voltage level converter circuit
    JP2012173814A5|2014-03-20|Information processing apparatus and control method and program for controlling information processing apparatus
    同族专利:
    公开号 | 公开日
    US20170322617A1|2017-11-09|
    ES2540651B1|2016-05-13|
    US9563263B2|2017-02-07|
    US20150177823A1|2015-06-25|
    US10359834B2|2019-07-23|
    ES2540651R1|2015-08-04|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20070008011A1|2005-06-29|2007-01-11|Paulette Thurston|Distributed power and clock management in a computerized system|
    CN103959196A|2011-11-21|2014-07-30|英特尔公司|Reconfigurable graphics processor for performance improvement|
    US20130173933A1|2011-12-29|2013-07-04|Advanced Micro Devices, Inc.|Performance of a power constrained processor|
    KR101422924B1|2012-10-18|2014-08-13|삼성전기주식회사|Low drop-out regulator|
    US9405357B2|2013-04-01|2016-08-02|Advanced Micro Devices, Inc.|Distribution of power gating controls for hierarchical power domains|US10088891B2|2013-09-23|2018-10-02|Cornell University|Multi-core computer processor based on a dynamic core-level power management for enhanced overall power efficiency|
    US10048742B2|2014-01-16|2018-08-14|Mediatek Inc.|Integrated circuit and electronic device|
    US9817470B2|2015-02-25|2017-11-14|Qualcomm Incorporated|Processor power management responsive to a sequence of an instruction stream|
    WO2017049592A1|2015-09-25|2017-03-30|Intel Corporation|Method and apparatus to improve shared memory efficiency|
    US10163557B2|2015-12-17|2018-12-25|Intel Corporation|Helical plated through-hole package inductor|
    US10209767B2|2016-02-02|2019-02-19|Apple Inc.|Power management architecture|
    US10193442B2|2016-02-09|2019-01-29|Faraday Semi, LLC|Chip embedded power converters|
    US10103714B2|2016-03-01|2018-10-16|Qualcomm Incorporated|Adjust voltage for thermal mitigation|
    US10684671B2|2016-05-27|2020-06-16|Qualcomm Incorporated|Adaptively controlling drive strength of multiplexed power from supply power rails in a power multiplexing system to a powered circuit|
    US10423206B2|2016-08-31|2019-09-24|Intel Corporation|Processor to pre-empt voltage ramps for exit latency reductions|
    US10235811B2|2016-12-29|2019-03-19|Intel Corporation|Replicating primitives across multiple viewports|
    US9899922B1|2017-02-13|2018-02-20|Qualcomm Incorporated|Digital sub-regulators|
    US10424107B2|2017-04-01|2019-09-24|Intel Corporation|Hierarchical depth buffer back annotaton|
    US11010953B2|2017-04-21|2021-05-18|Intel Corporation|Dedicated fixed point blending for energy efficiency|
    US10003337B1|2017-05-17|2018-06-19|International Business Machines Corporation|Resonant virtual supply booster for synchronous logic circuits and other circuits with use of on-chip integrated magnetic inductor|
    EP3435192A1|2017-07-28|2019-01-30|NXP USA, Inc.|Ultra low power linear voltage regulator|
    US10178619B1|2017-09-29|2019-01-08|Intel Corporation|Advanced graphics power state management|
    US11011495B2|2018-08-23|2021-05-18|Advanced Micro Devices, Inc.|Multiple-die integrated circuit with integrated voltage regulator|
    US10628910B2|2018-09-24|2020-04-21|Intel Corporation|Vertex shader with primitive replication|
    US10504848B1|2019-02-19|2019-12-10|Faraday Semi, Inc.|Chip embedded integrated voltage regulator|
    US11069624B2|2019-04-17|2021-07-20|Faraday Semi, Inc.|Electrical devices and methods of manufacture|
    US10447269B1|2019-05-08|2019-10-15|Nxp B.V.|Level shifter|
    US10742215B1|2019-05-20|2020-08-11|Nxp B.V.|Circuit to support multiple voltage level input/output|
    US20210303045A1|2020-03-27|2021-09-30|Intel Corporation|System, Apparatus And Method For Dynamic Power State Scaling Of A Voltage Regulator For A Processor|
    US11063516B1|2020-07-29|2021-07-13|Faraday Semi, Inc.|Power converters with bootstrap|
    法律状态:
    2016-05-13| FG2A| Definitive protection|Ref document number: 2540651 Country of ref document: ES Kind code of ref document: B1 Effective date: 20160513 |
    优先权:
    申请号 | 申请日 | 专利标题
    US14/134,598|2013-12-19|
    US14/134,598|US9563263B2|2013-12-19|2013-12-19|Graphics processor sub-domain voltage regulation|
    [返回顶部]