COMPARE AND REPLACE DAT TABLE INPUT

专利摘要:
compare and replace dat table entry. a first and a second operand are compared. if they are equal, the contents of register r1 are stored in the location of the second operand, and the cpu or cpus specified in the configuration is cleared of all tlb table entries of the designated type formed by using the overridden entry in storage, and all the lower-level tlb table entries formed using the clean top-level tlb table entries. a valid dat table entry is replaced with a new entry, and the translation-lookaside buffer (tlb) is purged of any copy of (at least) the single entry in all cpus in the configuration. if the first and second operands are different, the second operand is loaded in place of the first operand. the result of the comparison is indicated by the condition code. a computer program method, system, and product are provided.
公开号:BR112014031436B1
申请号:R112014031436-5
申请日:2012-11-26
公开日:2021-08-10
发明作者:Dan Greiner；Robert Rogers
申请人:International Business Machines Corporation；
IPC主号:

专利说明:

BACKGROUND 1. Technical Field
[0001] The present invention relates, in general, to processing within a computer environment and, in particular, to one or more of comparing and replacing an entry in an address table, clearing buffer entries (temporary storage ) and an instruction to do so. 2. Description of Related Art
[0002] As described in US patent 7284100, INVALIDATING STORAGE, CLEARING BUFFER ENTRIES, AND AN INSTRUCTION THEREFORE, filed May 12, 2003, selected storage units, such as storage segments or storage regions, are invalidated. Invalidation is facilitated by setting invalidation indicators, located in data structure entries corresponding to the storage units to be invalidated. Additionally, buffer entries associated with invalid storage units or other chosen storage units are cleared. An instruction is provided to perform invalidation and/or clearing. Furthermore, buffer entries associated with a particular address space are cleared without any invalidation. This is also accomplished by instruction. The instruction can be implemented in software, hardware, firmware, or some other combination, or it can be emulated. SUMMARY
[0003] In one embodiment, a computer program product to selectively clear a local Translation Lookaside Buffer (TLB) from one processor, or a plurality of Translation Lookaside Buffers from a plurality of processors, is provided. The computer program product includes: computer readable storage medium with program code incorporated therein, the program code readable by a computer processor for executing a method. The method includes determining, by the processor, an operational code of a machine-executable instruction to be executed, that the instruction is a comparison and replacement of the DAT input instruction; the instruction includes an R1 field and an R2 field; and executing, by the processor, the instructions. The execution includes: obtaining a second original operand from a memory location specified by registers of an odd-even register pair designated by the R2 field of the instruction; comparing a first operand and the obtained original second operand, the first operand contained in an even-numbered register (even Ri) of an even-numbered register pair designated by the Ri field of the instruction; based on the first operand being equal to the original second operand, storing the Ri register settings even in the second operand location as the new second operand and; selectively eliminating all local Translation Lookaside Buffer (TLB) entries corresponding to the formed DAT entries using translation table entries based on a translation table origin designated by a value of the original second operand.
[0004] In another embodiment, a system is provided to execute a Compare and Replace instruction from the DAT Input. The system includes: a memory; and a processor configured to communicate with memory, where the computer system is configured to execute a method. The method includes determining, by the processor, an operational code of a machine-executable instruction to be executed, that the instruction is a comparison and replacement of the DAT input instruction; instructions include a Ri field and an R2 field; and executing, by the processor, the instructions. The execution includes: obtaining a second original operand from a memory location specified by registers of an even-odd register pair designated by the R2 field of the instruction; comparing a first operand and the obtained original second operand, the first operand contained in an even numbered register (even Ri) of an even-odd register pair designated by the Ri field of the instruction; based on the first operand equal to the original second operand, storing the contents of the uniform Ri register in the second operand location as the new second operand and selectively clearing all local entries from the Translation Lookaside Buffer (TLB) corresponding to the entries formed from DAT using translation table entries based on a translation table source designated by a value of the second original operand.
[0005] In another embodiment, a computer-implemented method for comparing a first operand and a second address translation table entry is provided. The method includes determining, by the processor, an operational code of a machine-executable instruction to be executed, that the instruction is a comparison and replacement of the DAT input instruction; the instruction includes an R1 field and an R2 field; and executing, by the processor, the instructions. The execution includes: obtaining a second original operand from a memory location specified by registers of an odd-even register pair designated by the R2 field of the instruction, comparing a first operand and the obtained original second operand, the first operand contained in a register of even number (even Ri) of an even-odd register pair designated by the Ri field of the instruction; based on the first operand equal to the original second operand, storing the contents of the uniform Ri register in the second operand location as the new second operand e; selectively clear all local Translation Lookaside Buffer (TLB) entries corresponding to formed DAT entries using translation table entries based on a translation table source designated by a value of the original second operand.
[0006] Additional features and advantages are realized through the techniques described. Others and aspects are described in detail here and are considered to be included. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Additional objectives, features and advantages are evident from the following detailed description, in conjunction with the accompanying drawings in which: FIGURE 1 represents an embodiment of a computational environment incorporating and using one or more aspects; FIGURE 2 represents an embodiment of other details associated with a controller of FIGURE 1; FIGURE 3 represents an embodiment of a host computer that can emulate another computer; FIGURE 4 represents the instruction image of the COMPARE AND REPLACE DAT TABLE ENTRY instruction, and its operation; FIGURE 5 represents the register operands of the COMPARE AND REPLACE DAT TABLE ENTRY statement; FIGURE 6 represents field M4; e FIGURE 7 represents a computer readable medium. DETAILED DESCRIPTION OF THE PREFERRED MODALITIES
[0008] Computing environments can use virtual storage that is normally held in auxiliary storage to increase the size of available storage. When a virtual storage page is referenced, the virtual address used in the page reference is translated by dynamically translating addresses to a real storage address. If the translation is successful, the virtual storage is valid; otherwise it is invalid. A page of virtual storage is indicated as valid or invalid by an invalid bit in the page table entry, which entry includes an actual storage address, if the page is valid.
[0009] Storage pages can be invalidated one page at a time. For example, in a z/Architecture-based computing environment offered by International Business Machines Corporation, an instruction, referred to as an Invalidate Page Table Entry (IPTE) instruction, is used to invalidate one or more pages of virtual storage. Invalidation includes setting an invalid indicator in a control structure, associated with virtual storage and located in main physical storage, to indicate that a virtual address of a location in virtual storage cannot be translated by dynamic translation of addresses to an address physical main storage, also called the real address. In addition, the instructions are used to clear the internal machine buffer entries associated with the page, entries that can be used during dynamic address translation to prevent access to control structures in main physical storage. For example, in z/Architecture, there are Translation Lookaside Buffers used when translating dynamic addresses from virtual addresses to real addresses. When a storage page is invalidated, the corresponding buffers are also cleared from entries associated with that page.
[0010] There are also instructions that allow purging of all Translation Lookaside Buffers. For example, in z/Architecture, an instruction referred to as a Compare and Swap and Purge (CSP) instruction, purges all Translation Lookaside Buffers entries on all CPUs in the configuration; PURGE TLB erases all TLB entries on the CPU executing the instructions. Translation-Lookaside Buffer
[0011] To improve performance, the dynamic address translation mechanism is usually implemented in such a way that some of the information specified in the region tables, segment tables and page tables is kept in a special buffer, known as translation-lookaside buffer (TLB). The CPU necessarily reacts to a DAT table entry in real or absolute storage only for initial access to that entry. This information can be placed in the TLB and subsequent translations can be performed using the information in the TLB. For consistency of operation, virtual-equal-real translation specified by a real-space designation can also be performed using the information in the TLB. The presence of the TLB affects the translation process in that (1) a modification of the contents of a table entry in real or absolute storage does not necessarily have an immediate effect, if there is, in the translation, (2) the region origin - first-table, region origin - second table region origin- third-table, segment origin - table or real space token origin in an address space control element (ASCE) can select a TLB entry that was formed through ASCE containing a source of equal value even when the two sources are of different types and (3) the comparison against table length in an address space control element can be omitted, if a TLB equivalent of the designated table is used. In a multi-CPU configuration, each CPU has its own TLB.
[0012] Entries in the TLB are not explicitly addressable by the program.
[0013] Information is not necessarily retained in the TLB under all conditions for which such retention is permitted. In addition, information in the TLB can be cleared under additional conditions for those for whom compensation is mandatory. TLB Structure
[0014] The description of the logical structure of TLB covers implementation by all systems that function as defined by z/Architecture. TLB entries are considered to be of six types: TLB region first table entries, TLB region second table entries, TLB region third table entries (collectively called TLB region guide entries) , TLB segment table entries, TLB page table entries, and TLB real space entries. A TLB region table entry, TLB segment table entry, or TLB page table entry is considered to contain within it the information obtained from the table entry in real or absolute storage and the attributes used to obtain these storage information. A real space TLB entry is considered to contain an actual page frame address and the real space token source and the region, segment, and page indexes used to form the entry.
[0015] Any applicable TLB region table entries, the TLB segment table entry and the TLB page table entry can be incorporated into a single entry called the TLB composite table entry. Similarly, an implementation can combine any contiguous subset of table levels. When this happens, the intermediate table origins, offsets, and lengths do not need to be buffered.
[0016] It is possible to form an equivalent of the combined region and segment table entry (CRSTE), described in earlier versions of the architecture, which maps a table origin, region index, segment index, and common segment bit to an address absolute frame-segment or page table origin (and other designated fields).
[0017] The token origin in a TLB real-space entry is indistinguishable from the table origin in a TLB composite region or segment table entry. TLB, the conditions under which TLB information can be used for address translation and how changes to the translation tables affect the translation process. Formation of TLB entries
[0018] The formation of TLB region table entries, TLB segment table entries, and TLB page table entries from table entries in real or absolute storage and the effect of any manipulation of the contents of the table entries stored by the program depend on whether the entries in storage are attached to a specific CPU and whether the entries are valid.
[0019] The attached state of a table entry denotes that the CPU to which it is attached can attempt to use the table entry for implicit address translation, except that a table entry for the main or home address space can be attached , even when the CPU is not sought from any of those spaces. A table entry can be attached to more than one CPU at a time.
[0020] The valid state of a table entry indicates that the defined region, region, segment, or page associated with the table entry is available. An input is valid when the bad region, bad segment, or bad page bit in the input is zero.
[0021] A region table entry, segment table entry or page table entry can be placed in the TLB whenever the entry is appended and valid and would not cause a translation specification exception if used for translation.
[0022] The region table entries, if any, and the segment table entry, if any, used to translate a virtual address are called the translation path. The top-level table entry in a translation path is appended when it is inside a table designed by an appended address space control element (ASCE). "Inside a table" means as determined by the source and length fields in the ASCE. An ASCE is an attached ASCE when all of the following conditions are met:1. Current PSW specifies DAT enabled. 2. The current PSW does not contain errors that would cause an initial specification exception to be recognized. The ASCE meets the requirements in a, b, c, or d below.a The ASCE is the primary ASCE in register 1.b The ASCE is the minor ASCE in control register 7 and any of the following requirements are met:• The CPU is in secondary space mode or access register mode.• The CPU is in primary space mode, and the secondary space control, bit 37 of control register 0, is one.• The M4 operand of LOAD PAGE TABLE ENTRY ADDRESS explicitly allows access to secondary space or explicitly allows access-record translation.• Operator access-control operator (OAC) of MOVE WITH OPTIONAL SPECIFICATIONS explicitly allows access to economic space or explicitly allows access-translation. record.
[0023] For a further explanation of the term "explicitly permits" used in the above two items, see the programming note below. , and any of the following requirements are met:• The CPU is in access record mode.• The LOAD PAGE TABLE ENTRY ADDRESS field M4 explicitly allows access record translation to be performed. • The MOVE WITH OPTIONAL SPECIFICATIONS Operand OAC explicitly allows access record translation to be performed.d The ASCE is the HOME ASCE in record control 13.
[0024] Regardless of whether DAT is on or off, an ASCE is also an ASCE append when the current PSW does not contain errors that would cause an early specification exception to be recognized and one of the following conditions to be met:• The home ASCE it is considered an ASCE attach when a monitor event count operation occurs.
[0025] Each of the remaining table entries in a translation path is appended when it is within the table designated by a valid next top level appended entry that would not cause a translation specification exception if used for translation or by an entry Usable TLB from the next higher level. "Inside table" means as determined by the source, offset, and length fields in the next highest level entry. A usable TLB entry is explained in the next section.
[0026] A page table entry is appended when it is within the page table designated by a valid appended segment table entry that would not cause a translation specification exception if used for translation or a TLB segment table entry usable.
[0027] A region table entry or segment table entry causes a translation exception - specify whether the table type bits, bits 60 and 61, in the input are inconsistent with the level at which the entry would be encountered when using the translation path in the translation process. A segment table entry also causes a translation specification exception if the private space control bit is one in the address space control element used to select it and the common segment bit is one in the input. When EDAT-2 applies, a region third table entry also causes a translation-specification exception if the private space control bit is one in the address space control element used to select it and the region bit common is one at the entrance. An entry in the page table causes a translation specification exception if bit 52 in the entry is one. When EDAT-1 does not apply, the page table entry also causes a translation and specification exception if bit 55 in the entry is one.
[0028] A TLB real space uses an early specification exception to be acknowledged and any of the following conditions are met: • ASCE home is considered an attached ASCE when a monitor event count operation occurs.
[0029] Each of the remaining table entries in a translation path is appended when it is within the table designated by a valid next top level appended entry that would not cause a translation specification exception, whether used for translation or by a next higher level usable TLB entry. "Inside table" means as determined by the source, offset, and length fields in the next highest level entry. A usable TLB entry is explained in the next section.
[0030] A page table entry is appended when it is within the page table designated by a valid appended segment table entry that would not cause a translation specification exception if used for translation or a valid segment table entry. Usable TLB.
[0031] A region table entry or segment table entry causes a translation-specification exception if the table type bits, bits 60 and 61, in the input are inconsistent with the level at which the entry would be encountered when using the translation path in the translation process. A segment table entry also causes a translation and specification exception if the private space control bit is one in the address space control element used to select it and the common segment bit is one in the input. When EDAT-2 applies, a region third table entry also causes a translation-specification exception if the private space control bit is one in the address space control element used to select it and the bit common region is one at the entrance. An entry in the page table causes a translation specification exception if bit 52 in the entry is one. When EDAT-1 does not apply, a page table entry also causes a translation specification exception if bit 55 in the entry is one.
[0032] Subject to the valid and attached restrictions defined above, the CPU may form TLB entries in anticipation of future storage references or as a result of speculative execution of instructions.Programming Note: In the above list of conditions for an ASCE to be attached, items 3.b and 3.c use the term "explicitly allow ..." as explained below: • LPTEA explicitly allows access to the secondary space when the M4 field is binary 0010. • LPTEA explicitly allows ART to be executed when the field M4 is binary 0001.• Or the MVCOS operand explicitly allows access to the secondary space when bits 8-9 of the OAC of the operand are 10 binary, bit 15 of the OAC is one, and the secondary space control bit 37 of the control register 0, is one.• Or the MVCOS operand explicitly allows ART to be performed when operand OAC bits 8-9 are binary 01 and OAC bit 15 is one.
[0033] The usable state of a TLB entry indicates that the CPU may attempt to use the TLB entry for implicit address translation. A usable TLB entry appends the next low-level table, if any, and can be useful for a particular instance of implicit address translation.
[0034] With reference to a TLB entry, the term "current level" refers to the translation table level (region first table, region second table, region third table, segment table or page table) to from which the TLB entry was formed. Likewise, the "current level index" is that part of the virtual address used as an index on the current level of the translation table.
[0035] A TLB region or segment table entry is in the usable state when all of the following conditions are met:1. Current PSW specifies DAT enabled.2. The current PSW does not contain errors that would cause an initial specification exception to be recognized.3. The TLB entry meets at least one of the following requirements:a The common region bit is one in a TLB region third table entry.b The common segment bit is one in a TLB segment table entry.c O ASCE-table source (ASCETO) field in the TLB entry corresponds to the table source field or token in an append address space control element.d The TLB entry is a region-second-table,region-third entry - table or table segment TLB and the current field - table level - TLB source corresponds to one of the following: • The table source field in an ASCE append that directly designates the current table level (as indicated by the R and DT bits )• The table source field in a next-higher-level appended region table entry• The peer table source field in a next-higher-level usable TLB region table entry
[0036] A TLB region table entry can be used for a particular instance of implicit address translation only when the entry is in the usable state, the current level index field in the TLB entry matches the corresponding virtual address index field being translated, and one of the following conditions is met:1. The ASCE-table source (ASCETO) field in the TLB entry is the table or token source field in the address space control element being used in the translation and the part of the virtual address being translated, which is at left of the current level index matches the corresponding index fields in the TLB.2 entry. The address space control element being used in the translation designates a table of the current level, and the current level table source field in the TLB entry matches the table source in that address space control element.3. The current level table source field in the TLB entry corresponds to the peer table source in the top level table entry or TLB entry that is being used in the translation.4. For a TLB region third table entry, the common region bit is one in the TLB entry and the region first index and region second index fields in the TLB entry match those of the virtual address being translated.
[0037] However, when EDAT-2 applies, the TLB region third table entry is not used if the common region bit is one in the input and the private space control bit is one in the address space control being used in the translation, or this real space control element is a real space designation. In either case, the TLB entry is not used even though the ASCE-table source (ASCETO) field in the entry and the table or token source field in the address space control element match.
[0038] A TLB segment table entry can be used for a specific instance of implicit address translation only when the entry is in the usable state, the segment index field in the TLB entry matches that of the virtual address being translated and the following conditions are met:1. The ASCE-table source (ASCETO) field in the TLB entry matches the table or token source field in the address space control element being used in the translation, and the region index field in the TLB entry matches the of the virtual address being translated.2. The segment table source field in the TLB entry matches the table source field in the address space control element used in the translation and that address space control element is a segment table designation. 3. The segment table source field in the TLB entry matches the segment table source field in the region third table or region TLB entry, being used in the translation.4. The common segment bit is one in the TLB input and the region index field in the TLB input matches that of the virtual address being translated.
[0039] However, the TLB segment table entry is not used if the common segment bit is one in the input and the private space control bit is one in the address space control element being used in the translation or that address space control element is an actual space designation. In either case, the TLB entry is not used even if the ASCE- table source (ASCETO) field in the entry and the table or token source field in the address space control element match.
[0040] A TLB page table entry can be used for a specific instance of implicit address translation only when the page table source field in the input matches the page table source field in the segment table entry or TLB segment table entry being used in the translation and the page index field in the TLB page table entry matches the page index of the virtual address being translated.
[0041] A TLB real space entry can be used for implicit address translation only when the token source field in the TLB entry matches the table or token source field in the address space control element being used in the translation and the -index region index, segment index and page index fields in the TLB entry match those of the virtual address being translated
[0042] The operand addresses of LOAD PAGE-TABLE- ENTRY ADDRESS, LOAD REAL ADDRESS and STORE REAL ADDRESS, and enhanced monitor count array accesses can be translated using TLB content whether DAT is enabled or disabled. However, for LOAD PAGE-TABLE- ENTRY ADDRESS, LOAD REAL ADDRESS, and STORE REAL ADDRESS, TLB entries are still formed only if DAT is enabled.Programming Notes:1. Although the contents of a table entry can be copied to the TLB only when the table entry is appended and valid, the copy can remain in the TLB even when the table entry itself is no longer appended or valid.2. Except when translations are performed as a result of enhanced monitor count operations, no content can be copied to the TLB when DAT is disabled because the table entries at this time are not appended. In particular, the address translation of the operand of LOAD PAGE-TABLE-ENTRY ADDRESS, LOAD REAL ADDRESS and STORE REAL ADDRESS with DAT off does not cause entries to be placed in the TLB. On the other hand, when DAT is on, the information can be copied to the TLB from all translation table entries that can be used for address translation, given the current translation parameters, the setting of the address space control bits and the contents of the address registers. access. TLB loading does not depend on whether the input is used for translation as part of the execution of the current instruction, and that loading can occur when the CPU is in standby. More than one copy of the contents of a table entry can exist in the TLB. For example, some implementations may cause a copy of the contents of a valid table entry to be placed in the TLB for the table source in each address space control element by which the entry is attached.Modification of Translation Tables
[0043] When an invalid appended table entry is made valid and no usable entry for translation of the associated virtual address is in the TLB, the change will take effect no later than the end of the current unit of operation. Likewise, when an unattached and valid table entry is made appended and no usable entry for the associated virtual address is in the TLB, the change will take effect no later than the end of the current unit of operation.
[0044] When a valid, appended table entry is changed and when, before the TLB is removed from entries that qualify for the replacement of that entry, an attempt is made to reference the storage using a virtual address that requires that entry to translation, unpredictable results may occur, in the following extension. The use of the new value can start between instructions or during the execution of an instruction, including the instructions that caused the change. Also, until the TLB is removed from entries that qualify to replace that entry, the TLB can contain both the old and new values, and it is unpredictable whether the old or new value is selected for a given access. If the old and new values of a higher-level table entry are present in the TLB, a lower-level table entry can be taken using one value and placed in the TLB associated with the other value. If the new input value is a value that would cause an exception, the exception may or may not cause an interruption. If an interrupt occurs, instruction result fields may change even though the exception normally causes suppression or abort.
[0045] Entries are removed from the TLB according to the following rules:1. All entries are erased from the TLB by executing PURGE TLB or SET PREFIX and resetting the CPU.2. All entries can be erased from all TLBs in the configuration by performing COMPARE AND SWAP AND PURGE by any of the CPUs in the configuration, depending on a bit in a general register used by the instructions.3. Selected entries are erased from all TLBs in the configuration by executing INVALIDATE DAT TABLE ENTRY or INVALIDATE PAGE TABLE ENTRY by any of the CPUs in the configuration. 4. Some or all TLB entries may be deleted at times other than those required by the previous rules.
[0046] Programming Notes:1. Entries in the TLB can continue to be used for translation after the table entries from which they were formed become unattached or invalid. These TLB entries are not necessarily changed unless they are explicitly dropped from the TLB. A change made to an appended and valid entry or a change made to a table entry that causes the entry to be appended and valid is reflected in the process of translation to the next statement, or before the next statement, unless a TLB entry qualifies for replacement of that table entry. However, a change made to a table entry that causes the entry to become unattached or invalid is not necessarily reflected in the translation process until the TLB is removed from the eligible entries for that table entry's replacement. two. Exceptions associated with dynamic address translation can be established by a pretest for operand accessibility that is executed as part of the instruction execution initiation. Consequently, a region first translation, region second translation, region third translation, segment translation, or page translation may be indicated when a table entry is invalid at the start of execution, even if the instruction has validated the input of the table it uses and the table entry would have appeared valid if the instructions were considered to process the operands one byte at a time. A change made to an attached table entry, except to set the bit to zero, to set the CO bit of a segment or page table entry to one, or to change the rightmost byte of a page table entry , can produce unpredictable results if this entry is used for translation before the TLB is removed from all copies of the contents of that entry. The use of the new value can start between instructions or during the execution of an instruction, including the instructions that caused the change. When an instruction, such as MOVE (MVC), makes a change to an attached table entry, including a change that makes the entry invalid, and subsequently uses the entry for translation, a changed entry is being used without prior clarification of the entry. TLB and the associated unpredictability of result values and exception recognition apply. Handling attached table entries can cause spurious table entry values to be registered in a TLB. For example, if changes are made piecemeal, modification of a valid appended entry may be recorded as a partially updated entry or, if an intermediate value is introduced in the change process, a supposedly invalid entry may appear temporarily valid and may be registered in the TLB. This intermediate value can be introduced if the change is made by an I/O operation that is retried, or if an intermediate value is introduced during the execution of a single statement. As another example, if a segment table entry is changed to designate a different page table and used without clearing the TLB, new page table entries can be fetched and associated with the old page table source. In this case, executing the INVALIDATE PAGE TABLE ENTRY that assigns the new page table source will not necessarily clear the page table entries fetched from the new page table.4. To facilitate the manipulation of page tables, the INVALIDATE PAGE TABLE ENTRY statement is provided. This instruction sets the I bit in a page table entry to one and clears one or more TLBs in the configuration of the entries formed from those table entries as follows:a All TLBs in the configuration are cleared when the local installation removes of TLB is not installed or when the installation is installed and the statement specifies clearing of all TLBs (that is, the local clearing control in the statement is zero). b Only the TLB on the CPU executing the INVALIDATE PAGE TABLE ENTRY statement is cleared when the TLB local cleanup facility is installed and the statement specifies local TLB cleanup only (that is, the local cleanup control in the statement is one).
[0047] The following aspects of TLB operation should be considered when using INVALIDATE PAGE TABLE ENTRY (See also the programming notes for INVALIDATE PAGE TABLE ENTRY.) The INVALIDATE PAGE TABLE ENTRY should be performed before making any changes to an entry. different page table to change the rightmost byte; Otherwise, the selective cleanup portion of INVALIDATE PAGE TABLE ENTRY might not clean up the TLB copies of the entry.b Invalidating all page table entries within a page table through INVALIDATE PAGE TABLE ENTRY does not necessarily clean up the TLB of any segment table entry that designates the page table. When it is desired to invalidate and clear the TLB of a region or segment table entry, the rules in note 5 below must be followed. Likewise, invalidating all lower-level table entries within the segment table or table via INVALIDATE DAT TABLE ENTRY does not necessarily clear the TLB of any top-level table entry that designates the bottom-level table. When it is desired to invalidate and clear the TLB of a top-level table entry, the rules in note 5 below must be followed.c When a large number of page table entries must be invalidated at one time, the overhead involved using COMPARE AND SWAP AND PURGE (one that purges the TLB), INVALIDATE DAT TABLE ENTRY or PURGE TLB and following the rules in note 5 below may be less than issuing the INVALIDATE PAGE TABLE ENTRY for each page table entry .5. The handling of table entries must comply with the following rules. If these rules are met, translation is performed as if the real or absolute storage table entries were always used in the translation process.a A valid table entry must not be changed while it is attached to any CPU and can be used for translation by that CPU, except to (1) invalidate the entry using INVALIDATE PAGE TABLE ENTRY or INVALIDATE DAT TABLE ENTRY, (2) change bits 56-63 of a page table entry, (3) make a change through a COMPARE AND SWAP AND PURGE statement that purges the TLB, or (4) replace an entry using COMPARE AND REPLACE DAT TABLE ENTRY.b When any change is made to a valid or unattached appended table entry other than a bit change 56-63 of a page table entry, each CPU that can have a TLB entry formed from that entry must be taken to purge its TLB after the change occurs and before using that entry for implicit translation by that CPU. (Note that a separate purge is unnecessary if the change is made using COMPARE AND REPLACE DAT TABLE ENTRY, INVALIDATE DAT TABLE ENTRY, INVALIDATE PAGE TABLE ENTRY, or a COMPARE AND SWAP AND PURGE statement that purges TLB). In case the table entry is appended and valid, this rule applies when it is known that a program is not running that may require the entry for translation. c When any change is made to an invalid table entry in order to allow valid intermediate values to appear in the entry, each CPU to which the entry is connected must be caused to purge its TLB after the change occurs and before using the entry to the implicit address translation of the CPU.d When any change is made to a specified offset or length for a table, every CPU that can have a TLB entry formed from a table entry that is no longer within its table must be caused to purge your TLB after the change occurs and before the table is used for implicit translation by that CPU.
[0048] Note that when an invalid page table entry is made valid without inputting intermediate valid values, the TLB does not need to be cleared on a CPU that has no TLB entries formed from that entry. For example, when an invalid region table or segment table entry is made valid without having intermediate valid values, the TLB does not need to be cleared on a CPU that does not have any TLB entries formed from that validated entry and that does not have any no TLB entries formed from entries in a page table appended via that validated entry.
[0049] Performing PURGE TLB, COMPARE AND SWAP AND PURGE or SET PREFIX may have an adverse effect on the performance of some models. The use of these instructions should therefore be minimized in accordance with the above rules.6. The following considerations are in effect when EDAT-1 applies:a When STE format controls and ACCF validity are both one, it is unpredictable whether the CPU inspects the access control bits and the seek protection bit on the input from the segment table or the corresponding 4K byte block storage key for any key-controlled protection check. Therefore, the program must ensure that the access control bits and the seek protection bit in the segment table entry are identical to the respective fields in all 256 storage keys of the building blocks of the 4K segment, before setting the bit. invalid in the STE to zero. Before changing the ACCF validity control, the access control bits or the fetch protection bit in the segment table entry and before changing the access control bits or the search protection bit fetching any of the 256 segment storage keys, the program must first set the invalid bit to one in the segment table entry and clear all entries in all TLBs in the configuration, as described earlier in this section.b. Before setting change-registration to zero in a segment table entry, the program must set the invalid bit to one in the segment table entry and clear all entries in all TLBs in the configuration (for example, using INVALIDATE DAT TABLE ENTRY). Invalidating the table entry is not necessary if the change is made using COMPARE AND REPLACE DAT TABLE ENTRY or a form of COMPARE AND SWAP AND PURGE that cleans up TLB.c. Before setting change-registration to zero in the page table entry, the program must set the invalid bit to one in the page table entry and clear all entries in all TLBs in the configuration (for example, using INVALIDATE PAGE TABLE ENTRY). Invalidating the table entry is not necessary if the change is made using COMPARE AND REPLACE DAT TABLE ENTRY or a form of COMPARE AND SWAP AND PURGE that purges TLB.
[0050] When EDAT-2 applies, the following additional considerations are in effect:[0001] When the RTT ACCF-validity format control are both one, it is unpredictable whether the CPU inspects the access control bits and the fetch protection bit in the third table entry region or in the storage key of the corresponding 4K byte block or any key-controlled protection check. Therefore, the program must ensure that the access control bits and fetch protection bit in the region third table entry are identical to the respective fields in all 524.288 storage keys for the region's 4K byte building blocks before to set the invalid bit in the RTTE to zero. Before changing the ACCF validity control, the access control bits or fetch protection bit in the third region table entry and before changing the access control bits or For access protection on any of the 524288 region storage keys, the program must first set the invalid bit to one in the region third table entry and clear all entries in all TLBs in the configuration, as described earlier in this section. B. Before setting change write cancel to zero in a region third table entry, the program must set the invalid bit to one in the region third table entry and clear all entries in all TLBs in the configuration (for example , using INVALIDATE DAT TABLE ENTRY). Invalidating the table entry is not necessary if the change is made using COMPARE AND REPLACE DAT TABLE ENTRY or a form of COMPARE AND SWAP AND PURGE that clears the TLB. Failure to observe these procedures can lead to unpredictable results, possibly including a delayed access exception machine check or failed to log a change. Optimized DAT installation
[0051] The enhanced-DAT facility 1 may be available on models that implement z/Architecture. When the facility is installed and enabled, DAT translation can produce either an actual page frame address or an absolute segment frame address, determined by the STE format control in the segment table entry. When installation is installed in a configuration, a new bit in control register 0 enables installation. Note: The term EDAT-1 is applied broadly throughout this document to describe the condition when the enhanced DAT 1 installation is installed in the configuration and enabled by control register 0.
[0052] When applying EDAT-1, the following additional function is available in the DAT process:- A DAT protection bit is added to the region table entries, providing similar function to the DAT protection bits in the segment table entries and page.- An STE format control is added to the segment table entry. When the STE format control is zero, DAT proceeds as it is currently defined, except that a change write override in the page table entry indicates whether the change bit setting can be ignored for the page. STE format is one, the segment set entry contains the following:- A segment frame absolute address (instead of a page table source) specifying the absolute storage location of the 1 M-byte block.- Bits and a fetch protection bit that can optionally be used in place of the corresponding bits in the individual storage keys of the segment- A bit that determines the validity of the access control bits and a fetch protection bit in segment table entry - A change write cancel that indicates whether the change bit setting can be overwritten in the segment's individual storage keys. Setup adds PERFORM FRAME MANAGEMENT FUNCTION control statements. Installation includes enhancements or changes to the following control statements: • LOAD PAGE-TABLE-ENTRY ADDRESS • MOVE PAGE • SET STORAGE KEY EXTENDED • TEST PROTECTION Enhanced DAT 2 installationThe enhanced-DAT facility 2 may be available on models that implement z/Architecture . When the installation is installed and enabled, DAT translation can produce an actual page frame address, a segment frame absolute address, or a region frame absolute address, determined by format controls on the region third input (if any ) and the segment table entry (if any). control 0.When applying EDAT-2, the following additional function is available in the DAT process:• EDAT-1 applies• A format control is added to the third region table entry (RTTE). When RTTE format control is zero, DAT proceeds as is the case when EDAT-1 applies.• When RTTE format control is one, the region third table entry also contains the following:• An absolute frame address of region (instead of a segment table source) specifying the absolute storage location of the 2G-byte block.• Access control bits and a fetch protection bit that can optionally be used in place of the corresponding bits in the individual region storage keys• A bit that determines the validity of the access control bits and a fetch protection bit in the region third table entry. A change register override that indicates whether the change bit setting can be bypassed in the individual region storage keys. The enhanced DAT 2 installation adds COMPARE AND REPLACE DAT TABLE entry statements, providing dynamic replacement of valid append DAT table entries and selective pruning of all TLB entries created from the replaced entry. The enhanced DAT 2 feature also includes enhancements or changes to the following control statements: • INVALIDATE DAT TABLE ENTRY • LOAD PAGE-TABLE-ENTRY ADDRESS • MOVE PAGE • PERFORM FRAME MANAGEMENT FUNCTION • TEST PROTECTION When the enhanced DAT 2 installation is installed, Advanced DAT installation 1 is also installed.
[0053] INVALIDATE DAT TABLE ENTRY (IDTE) performs the invalidation and purge operation, selectively dropping the combined TLB region and segment table settings when a segment table entry or entries are invalidated. IDTE also performs the cleanup operation by ASCE.
[0054] During the execution of an IDTE instruction, a specified portion of storage (for example, virtual storage) is invalidated. As examples, a storage segment, which includes a plurality of storage pages, or a storage region, which includes a plurality of storage segments, is selected to be invalidated. Invalidation is facilitated by setting invalidation indicators located in data structure entries corresponding to the storage units to be invalidated. In an additional aspect, buffer entries (for example, Translation Lookaside Buffer entries) associated with storage being invalidated or other storage are erased. Furthermore, in another aspect, entries associated with selected address spaces are cleared from the buffers without affecting the buffer entries for unselected address spaces and without performing invalidation. In one example, a statement, referred to herein as an IBM® z/Architecture Invalidate Dynamic Address Translation (DTE) statement, is used to perform one or more of the above operations.INVALIDATE DAT TABLE ENTRYIDTE R1, R3, R2 [, M4]Note: The term "specified CPU or CPUs" has the following meaning for the scope of TLBs affected by this instruction: • When the local TLB cleaning facility is not installed, or when the unit is installed and the control bit clean local (LC) in field M4 is zero, the term “specified CPU or CPUs” means all CPUs in the configuration.• When TLB removal local installation is installed and the LC bit in field M4 is one, the term "Specified CPU or CPUs" means only the CPU that executes the IDTE instruction (Local CPU). TLBs on all other CPUs in the configuration may not be affected.
[0055] When the ASCE clear option bit, bit 52 of general register R2, is zero, an operation called invalidation and clear operation is performed, as follows. The designated region table entry or segment table entry in storage, or a range of entries starting with the designated entry, is invalidated and the Translation Lookside Buffers on the CPU or CPUs specified in the configuration are cleared (1) all TLB table entries of the designated type formed through the use of the invalid entry or entries in storage and (2) all lower level TLB table entries formed through the use of the cleared top level TLB table entries. Unmarked TLB entries can optionally be limited to entries formed to translate addresses in a specified address space.
[0056] When the ASCE clear option bit is one, an operation called ASCE clear operation is performed as follows. The operation does not effect any invalidation of the DAT table entries in storage, but of course, from the TLBs on all CPUs in the configuration, all region first table entries, region second table entries, third table entries region, segment table entries, and page table entries formed to translate addresses in a specified address space.
[0057] The bits of field M4 are defined as follows: • Reserved: bits 0-1 of field M4 are ignored, but must contain zeros; Otherwise, the program may not work compatibly in the future.• Format Control Summary (FS): When EDAT-2 applies, bit 2 of the M4 field is the Format Control Summary (FS) for the operation of cancellation and cleaning. Bit 2 of field M4 is ignored for clear operation by ASCE and when EDAT-2 does not apply. Format control summary applies when designation type (DT), bits 60-61 of general register Ri, is 00 or 01 binary; When the DT in general register R1 is binary 10 or 11, the format control summary is ignored.• Local Clean Control (LC): When the Local TLB Cleanse Facility is installed, the LC bit, bit 3 of the field M4, controls whether only the TLB on the local CPU is unchecked or whether the TLBs on all CPUs in the configuration are cleared. When the local TLB compensation facility is not installed, bit 3 of field M4 is ignored. Invalidation and Clear Operation When bit 52 of general register R2, the clear by ASCE option bit is zero, the operation of invalidation and cleaning is specified.
[0058] The contents of general register R1 have the format of an address space control element with only the table origin, bits 0-51 and designation type control (DT), bits 60 and 61, used . The table origin designates the DAT table in which one or more entries are to be invalidated, and DT specifies the type of that table. Bits 52-59, 62, and 63 of general register Ri are ignored.
[0059] Bits 0-43 of general register R2 have the format of the region index and segment index of a virtual address. The part of bits 0-43 normally used by the DAT to select an entry in the table type designated by general register R1 is called the effective invalidating index. Bits 60 and 61 of general register R1 specify a table type and an index of effective invalidation as follows: The part of bits 0-43 of general register R2 to the right of the effective invalidation index is ignored.
[0060] The table source in general record R1 and the effective invalidating index designate a DAT table entry to be invalidated. Bits 53-63 of general register R2 are an unsigned binary integer that specifies the number of additional table entries to be invalidated. Therefore, the number of entries to be invalidated is 1-2,048, corresponding to a value of bits 53-63. Bits 44-51 of general register R2 must be zero; Otherwise, a specification exception is recognized.
[0061] If R3 is non-zero, the contents of general register R3 have the format of an address space control element with only the table origin, bits 0-51 and designation control (DT), bits 60 and 61, used. These contents are used to select the TLB entries to be cleared. Bits 52-59, 62 and 63 of general register R3 are ignored. If R3 is zero, the entire contents of general register 0 will be ignored and TLB entries will be erased, regardless of the ASCE used to form them.
[0062] Table origin in general register R1 and effective invalidation index in general register R2 designate a table entry according to the rules in “Lookup in a Table Designated by an Address-Space-Control Element” in "z/ Architecture Principles of Operation," IBM Publication No. SA22-7832-08, Aug 2010", except that a transport of bit position 0 of the resulting address is always ignored and the index is not checked on a table length field. The table origin is treated as a 64-bit address and addition is performed using the rules for 64-bit address arithmetic, regardless of the current addressing mode specified by bits 31 and 32 of the current PSW. The address formed from these two components is a real or absolute address. The invalid bit, bit 58, of this region table or segment table is set to one. During this procedure, the entry is not checked for a format error or whether the source, in the entry, of the next lower level table would cause an addressing exception. The table type field in the input is ignored. If the input is a segment table entry, the common segment bit in the input is ignored. If EDAT-2 applies and the entry is a region third table entry, the region common bit in the entry is ignored.
[0063] All table entry is fetched simultaneously from storage. Afterwards, the byte containing the invalid bit is stored. Entry fetching access is subject to key controlled protection and storage access is subject to key controlled protection and low address protection.
[0064] If bits 53-63 of general register R2 are not all zeros, the invalid bit setting to one in a region table or segment table entry is repeated by adding one to the previously used value of effective index invalidation, and this is done as many times as specified by bits 53-63. A performance of the leftmost bit position of the effective invalidation index is ignored and involved in table occupants in this case. The contents of general register R2 remain unchanged.
[0065] A serialization function is performed before the start of the operation and again after the completion of the operation. As is the case with all serialization operations, this serialization only applies to this CPU; other CPUs are not necessarily serialized.
[0066] After setting an invalid bit to one, this CPU clears the selected entries from its TLB. So, if the local TLB offset facility is not installed or if the facility is installed and the LC bit in the M4 field is zero, that CPU will flag all other CPUs in the configuration to clear the selected entries from their TLBs. Each affected TLB is removed from at least those entries so that all conditions are met: • The effective invalidation index in general register R2 matches the corresponding index in the TLB table entry of the type designated by field DT in bits 60-61 of general register R1. If the model implements a composite TLB entry that includes the index designated by the DT field, the bits to the left of the effective index in general register R2 also match the corresponding bits given in the designated TLB table entry. Note that when multiple table entries are invalidated due to bits 53-63 of general register R2, then the effective invalidating index is incremented, a leftmost bit position of the index is lost, and the region or segment table entries TLB values are cleared for each index value thus obtained. • Field R3 is zero, or the effective invalidation of table origin and assignment fields in general record R3 correspond to table origin and assignment type fields in the element of address space control (ASCE) used to form the TLB table entry.• If the R3 field is zero, the condition described in this step does not apply.• If the invalidated entry in storage designates a lower-level translation table , the lower-level table source in the invalidated entry matches the table source field in the TLB table entry.
[0067] Each affected TLB is also cleared of at least any low-level TLB table entries for which the following conditions are:• The low-level TLB table entry was formed through the use of an invalid entry in storage or by use a top-level TLB table entry, formed by either an invalided entry in storage or a clean TLB entry in this process.• The R3 field is zero, or the table source and designation fields in the R3 general record match the table source and designation fields in the address space control element (ASCE) used to form the low-level TLB table entry. This ASCE can be the one that appended a translation path containing a top-level table entry that appended the lower-level table entry into storage from which the lower-level TLB table entry was formed, or it could be one that made useful a top level table entry, level TLB table entry that appended the lower level table entry into storage from which the lower level TLB table entry was formed. If the R3 field is zero, the condition described in this step does not apply. • If the invalid entry in storage designates a lower-level translation table, the lower-level table source in the invalid entry matches the table source field in the TLB table entry.Programming Notes:1. Setting the format control summary to one may provide better performance on certain models.2. When the designation type (DT), bits 60-61 of general register R1, is 00 binary, the format control summary applies to the segment table entries being invalidated. When the DT in general register R1 is binary 01, the format control summary applies to the region third table entries being invalidated. The program should only set the format control summary to one if it can guarantee that the format control (bit 53 of the table entry) is one in all table entries being invalidated. If the format control summary is set to one, but the format control is not one in all table entries being invalidated, incomplete TLB purge can occur, resulting in unpredictable results from DAT.4. The M4 field of the instruction is considered to be optional, as indicated by the field being enclosed in square brackets [ ] in the assembler syntax. When the M4 field is not specified, the assembler places zeros in this instruction field.
[0068] Storing in region or segment table entry and clearing TLB entries may or may not occur if the bad bit is already one in region or segment table entry.
[0069] When multiple entries are invalidated, the cancellation of TLB entries can be postponed until all entries have been invalidated. ASCE Cleaning Operation
[0070] When bit 52 of general register R2, the clear by ASCE option bit is one, the clear by ASCE operation is specified.
[0071] The contents of general register R3 have the form of an address space control element with only the table origin, bits 0-51 and designation type control (DT), bits 60 and 61, used. These contents are used to select the TLB entries to be cleared. Bits 52-59, 62 and 63 of general register R3 are ignored. R3 can be zero or non-zero, meaning any general register, including register 0, can be disabled.
[0072] Bits 44-51 of general register R2 must be zero; Otherwise, a specification exception is recognized.
[0073] The contents of general register R1 and bit positions 0-43 and 53-63 of general register R2 are ignored.
[0074] The CPU TLBs or CPUs specified in the configuration are cleared at all levels at least from entries for which the table source and designation type fields in the R3 general record match the table source and designation fields in the element address space control (ASCE) used for input. This ASCE is used in the translation during which the input was formed. When the option bit clear by ASCE (bit 52 of general register R2 is one), field M4 is ignored. common operation
[0075] The execution of INVALIDATE DAT TABLE ENTRY is not completed on the executing CPU until the following occurs:1. All entries that meet the criteria specified above have been deleted from this CPU's TLB. When TLB removal local installation is installed and the LC bit in field M4 is one, INVALIDATE DAT TABLE ENTRY execution is complete at this point and the next step is not performed.2. When the local TLB cleanup facility is not installed or when the facility is installed and the LC bit in the M4 field is zero, all other CPUs in the configuration have completed all storage accesses, including updating the change and reference bits, using TLB entries corresponding to the specified parameters. Operations do not necessarily have any effect on real space TLB entries. Special conditions: Bits 44-51 of general register R2 must be zero; Otherwise, a specification exception is recognized. The operation is suppressed on all addressing and protection exceptions (only invalidating and clearing operation). Resulting condition code: The code is unpredictable. Program exceptions:• Addressing (invalid segment or region table entry, only invalidate and clear operation). • Operation (if DAT optimization facility is not installed) • Privileged operation • Protection (search and store, region or segment table entry, key controlled protection and low address protection, only invalidate and clear operation). • SpecificationProgramming Notes:1. Selective clearing of TLB entries can be implemented in different ways depending on the model and, in general, more entries can be deleted than the minimum number needed. When the invalidation and scavenging operation is performed, some models might clear all TLB entries when the effective invalidating index is not a segment index, or might clear an entry regardless of the source of the page table in the entry. When this operation or the clear by ASCE operation is performed, some models may clear a TLB entry regardless of the designation type field in the R3 general record. When any operation is performed, other models can precisely clear the minimum number of entries needed. Therefore, for a program to work on all models, the program must not take advantage of any properties gained by less selective cleaning on a specific model.2. When using the clear by ASCE operation to clear TLB entries associated with common threads, note that these entries may have been formed through the use of address space control elements that contain many different table sources. if when the invalidation and clearing operation is specified. Cleaning up TLB entries can make use of the page table source in a segment table entry. Therefore, if the segment table entry, when in the attached state, already contained a page table source other than the current value, copies of the entries containing the previous values can remain in TLB.4. INVALIDATE DAT TABLE ENTRY cannot be safely used to update a shared location on main storage if there is a possibility that another CPU or channel program is also updating the location.5. The address of the DAT table entry for INVALIDATE DAT TABLE ENTRY is a 64-bit address and the address arithmetic is performed following the normal rules for 64-bit address arithmetic, with 2641 involvement. and length are not used. Contrast this with implicit translation and the translations for LOAD REAL ADDRESS and STORE REAL ADDRESS, all of which can result in an involvement or an addressing exception when a transport occurs outside bit position 0 and which indicates an exception condition when the designated entry is not inside your table. Consequently, DAT tables must not be specified for involving maximum storage locations for location 0 and the first designated entry and all additional entries specified by bits 53-63 of general register R2 must be within the designated table.6. When the local cleanup TLB installation is installed, the local cleanup control must be specified as one when the ASCE used to form the TLB entries being purged has only been appended to the CPU on which the IDTE instruction is executed (for example , if the program is running on a uniprocessor). Otherwise, unpredictable results can occur, including the presentation of a delayed access exception machine check. On some models, using INVALIDATE DAT TABLE ENTRY specifying to clean only the local TLB for the cases listed above can result in improvements to significant performance.7. The M4 field of the instruction is considered optional, as indicated by the field being enclosed in square brackets [ ] in the assembler syntax. When the M4 field is not specified, the assembler places zeros in this field of the instructions.INVALIDATE PAGE TABLE ENTRYIPTE R1, R2[, R3[, M4]]Note: The term "specified CPU or CPUs" has the following meaning for the scope of TLBs affected by this instruction: • When TLB clean-up local facility is not installed or when the facility is installed and the local-clean (LC) control bit in field M4 is zero, the term "specified CPU or CPUs" means all CPUs in the configuration.• When the local TLB removal facility is installed and the LC bit in the M4 field is one, the term "specified CPU or CPUs" means only the CPU that executes the IPTE instruction (the local CPU). TLBs on all other CPUs in the configuration may not be affected.
[0076] Designated page table entries are invalidated and translation-lookaside buffers on the CPU or CPUs specified in the configuration are purged of associated entries.
[0077] The contents of general record R1 have the format of a segment table entry, with only the page table source used. The contents of general register R2 have the format of a virtual address, with just the page index used. The contents of fields that are not part of the source of the page table or page index are ignored. When the IPTE range installation is not installed, or when the R3 field is zero, the single entry in the page table designated by the first and second operands is invalidated.
[0078] When the IPTE range facility is installed and field R3 is non-zero, bits 56-63 of general register R3 contain an unsigned binary integer specifying the count of additional page table entries to be invalidated. Therefore, the number of page table entries to be invalidated is 1-256, corresponding to a value of 0-255 in bits 56-63 of the register.
[0079] When the IPTE range facility is not installed, the R3 field is ignored but must contain zeros; Otherwise, the program may not work compatibly in the future.
[0080] The bits of field M4 are defined as follows: • Reserved: Bits 0-2 are reserved. The reserved bit positions of field M4 are ignored, but must contain zeros; Otherwise, the program may not work compatibly in the future.• Local Wipe Control (LC): When local install TLB removal is installed, bitLC, bit 3 of field M4, controls whether only TLB in local CPU is unchecked or whether the TLBs on all CPUs in the configuration are cleared. When TLB local cleanup installation is not installed, bit 3 of field M4 is reserved.
[0081] The page table source and page index designate a page table entry, following the dynamic address translation rules for page table lookup. The source of the page table is treated as a 64-bit address and addition is performed using the rules for 64-bit address arithmetic, regardless of the current addressing mode, which is specified by bits 31 and 32 of the current PSW. Cannot perform bit position 0 as a result of adding page index and page table origin. The address formed from these two components is a real or absolute address. The invalid page bit of this page table entry is set to one. During this procedure, the page table entry is not inspected if the page's invalid bit is already one or for format errors. Also, the actual address of the page frame contained in the input is not checked for an addressing exception.
[0082] When the IPTE range facility is installed and the R3 field is non-zero, the instruction is interruptible and processing is as follows:1. The invalidation process described above is repeated for each subsequent entry in the page table until the number of additional entries specified in bits 56-63 of general register R3 has been invalidated or an interrupt occurs.2. The page index in bits 44-51 of general register R2 is incremented by the number of page table entries that have been invalidated; a bit position 44 of general register R2.3 is ignored. The additional entry count in bits 56-63 of general register R3 is decremented by the number of page table entries that have been invalidated.
[0083] Therefore, when the installation of the IPTE range is installed, the field R3 is non-zero, and an interruption occurs (other than one that causes termination), the general registers R2 and R3 have been updated, so the instructions , when replayed, return to the breakpoint. When the IPTE range feature is not installed, or when the R3 field is zero, the contents of registers R2 and R3 remain unchanged.
[0084] For each page table entry that is invalidated, the entire page table entry appears to be supplied simultaneously from storage as observed by other CPUs. Afterwards, the byte containing the invalid bit of the page is stored. Fetch access to the page table entry and is subject to key-controlled protection and storage access is subject to key-controlled protection and low-address protection.
[0085] A serialization function is performed before the start of the operation and again after the completion of the operation. As is the case with all serialization operations, this serialization only applies to this CPU; other CPUs are not necessarily serialized.
[0086] If no exception is recognized, this CPU erases the selected entries from its TLB. So, if the local TLB clearing facility is not installed, or if the facility is installed and the LC bit in the M4 field is zero, this CPU signals all CPUs in the configuration to clear the selected entries from their TLBs. For each invalid page table entry, each affected TLB is cleared, at least from those entries that were formed using all of the following: • The page table origin specified by general register R1 • The page index specified by general register R2 • The actual address of the page frame contained in the designated page table entry
[0087] The execution of INVALIDATE PAGE TABLE ENTRY is not completed on the CPU that executes it until the following occurs:1. All page table entries corresponding to the specified parameters have been invalidated.2. All entries corresponding to the specified parameters have been cleared from this CPU's TLB. When the TLB local cleanup installation is installed and the LC bit in the M4 field is one, the execution of the INVALIDATE PAGE TABLE entry is complete at this point and the following step is not performed. When the local TLB removal facility is not installed or when the facility is installed and the LC bit in the M4 field is zero, all other CPUs in the configuration have completed all storage accesses, including the update of the shift and reference bits, using the TLB entries corresponding to the specified parameters.Special conditions
[0088] When the IPTE range installation is installed, field R3 is non-zero and the page index in general register R2 plus additional entry count in general register R3 is greater than 255, a specification exception is recognized .Operation is suppressed for all addressing and protection exceptions. Condition code: the code remains unchanged. Program exceptions:• Addressing (page table entry)• Privileged operation• Protection (search and store, page table entry, key-controlled protection, and low address protection)• SpecificationProgramming Notes:1. Selective cleaning of entries can be implemented in different ways depending on the model and, in general, more entries can be cleaned than the minimum number required. Some models can clear all entries that contain the actual page frame addresses taken from the page table entries in storage. Others can clear all entries that contain the designated page index (or indexes), and some implementations can precisely clear the minimum number of entries needed. Therefore, for a program to work on all models, the program must not take advantage of any properties gained by less selective cleaning on a specific model.2. Cleaning up TLB entries can make use of the actual page frame addresses in the page table entries. Therefore, if the page table entries, when in the attached state, already contained actual page frame addresses that are different from the current values, copies of entries containing the previous values may remain in the TLB. 3. INVALIDATE PAGE TABLE ENTRY cannot be safely used to update a shared location on main storage if there is a possibility that another CPU or a channel program might also be updating the location.4. When the IPTE range facility is installed and the R3 field is non-zero, the following applies:a All page table entries to be invalidated must reside in the same page table. A specification exception is recognized if the page index in general register R1 plus the additional entry count in general register R3 is greater than the maximum page index of 255.b The number of entries in the page table that are invalidated by INVALIDATE PAGE TABLE ENTRY may vary from execution to execution.c The statement cannot be used for situations where the program must rely on uninterrupted execution of the statement. Likewise, the program should not normally use INVALIDATE PAGE TABLE ENTRY to invalidate a page table entry whose actual page frame address designates the 4K-byte block that contains the instructions or of an execution instruction that executes the IPTE.5. When the local TLB pruning facility is installed, the local scavenging control must be specified as one when the ASCE used to form the TLB entries, before they are pruned, was appended only to the CPU on which the IPTE instruction is executed ( for example, if the program is running on a uniprocessor). Otherwise, unpredictable results can occur, including presenting a delayed access exception machine check. In some models, using INVALIDATE PAGE TABLE ENTRY specifying to clean only the local TLB for the cases listed above can result in improvements to significant performance.6. The R3 and M4 fields of the instructions are considered optional, as indicated by the fields that are contained in square brackets [ ] in the assembler syntax. When the field is not specified, the assembler places zeros in the corresponding field of the instruction. When the M4 field is encoded, but the R3 field is not required, a zero must be encoded to designate the place of the third operand.
[0089] An embodiment of a computing environment 100 that incorporates and uses one or more aspects is described with reference to FIGURE 1. The computing environment 100 is based, for example, on the z/Architecture offered by International Business Machines Corporation, Armonk , New York. z/Architecture is described in the IBM® publication entitled "z/Architecture Principles of Operation", IBM Publication No. SA22-7832-08, August 2010. (IBM® is a registered trademark of International Business Machines Corporation, Armonk, New York, USA Other names used herein may be trademarks, registered trademarks or product names of International Business Machines Corporation or other companies.) In one example, a z/Architecture-based computing environment includes an eServer zSeries, offered by International Business Machines Corporation, Armonk, New York.
[0090] As an example, computing environment 100 includes a central processor complex (CPC) 102 coupled to a controller 120. The central processor complex 102 includes, for example, one or more partitions 104 (e.g., logical partitions LP1-LPn), one or more central processors 106 (for example, CP1-CPm) and a hypervisor 108 (for example, a logical partition manager), each of which is described below.
[0091] Each logical partition 104 is capable of functioning as a separate system. That is, each logical partition can be reset independently, initially loaded with an operating system if desired, and run with different programs. An operating system or application program running on a logical partition appears to have access to a complete system, but in reality, only a portion of it is available. A combination of hardware and Licensed Internal Code (commonly referred to as microcode) prevents a program in one logical partition from interfering with a program in a different logical partition. This allows multiple different logical partitions to operate on a single or multiple physical processors in a time-stamped manner. In this particular example, each logical partition has a resident operating system 110, which can differ for one or more logical partitions. In one embodiment, operating system 110 is the z/OS operating system offered by International Business Machines Corporation, Armonk, New York.
[0092] Central processors 106 are physical processor resources allocated to logical partitions. For example, a logical partition 104 includes one or more logical processors, each of which represents all or part of a physical process or resource 106 assigned to the partition. The logical processors of a particular partition 104 may be dedicated to the partition so that the underlying processor resource is reserved for that partition; or shared with another partition, so that the underlying processor resource is potentially available to another partition.
[0093] Logical partitions 104 are managed by hypervisor 108 implemented by microcode executed on processors 106. Logical partitions 104 and hypervisor 108 each comprise one or more programs residing in respective portions of central storage associated with the central processors. An example of hypervisor 108 is Processor Resource/Systems Manager (PR/SM), offered by International Business Machines Corporation, Armonk, New York.
[0094] The controller 120, which is coupled to the central processor complex, includes centralized logic responsible for arbitrating between different processors that issue requests. For example, when controller 120 receives a request, it determines that the requester is the main processor for that request and that the other processors are slave processors; transmit messages; and otherwise handles orders. An example of a controller is described in US Patent No. 6,199,219 entitled "System Serialization With Early Release Of Individual Processor", Webb et al., September 12, 2000. Other details are also described with reference to FIGURE 2.
[0095] FIGURE 2 represents an example of a controller 200 coupled to a plurality of central processors (CPUs) 201. In this example, two central processors are represented. However, it will be understood that more than two processors can be coupled to controller 200.
[0096] The controller 200 includes various controls including, for example, system serialization controls 202. System serialization controls are used to ensure that operations that are to be serialized, such as invalidating instructions, are serialized to the extent that only one of these instructions is in progress at the same time in the computing environment. It also monitors the sequence of events for that operation.
[0097] The controller 200 is coupled to each central processor through various interfaces. For example, an interface 204 is used by Internal Code licensed on a central processor to send "control" commands to the controller, which specify an action to be taken, and to send "detect" commands, which return information from the controller. Another interface is a 206 response bus, which is used to return controller information for "sensing" commands. The response bus is also used to communicate command status to "control" commands and can be configured from a variety of sources within the controller, including system serialization controls. A central processor can use this interface to detect the state of system serialization controls on the 200 controller.
[0098] Another interface is interface 208, which is used by the controller to send commands to each CPU. This can also be controlled from a plurality of sources within the controller, including system serialization controls 202. A still additional interface is interface 210, which provides signals to cache controls 212 of the central processor 201. Cache controls 212 process commands in response to signals. In one example, cache controls 212 process commands that affect one or more buffers, such as Translation Lookaside Buffers (TLBs) 213, as described in additional detail below.
[0099] In addition to the 212 cache controls, the central processor 201 includes several other controls, including, for example, interrupt 220 controls and 222 execution controls. In response to particular events, interrupt controls 220 cause an interrupt internal is pending in the CPU, which in turn causes the execution controls 222 to suspend processing the program instruction at the next interrupt point. In response to the interrupt, execution controls 222 invoke a Licensed Internal Code routine to set an allowed transmit operation lock 224 to enable cache controls 212 in order to process pending commands.
[0100] The central processor 201 also includes a central processing unit (CPU) lock 226 that indicates whether or not the central processor is stopped. The terms CPU and Processor can be used interchangeably in the specification.
[0101] The computing environment described above is just an example. Many variations are possible. For example, one or more partitions can run in different architectural modes. Also, as another example, the environment does not need to be based on z/Architecture, but can be based on other architectures offered by Intel, Sun Microsystems, as well as others. In addition, an environment can include an emulator (for example, software or other emulation mechanisms), where a particular architecture or its subset is emulated. In such an environment, one or more emulator functions may implement one or more because a computer running the emulator may have a different architecture than the emulated capability. As an example, in emulation mode, the specific instruction or operation being emulated is decoded, and an appropriate emulation function is built to implement the individual instruction or operation.
[0102] More details of an emulation environment are described with reference to FIGURE 3. As an example, a host computer 300 is capable of emulating other computer architecture, computing and/or processing capabilities. For example, host computer 300 is based on an Intel architecture; a RISC architecture such as PowerPC; a SPARC architecture, offered by Sun Microsystems; or other architecture, and is capable of emulating the z/Architecture of IBM® or another architecture of IBM® or another entity.
[0103] The host computer 300 includes, for example, a memory 302 for storing instructions and data; an instruction fetch unit 304 for fetching instructions from memory 302 and optionally providing a local temporary storage memory for the obtained instructions; an instruction decoding unit 306 for receiving instructions from the instruction fetch unit 304 and for determining the type of instructions that have been obtained; and an instruction execution unit 308 for executing the instructions. Execution may include loading data into a register from memory 302; store data back to memory from a record; or perform some kind of arithmetic or logical operation as determined by the decoding unit.
[0104] In one example, each unit described above is implemented in software. For example, operations performed by units are implemented as one or more subroutines in the emulator software. In another example, one or more of the operations are implemented in firmware, hardware, software, or some combination of them.
[0105] Furthermore, although FIGURE 3 is described with reference to emulation, the environment of FIGURE 3 need not be an emulation environment. In another example, instructions are executed in a native environment, and operations are implemented in hardware, firmware, software, or some combination of them.
[0106] A computing environment can include virtual storage as well as main storage. Virtual storage can exceed the size of main storage available in the configuration and is typically kept in auxiliary storage. Virtual storage is considered to be made up of blocks of addresses, called pages. The latest pages pertaining to virtual storage are assigned to occupy blocks of physical main storage. As a user refers to virtual storage pages that do not appear in main storage, the virtual pages are brought in to replace pages in main storage that are less likely to be used. Swapping pages in storage can be performed by the operating system without the user's knowledge.
[0107] Addresses used to designate locations in virtual storage are referred to as virtual addresses. A block of sequential virtual addresses spanning, for example, up to 4k bytes, is referred to as a page. Likewise, a spanning block of sequential virtual pages, eg up to 4k bytes, is referred to as a segment; and a block of sequential virtual segments spanning, for example, up to 2G bytes, is referred to as a region. In addition, a sequence of virtual addresses associated with virtual storage designated by an address space control element (ASCE) is called an address space. Address spaces can be used to provide degrees of isolation between users. An address space can include one or more regions, one or more segments, one or more pages, or some combination thereof.
[0108] Associated with the different types of storage units (for example, regions, segments, pages) are data structures to be used in the processing associated with the storage units. For example, associated with regions are tables of regions; associated with segments are segment tables; and associated with the pages are page tables. These tables are used, for example, when translating (eg Dynamic Address Translation) from a virtual address to a real address that is used to access main storage. Tables to be used in translation, referred to herein as translation tables, are designated by an address space control element (ASCE). A unit of virtual storage that is not currently assigned to main storage is called invalid. The invalid state of a virtual drive. Storage is indicated by an invalid indicator in the data structure associated with the unit.
[0109] The dynamic address translation mechanism is implemented, in one embodiment, so that information derived from the translation tables (eg region tables, segment tables and/or page tables) through the DAT process is maintained in one or more buffers located within the processors, referred to herein as Translation Lookaside Buffers, to improve address translation performance. That is, during translation the buffers are checked for the necessary information and, if the information is not in the buffers, one or more of the translation tables are accessed.
[0110] In emulation mode, the emulated specific instruction is decoded and a subroutine is built to implement the individual instructions, as in a subroutine or C driver, or some other technique is used to provide a driver for the hardware specific, as is within the skill of those skilled in the art after understanding the description of an embodiment. Various software and hardware emulation patents including, but not limited to, US Patent No. 5,551,013 entitled "Multiprocessor for Hardware Emulation", Beausoleil et al; US Patent No. 6,009,261 entitled "Preprocessing of Stored Target Routines for Emulating Incompatible Instructions on a Target Processor", Scalzi et al; US Patent No. 5,574,873 entitled "Decoding Guest Instruction to Directly Access Emulation Routines That Emulate the Guest Instructions", Davidian et al; US Patent No. 6,308,255 entitled "Symmetrical Multiprocessing Bus and Chipset Used for Coprocessor Support Allowing Non-Native Code to Run in a System”, Gorishek et al.; US Patent No. 6,463,582 entitled "Dynamic Optimizing Object Code Translator For Architecture Emulation and Dynamic Optimizing Object Code Translation Method", Lethin et al.; and US Patent No. 5,790,825 entitled "Method for Emulating Guest Instructions on a Host Computer Through Dynamic Recompilation of Host Instructions", Eric Traut; and many others, we have proven a variety of known ways to achieve emulation of an instruction format architected for a different machine to a target machine available to those skilled in the art, as well as commercial software techniques used by those referenced above. COMPARE AND REPLACE DAT TABLE ENTRY (CRDTE)
[0111] A CPU instruction ((COMPARE AND REPLACE DAT TABLE ENTRY)) is described that can replace a valid DAT table entry with a new entry and purge the TLB of any copy of (at least) the single entry in all CPUs in the configuration. This instruction does not require any active tasks to be suspended, and cannot clear more entries than necessary.
[0112] When the CRDTE instruction is executed, selective cleaning of inputs can be implemented in different ways depending on the model and, in general, more inputs than the minimum number required can be cleaned. Some models can clear all entries that contain the actual page frame addresses taken from the page table entries in storage.
[0113] If the driver needs to replace a valid entry in a DAT table (that is, a table entry potentially used by other CPUs), it can perform one of the following operations: • Suspend execution of all tasks that can use this DAT table entry on all CPUs in the configuration, invalidate and purge the entry on all CPUs (for example, using IPTE), replace the invalidated entry with a new entry, and redistribute the suspended tasks. DAT and purge the entire TLB on all CPUs in the configuration (eg using CSPG).
[0114] The first option is complex in that it requires non-distribution and redistribution of message handling tasks. The second option is sub-optimal in that it requires purging the entire TLB, even if only one entry is being changed.
[0115] In one embodiment, a computer processor obtains an instruction for processing. Based on the opcode, the machine processes the Compare and Replace instructions from the DAT Table Entry (CRDTE). The CRDTE instruction has the following format: Opcode R3 M4 R1 R2
[0116] Fields R1 and R2 designate a pair of odd and even general records and shall designate an even numbered record; Otherwise, a specification exception is recognized. General register R1 (the even-odd register) contains the first operand. The first operand can be called the comparison value. The general register R1 + 1 (the odd register of the even) can be called the replacement value.
[0117] When executing the instructions, the first and second operands are compared. The first operand is located in general register R1. The second operand is designated by general registers R2 and R2 + 1. R2 and R2 + 1 contain addressing information such as designated table type (DTT) and effective index in the table to locate the second operand.
[0118] Once the first and second operands are obtained, they are compared and, if they are equal, the contents of the general register R1 + 1 are stored in the location of the second operand, and the CPU or CPUs specified in the configuration are cleared of (1) all TLB table entries of the designated type formed through the use of the superseded entry in storage and (2) all lower-level TLB table entries formed through the use of the cleared top-level TLB table entries. Cleaned TLB entries can optionally be limited to entries formed to translate addresses in a specified summary space. The resulting condition code is set to 0.
[0119] If the first and second operands are not equal, the second operand is loaded into the first location of the operand and the resulting condition code is set to 1. Field M4 can determine if you want to clear the TLBs of all CPUs in a configuration or just the TLB on the CPU executing the instructions. Figure 4 displays a graph of one achievement.
[0120] In one embodiment, a computer processor obtains a 0401 CRDTE instruction for processing. Based on the opcode, the machine processes the Compare and Replace DAT Table Entry instruction.
[0121] Fields R1 and R2 designate a pair of even and even 0405 general registers and shall designate an even numbered register; Otherwise, a specification exception is recognized. General register R1 (the even register of the pair) 0410 contains the first operand in bit positions 0-63. The first operand can be called the comparison value. Bit positions 0-63 of general register R1 + 1 (the odd register of even) 0411 can be called replacement values.
[0122] When executing instructions, the first and second operands are compared. The first operand is located in general register R1 0410. The second operand is a double word in storage designated by general registers R2 0420 and R2 + 1 0421. Bits 59-61 of general register R2 are the designated table type (DTT) , specifying the bits in general register R2 that form the origin of a table 0430 in storage 0440; the DTT also specifies the bits in general register R2 + 1 that are used as the effective index into the table to find the second operand 0435.
[0123] Since the first and second operands are compared 0436, if they are equal, the contents of general register R1 + 1 are stored in the location of the second operand 0445, and as shown in 0450, the CPU or CPU in the configuration is cleared of (1) all TLB table entries of the designated type formed through the use of the superseded entry in storage and (2) all lower-level TLB table entries formed through the use of the cleared top-level TLB table entries. Cleaned TLB entries can optionally be limited to entries formed to translate addresses in a specified address space. The resulting condition code is set to 0 as shown in 0455.
[0124] If the first and second operands are different, the second operand is loaded into the first location of operand 0460. The resulting condition code is set to 1, as shown in 0465.
[0125] Instruction 0401 can use field M4 0402 to determine whether to selectively clear the TLBs of all CPUs in a 1570 configuration or just the TLB on the CPU executing the 1575 instructions. Field M4 contains a Local clearing control (LC ). If the LC control in the M4 field is zero, the TLBs on all CPUs in the configuration will be affected. If the LC control field in field M4 is one, only the TLB associated with the CPU executing the Compare and Replace instructions for the DAT Table Entry can be affected. TLBs on all other CPUs in the configuration may not be affected.
[0126] Note: The term "specified CPU or CPUs" has the following meaning for the scope of TLBs affected by this instruction:
[0127] When the local clean control (LC) in field M4 is zero, the term "specified CPU or CPUs" means all CPUs in the configuration.
[0128] When the LC control in field M4 is one, the term "specified CPU or CPUs" means only the CPU executing the COMPARRE AND REPLACE DAT TABLE ENTRY instruction (the local CPU). TLBs on all other CPUs in the configuration may not be affected. • The first and second operands are compared. If they are equal, the contents of the general register R1 + 1 are stored in the location of the second operand and the CPUs or CPUs specified in the configuration are cleared of (1) all TLB table entries of the designated type formed by using the entry substituted in storage and (2) all lower-level TLB table entries for the use of the cleared top-level TLB table entries. Cleaned TLB entries can optionally be limited to entries formed to translate addresses in a specified address space. • If the first and second operands are unequal, the second operand is loaded into the first place of the operand. However, in some models, the second operand can be fetched and later stored back without changing the location of the second operand. This update appears to be a block parallel wired update reference as observed by other CPUs. The result of the comparison is indicated by the condition code.
[0129] Fields R1 and R2 designate a pair of even and even general records and shall designate an even numbered record; Otherwise, a specification exception is recognized. As far as Figure 5 is concerned, the first operand is called comparison value 0501 and is contained in bit positions 0-63 of general register R1. Bit positions 0-63 of general register R1 + 1 are called substitution value 0510.
[0130] The second operand is a double word in storage designated by general registers R2 and R2 + 1 0540. Bits 59-61 of general register R2 are the designated table type (DTT), specifying the bits in general register R2 that form the source of a table in storage; the DTT also specifies the bits in general register R2 + 1 0540 that are used as the effective index into the table to find the second operand, as follows:

[0131] When DTT is binary 000, as shown in 0520, the contents of bit positions 0-52 of general register R2, with eleven zeros appended to the right, 0521, form the table origin and bits 53-58 in 0522, 62 in 0523 and 63 in 0524 of the record are ignored. When the DTT is binary 100-111, as shown in 0530, the contents of bit positions 0-51 of general register R2, with twelve zeros appended to the right, 0531 form the table origin and bits 52 to 58 in 0532, 62 in 0533 and 63 in 0534 of the registry are ignored. TDT values of 001, 010 and oil torque are invalid; a specification exception is recognized if the DTT is invalid.
[0132] Bits 0-51 of general register R2 + 1 0540 have the format of region index, segment index and page index of a virtual address. The part of bits 0-51 in 0541 normally used by DAT to select an entry in the type of table designated by DTT is called the effective index. The part of bits 0-51 of general register R2 + 1 to the right of the effective index is ignored. Bit positions 52-63 of general register R2 + 1, 0542, are reserved and must contain zeros; Otherwise, a specification exception is recognized.
[0133] If R3 0550 is non-zero, the contents of general register R3 have the form of an address space control element with only the table origin, bits 0-51 in 0551, and designation type control ( DT), bits 60 and 61 in 0553, used. These are used to select the TLB entries to be cleared. Bits 52-59 in 0552, 62 in 0554, and 63 in 0555 of general register R3 are ignored. If R3 is zero, all contents of general register 0 will be ignored and TLB entries will be cleared regardless of the ASCE used to form them.
[0134] The M4 field is shown in Figure 6.
[0135] The bits of field M4 are defined as follows:
[0136] Reserved: Bits 0-2, as shown in 0601, are reserved. The reserved bit positions of field M4 are ignored, but must contain zeros; Otherwise, the program may not work compatibly in the future.
[0137] Local Clear Control (LC):The LC bit, bit 3 of field M4 0602, controls whether only the TLB on the local CPU is clear or whether the TLBs on all CPUs in the configuration are clear.
[0138] When the first and second operands are equal, the contents of the general register R1 + 1 are stored in the location of the second operand and the Translationlookaside Buffers (TLBs) on the CPUs specified in the configuration are cleared (1) all table entries TLB of the designated type formed by using the source contents of the second operand in storage (that is, the contents of the second operand before being replaced by the replacement value) and (2) all lower-level TLB table entries were formed through the use of the clean top-level TLB table entries. Cleaned TLB entries can optionally be limited to entries formed to translate addresses in a specified address space.
[0139] Depending on the table type, the table origin in general register R2 and the effective index in general register R2 + 1 designate a table entry according to the rules in "Lookup in a Table Designated by an AddressSpace-Control Element " or "Page-Table Lookup" in the z/Architecture Principles of Operation,” IBM Publication No. SA22-7832-08, Aug 2010, except that a carry of bit position 0 of the resulting address is always ignored, and the index is not checked on a table length field. The table origin is treated as a 64-bit address and addition is performed using the rules for 64-bit address arithmetic, regardless of the current addressing mode specified by bits 31 and 32 of the current PSW. The address formed from these two components is a real or absolute address. The contents of the table entry are not examined for validity, and no exception conditions are recognized due to the contents of the table entry.
[0140] Searching and storing the table entry is performed as a parallel linked block update. Entry access access is subject to key controlled protection and storage access is subject to key controlled protection and low address protection.
[0141] A serialization function is performed before the start of the operation and again after the completion of the operation. As is the case with all serialization operations, this serialization only applies to this CPU; Other CPUs are not necessarily serialized.
[0142] When the first and second operands are the same, this CPU clears the selected entries from its TLB. In addition to local CPU clearing, if the LC bit in the M4 field is zero, all other CPUs in the configuration will be flagged to clear the selected entries from their TLBs. Each TLB is cleared of at least the entries for which all of the following conditions are met:
[0143] - The effective index in general register R2 + 1 corresponds to the corresponding index in the TLB table entry of the type designated by field DTT in bits 59-61 of general register R2. If the model implements a composite TLB entry that includes the index designated by the DTT field, the bits to the left of the effective index in general register R2 + 1 also match any corresponding bits provided in the designated TLB table entry.
[0144] - Either the R3 field is zero, or the table source and assignment type fields in general record R3 match the table source and assignment type fields in the address space control element (ASCE) used to form the TLB table entry.
[0145] - If field R3 is zero, then the condition described in this step does not apply.
[0146] - If EDAT-1 applies and the replaced entry in storage is a segment table entry, or if EDAT-2 applies and the replaced entry in storage is a third region table entry, format control in the replaced entry corresponds to the TLB entry.
[0147] - If the replaced entry in storage designates a lower-level translation table, the lower-level table origin in the entry matches the table origin field in the TLB entry.
[0148] - If EDAT-1 applies and the replaced entry in storage is a segment table entry where the format control is one, or if EDAT-2 applies and the replaced entry in storage is a third entry region where the format control is one, the absolute address of the segment frame or the absolute address of the region frame, respectively, in the replaced entry matches that of the TLB entry.
[0149] Each affected TLB is also cleared of at least any low-level TLB table entries for which all of the following conditions are met:
[0150] The lower-level TLB table entry was formed by using the superseded entry in storage or by using a top-level TLB table entry, formed by using the superseded entry in storage or a clean TLB entry in this process.
[0151] Either the R3 field is zero or the table source and designation type fields in the R3 general record match the table source and designation fields in the address space control element (ASCE) used to form the low-level TLB table entry. This ASCE can be one that is appended to a translation path containing a top-level table entry that appended the bottom-level table entry in storage from which the bottom-level TLB table entry was formed, or it can be a which made it more useful - level TLB table entry which appended the lower level table entry in storage from which the lower level TLB table entry was formed.
[0152] If the R3 field is zero, the condition described in this step does not apply.
[0153] - If EDAT-1 applies and the replaced entry in storage is a segment table entry, or if EDAT-2 applies and the replaced entry in storage is a third region table entry, format control in the replaced entry corresponds to the TLB entry.
[0154] If the storage entry designates a lower-level translation table, the lower-level table origin in the entry matches the table origin field in the TLB table entry.
[0155] When the first and second operands are the same, the execution of COMPARE AND REPLACE DAT TABLE ENTRY is not completed on the executing CPU until the following occurs:1. All entries that meet the criteria specified above have been cleared from this CPU's TLB. When the LC control in field M4 is one, the execution of COMPARE AND REPLACE DAT TABLE ENTRY is complete and the next step is not executed.2. When the LC control in the M4 field is zero, all other CPUs in the configuration have completed all storage accesses, including updating the shift and reference bits.
[0156] The operation does not necessarily have any effect on real space TLB entries.
[0157] Special conditions
[0158] A specification exception is recognized and the operation is suppressed if any of the following conditions are true:
[0159] Field R1 or R2 is odd.
[0160] DTT fields, bit positions 59-61 of general register R2, contain 001, 010 or 011 binary.
[0161] Bit positions 52-63 of general register R2 + 1 contain non-zero values.
[0162] Operation is suppressed on all addressing and protection exceptions.
[0163] Resulting condition code:0 - First and second operands equal, second operand replaced by the contents of general register R1 + 11 - First and second operands unequal, first operand replaced by second operand23 -
[0164] Program exceptions:• Addressing• Operation (if enhanced DAT 2 feature is not installed)• Privileged operation• Protection (search and store, region, segment or page table entry, key-controlled protection, and address protection low) • Specification
[0165] Programming Notes:1. Selective scavenging of TLB entries can be implemented in different ways depending on the model, and in general more entries can be scavenged than the minimum number required.2. When cleaning up TLB entries associated with common segments, note that these entries may have been formed through the use of address space control elements containing many different table sources.3. The M4 field of the instruction is considered optional, as indicated by the field being enclosed in square brackets [ ] in the assembler syntax. When the M4 field is not specified, the assembler puts zeros in this field of instructions.4. Local cleaning control must be specified as one only when any of the following is true; Otherwise, unpredictable results can occur, including the presentation of a delayed access exception machine check.• The program is running in a uniprocessor configuration.• The program is assigned to run on a single CPU and the affinity between the program and that CPU is kept. On some models, using COMPARE AND REPLACE DAT TABLE ENTRY, specifying to clean only the local TLB for the cases listed above can result in better performances.
[0166] Many variations to the above environment are possible. For example, one or more aspects are equally applicable, for example, to virtual machine emulation, where one or more advertising entities (eg, guests) run on one or more processors. As an example, paying guests are defined by the Start Interpretive Execution (SIE) architecture, an example of which is described in an IBM® publication entitled "IBM System/370 Extended Architecture", IBM publication No. SA22-7095 (1985), which is incorporated herein by reference in its entirety.
[0167] Although SIE and z/Architecture are mentioned above, one or more aspects are equally applicable to other architectures and/or environments that employ advertising entities or similar constructs.
[0168] Furthermore, the various embodiments described above are only exemplary. For example, although a logically partitioned environment is described here, this is just an example. Aspects are beneficial for many types of environments, including other environments that have a plurality of zones and unpartitioned environments. Also, there may be no central processor complexes, but still, multiple processors are coupled. Furthermore, one or more aspects are applicable to single-processor environments.
[0169] Although specific environments are described here, again, many variations to these environments can be implemented. For example, if the environment is partitioned apart, more or less logical partitions can be added to the environment. In addition, there may be multiple central processing complexes coupled together. These are just a few of the variations that can be made. Also, other variations are possible. Also, the environment can include multiple controllers. However, several quiescent requests (from one or more controllers) can be simultaneously pending on the system. Additional variations are also possible.
[0170] Advantageously, one or more aspects may benefit from the performance improvements described in one or more of the following US patents: US Patent 7,530,067 entitled "Filtering Processor Requests Based On Identifiers", Siegel et al; US Patent 7,020,761 entitled "Blocking Processing Restrictions Based On Page Indices", Siegel et al., and US Patent 6,996,698 entitled "Blocking Processing Restrictions Based On Addresses", Siegel et al.
[0171] As used herein, the term "processing unit" includes advertising entities, such as guests; processors; emulators; and/or other similar components. In addition, the term "by a processing unit" includes in the name of a processing unit. The term "buffer" includes a storage area as well as different types of data structures, including but not limited to arrays; and the term "table" may include other table-like data structures. In addition, instructions may include other than records to designate information. Also, a page, a segment and/or a region can be different sizes from those described here.
[0172] One or more of the features may be implemented in software, firmware, hardware, or some combination. Also, one or more of the features can be emulated.
[0173] One or more aspects may be included in an article of manufacture (eg, one or more computer program products) having, for example, computer-usable media. The media incorporated, for example, means of computer-readable program code or logic (eg, instructions, code, commands, etc.) to provide and facilitate features. The article of manufacture can be included as part of a computer system or sold separately.
[0174] Furthermore, at least one machine-readable program storage device may be provided that incorporates at least one machine-executable instruction program to execute the capabilities.
[0175] The flow diagrams described here are just examples. They can be many variations of these diagrams or the steps (or operations) described there. For example, steps can be performed in a different order, or steps can be added, deleted, or modified.
[0176] Although preferred embodiments have been depicted and described in detail herein, it will be apparent to those skilled in the relevant art that various modifications, additions, substitutions and the like can be made and therefore are considered to be within the scope defined in the claims to follow
[0177] In another embodiment, a data processing system suitable for storing and/or executing program code is usable which includes at least one processor directly or indirectly coupled to memory elements via a system bus. Memory elements include, for example, local memory employed during the actual execution of program code, mass storage, and cache memory that provide temporary storage of at least some program code to reduce the number of times the code must be retrieved from the storage volume at runtime.
[0178] Input/Output or I/O devices (including but not limited to keyboards, displays, pointing devices, DASD, tape, CDs, DVDs, thumbnails and other memory media, etc.) may be attached to the system directly or through intervening I/O controllers. Network adapters can also be coupled to the system to allow the data processing system to be coupled to other data processing systems or remote printers or storage devices via interposed public or private networks. Modems, cable modems and Ethernet network cards are just some of the types of network adapters available.
[0179] One or more aspects may be included in an article of manufacture (eg, one or more computer program products) having, for example, computer-usable media. The media has, for example, computer readable program code media or logic (eg instructions, code, commands, etc.) to provide and facilitate the features. The article of manufacture can be included as part of a system (eg computer system) or sold separately.
[0180] An example of an article of manufacture or a computer program product that incorporates one or more aspects is described with reference to FIGURE 7. A 0700 computer program product includes, for example, one or more usable media of the computer 0702 for storing network program code means or logic 0704 thereon to provide and facilitate one or more aspects. The medium can be an electronic, magnetic, optical, electromagnetic, infrared or semiconductor system (or apparatus or device) or a propagation medium. Examples of a computer-readable medium include a semiconductor or solid-state memory, magnetic tape, a removable computer floppy disk, a random access memory (RAM), a read-only memory (ROM), a magnetic hard disk, and a disk optical. Examples of optical discs include read-only memory compact disc (CD-ROM), read/write compact disc (CD-R/W), and DVD. A sequence of program instructions or a logical assembly of one or more interrelated modules defined by one or more computer-readable program codes or logic drives the performance of one or more aspects.

权利要求:
Claims (7)
[0001]
1. Method for managing a dynamic address translation table (DAT), the method characterized by the fact that it comprises the steps of: determining, by a processor, from an operation code of a machine executable instruction (401) to be executed, which is a compare and replace DTA table entry instruction, which is used to replace a valid DAT table entry with a new entry, the instruction comprising an R1 field and an R2 field, the R1 and R2 fields. R2 each designating an odd-even numbered pair of registers R1 and R1+1 and R2 and R2+1, and must designate an equally numbered register, where general register R1 is the even register of the even and contains a first considered operand the comparison value, general registers R1+1 is the odd register of the even and contains replacement value, and where general registers R2 and R2+1 contain address information such as a designated table type and effective index within a table to allocate a second original operand nal from a second operand memory location; and execute, by the processor, the instruction, comprising: comparing (436) the obtained original first operand and second operand; based on the first operand being equal to the original second operand, store (445) the replacement value in the second operand location in the memory as a new second operand; selectively clear (450) all local translation lookaside buffer (TLB) entries corresponding to entries formed from DAT table entries using translation based on a translation table entry designated by an initial second operand value.
[0002]
2. Method according to claim 1, characterized in that it comprises the storage of the second original operand to the pair register R1 based on the first operand not being equal to the second initial operand.
[0003]
3. Method according to claim 1, characterized in that a selectively computed translation table entry corresponds to lower-level translation table entries associated with the second initial operand.
[0004]
4. Method, according to claim 1, characterized in that it further comprises: based on a first operand being equal to the original second operand, defining a first condition code value; and based on a first operand being different from the original second operand, establish a second condition code value.
[0005]
5. Method according to claim 1, characterized in that the compensated TLB inputs are limited to inputs formed to translate addresses in an address space specified by the instruction.
[0006]
6. Method according to claim 1, characterized in that it further comprises: based on an instruction mask field having a first value, selectively clearing only one TLB of the processor executing the instruction from a plurality of processors a configuration; and based on an instruction mask field that has a second value, selectively clear the TLB from a plurality of processors in the configuration.
[0007]
7. System characterized in that it comprises means adapted to carry out all the steps of the method as defined in any one of claims 1 to 6.

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法律状态:
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2018-05-15| B04C| Request for examination: application reinstated [chapter 4.3 patent gazette]|

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2019-12-10| B06U| Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]|

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2021-06-29| B09A| Decision: intention to grant [chapter 9.1 patent gazette]|

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2021-08-10| B16A| Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 26/11/2012, OBSERVADAS AS CONDICOES LEGAIS. |

优先权:

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申请号 | 申请日 | 专利标题

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US13/524,468|US20130339656A1|2012-06-15|2012-06-15|Compare and Replace DAT Table Entry|

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