巴西专利BR112014002542B1 power amplifier circuit and adaptation unit

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专利摘要:
HIGH EFFICIENCY POWER AMPLIFIER. It is a power amplifier circuit (100) comprising a cross-coupled transistor unit (110) comprising a pair of cross-coupled cascode transistors (112), a switching transistor unit (120) which comprises a pair of cross-coupled switching transistors (122), and an RF current generator (130), an RF current generator (130) generates a differential RF injection current, while the switching transistor unit (120 ) amplifies the injection current to generate an amplified injection current at the broadband node of the amplifier circuit (100) and the cascode transistor unit (110) further amplifies the injection current to generate the desired amplified signal at the output of the amplifier circuit (100). The output signal amplitude generally depends on the differential injection current and the supply voltage V00 applied to the power amplifier circuit (100).
公开号:BR112014002542B1
申请号:R112014002542-8
申请日:2012-07-17
公开日:2021-05-18
发明作者:Henrik Sjöland；Jonas Lindstrand；Carl Bryant
申请人:Telefonaktiebolaget L M Ericsson (Publ)；
IPC主号:

专利说明:

[001] The invention described here generally relates to amplifiers, and more particularly relates to power amplifiers of wireless communication devices. BACKGROUND
[002] Current wireless technology tends to augment numerous wireless standards and radio frequency (RF) bands to support wireless communication have resulted in the development of multi-standard, multi-band cellular systems. These efforts have produced broadband receivers and frequency synthesizers with satisfactory performance. However, power amplifiers that deliver the desired performance, eg Added Power Efficiency (PAE), output power, etc., across multiple frequency bands remain a challenge for these cellular systems.
[003] Although several groups have tried to solve this problem, the results generally do not provide sufficient efficiency across a wide frequency band, undesirably require multiple amplifier stages, do not provide wideband operation, etc. For example, "A Polyphase Multipath Technique for Software-Defined Radio Transmitters" by R. Shrestha, E.A.M. Klumperink, E. Mensink, G.J.M. Wienk, and B. Nauta (IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2681-2692, 2006) provides a broadband solution, but the output power is insufficient and the efficiency across the broadband is low compared to single-band amplifiers. "A 1.9 GHz 1W CMOS Class E Power Amplifier for Wireless Communications" filed with K.C. Tsai and PR Gray (ESSC/RC, pp. 76-79, 1998), referred to here as the Tsai solution, and "A 29 dBm 70.7% PAE Injection-Locked CMOS Power Amplifier for PWM Digitized Polar Transmitter" by J. Paek and S Hong (Microwave and Wireless Components Letters, vol. 20, no. 11, pp. 637-639, 2010), referred to here as the Paek solution, provide alternative solutions using injection-lock power amplifiers. These solutions, however, require multiple amplifier stages and have not shown wideband frequency operation. Another solution, "At 65 nm CMOS 30 dBm Class-E RF Power Amplifier with 60% Power Added Efficiency" by M. Apostolidou, M.P. van der Heijden, D.M.W. Leenaerts, J. Sonsky, A. Heringa, and l. Volokhine (Radio Frequency Integrated Circuits Symposium, pp. 141-144, 2008), referred to here as the Apostolidou solution, provides a broadband solution with enhanced PAE and output power but requires multiple amplifier stages, this undesirably increases the area of chip and the power consumption of the amplifier.
[004] Thus, there is still a need for an improved power amplifier useful in broadband RF scenarios. SUMMARY
[005] The power amplifier circuit described here uses a cascode topology derived from cross coupling together with a technique of applying an RF injection current at a broadband node to provide a single stage power amplifier with enhanced PAE, power of output, and gain over a wide radio frequency band. It will be appreciated that although the power amplifier described here can be used for wideband operations, the power amplifier also provides high efficiency, output power, and gain for narrower frequency band applications.
[006] The power amplifier circuit comprises a current generator, a pair of cross-coupled switching transistors, a pair of cross-coupled cascode transistors, and first and second shunt capacitors. The current generator is configured to generate a radio frequency differential injection current into a differential current generator output based on an input signal. The input signal may comprise any of an analogue input voltage signal at the radio frequency, or a baseband input signal, for example, an analogue or digital baseband input signal. Switching transistors include a source node, a gate node, and a drain node, and are cross-coupled so that the drain node of one switching transistor couples to the gate node of the other switching transistor. . Furthermore, the drain nodes of the switching transistors are coupled to the differential current generator output to receive the differential injection current. Cascode transistors include a source node, a gate node, and a drain node, and are cross-coupled so that the drain node of one cascode transistor couples to the gate node the gate node of the other cascade transistor . The cross-coupled cascode transistors are configured to generate an amplified output signal differential amplified output signal at the drain nodes of the cascode transistors based on a supply voltage operably coupled to the drain node of the cascode transistors and the differential injection current applied to the source node of the cascode transistors. The first and second shunt capacitors couple to the respective gate nodes of the cascode transistors. In one embodiment, the shunt capacitors have a capacitance selected to control the amplitude of a gate signal at the gate nodes of the cascade transistors substantially equal to the amplitude of a source signal at the corresponding source nodes of the cascade transistors. As used herein, substantially equal can mean equal, but more likely means that the amplitude of the gate signals at the gate nodes of the cascode transistors has some deviation, for example, it deviates within a certain range around the amplitude of the source signals at the source nodes corresponding to the cascode transistors. The deviation range should be, for example, 10%. In other modalities, the deviation range should be 5% in some cases, 2% in other cases, 20% in other cases, 50% in other cases, or any other value in between, depending on the values of specific components or conditions of circuit operation. Preferably, this offset range is beyond the full dynamic range of the amplifier circuit. However, there may be intervals where the deviation range is greater. The total length of these gaps preferably constitutes no more than 20% of the entire dynamic range, however in some cases a total gap length, eg 10% or 5% or 2% may be required. BRIEF DESCRIPTION OF THE DRAWINGS
[007] Figure 1 shows a power amplifier circuit according to an exemplary modality.
[008] Figure 2 shows signal diagrams of the signals at selected points of the power amplifier circuit in Figure 1.
[009] Figure 3 shows a circuit diagram of an RF current generator according to an exemplary modality.
[0010] Figure 4 shows a circuit diagram for an RF current generator according to another exemplary modality.
[0011] Figure 5 shows a circuit diagram of an RF current generator according to another exemplary modality.
[0012] Figure 6 shows a circuit diagram of an RF current generator according to another exemplary modality.
[0013] Figure 7 shows a circuit diagram of an adaptation network according to an exemplary embodiment.
[0014] Figure 8 shows a circuit diagram of an adaptation network according to another exemplary modality.
[0015] Figure 9 shows a circuit diagram of an adaptation network according to another exemplary modality.
[0016] Figure 10 shows a circuit diagram of an adaptation network according to another exemplary modality.
[0017] Figures 1 IA and 1 IB respectively show the supply voltage and polarization cascode vs. input power of the amplifier circuit comprising the components of Figures 1, 3, and 7.
[0018] Figure 12 shows the output power, power gain, and PAE vs. input power of the amplifier circuit comprising the components of Figures 1, 3, and 7.
[0019] Figures 13A and 13B show respectively the output power and PAE vs. frequency of the amplifier circuit comprising the components of the Figures
[0020] Figures 14A and 14B show the gain error and phase error vs. input power of the amplifier circuit comprising the components of Figures 1, 3, and 7.
[0021] Figures 15A and 15B show respectively the gain error and phase error vs. output power of the amplifier circuit comprising the components of Figures 1, 4, and 7.
[0022] Figures 16A and 16B show respectively the output power and PAE vs. frequency of the amplifier circuit comprising the components of Figures 1, 4, and 8.
[0023] Figure 17 shows an exemplary transmitter application of the power amplifier described here. DETAILED DESCRIPTION
[0024] The power amplifier described here comprises a single-stage amplifier that uses a cascode-derived cross-coupling topology along with a technique of applying an RF injection current to a broadband node to provide a stage power amplifier single. In one embodiment, the power amplifier exhibits a peak of 64% PAE, 29 dBm output power, and a 20.5 dB gain over a 2 GHz radio frequency band. Figure 1 shows an exemplary embodiment of a circuit 100 power amplifier configured to obtain these results. Amplifier circuit 100 comprises a cross-coupled cascode transistor unit 110 comprising a pair of cross-coupled cascode transistors 112, a cross-coupled switching transistor unit 120 comprising a pair of cross-coupled switching transistors 122, and an RF current generator 130. Generally speaking, the RF current generator 130 generates a differential RF injection current based on a differential input signal. The switching transistor unit 120 amplifies the injection current to generate an amplified injection current at the wideband node of the amplifier circuit, i.e. the source nodes of the cascode transistors 112. The cascode transistor unit 110 further amplifies the current of injection to generate the desired amplified signal at the output 220 of the amplifier circuit 100, for example, at the drain nodes of the cascode transistors 112. The amplitude of the output signal generally depends on the differential injection current and the supply voltage Voo applied to the circuit power amplifier 100. As shown in Figure 1, a matching network 200 can be coupled to output 220 of amplifier circuit 100 to match the impedance of amplifier circuit 100 to that of an external element, e.g., an antenna (not shown). Although not required, it will be appreciated that the supply voltage VOO can be applied to the power amplifier circuit 100 through the adaptive network 200, as shown in Figure 1. It will be appreciated that the transistors used to implement the power amplifier circuit 100 may comprise any other type of transistor, including, but not limited to, NMOS, CMOS, BiCMOS, HBT, and III-V transistor technology (including Bipolar and FET).
[0025] The enhanced operation of the amplifier circuit 100 relies on the cross-coupling configurations of transistor units 110, 120 and shunt capacitors 114 of transistor cascode unit 110. As shown in Figure 2 and explained in more detail here, this This configuration causes a B signal at the source node of a transistor cascode 112 to have the same amplitude, but be out of phase, as an A signal at the gate node of the same transistor cascode 112 and a C signal at a drain node. opposite switching transistor 122. To further explain the details of power amplifier circuit 100, the following description considers each RF current generator 130, switching transistor unit 120, and cascode transistor unit 110 separately.
[0026] The RF current generator 130 generates a differential injection current IRF , IRF_ based on a differential input signal Dr, D_ . Figures 3-6 show various modalities of exemplary RF current generators 130. It will be appreciated, however, that current generators other than those shown here can also be used.
[0027] The RF current generator 130 shown in Figure 3 comprises a pair of injection transistors 132 configured to generate the differential RF injection current at the drain nodes from an input signal comprising an analog RF differential voltage signal applied to port nodes. In this mode, the injection transistors 132 are configured to operate as voltage-to-current converters. To supply the RF differential injection current to the remainder of amplifier circuit 100, the drain node of each injection transistor 132 couples to the drain node of the corresponding switching transistor 122 and the source node of the corresponding cascode transistor 112.
[0028] An alternative embodiment of the RF current generator 130 may comprise a mixer configured to generate the RF differential injection current from a local RF oscillator signal and an input signal comprising a baseband differential input signal. In this embodiment, the upconversion to RF occurs within the amplifier circuit 100, this eliminates the need for any upconversion outside the amplifier circuit 100. It will be appreciated that implementing the upconversion within the amplifier circuit 100 provides a more linear result, relative to to upconversion and power amplification. Furthermore, these mixers advantageously eliminate the need to separate RF drivers and other RF circuitry, which often have high dynamic range requirements.
[0029] For example, Figure 4 shows an RF current generator 130 comprising a transconductance mixer configured to generate the differential RF injection current at the RF current generator outputs from a local RF oscillator (LO) signal and an input signal comprising a differential baseband (BB) input current. The RF current generator 130 of Figure 4 comprises a first pair of baseband transistors 134, a second pair of baseband transistors 135, and a pair of local oscillator transistors 136, e.g., NMOS transistors 136. the drain node of one of the local oscillator transistors 136 couples to the corresponding transistor source nodes of the first and second baseband transistor pairs 134, 135, and the drain node of the other local oscillator transistor 136 couples to the source nodes from the other between the first and second pairs of baseband transistors 134, 135, as shown in Figure 4. The drains of the first pair of baseband transistors 134 are also cross-coupled with the drains of the second pair of baseband transistors 135. The positive input current signal D1 = BB is applied to the gate node of each first pair of baseband transistors 134 and the negative input current signal D = BB_ is applied. connected to the gate node of each second pair of baseband transistors 135. The positive and negative local oscillator signals are applied to the gate nodes of respective transistors of the pair of local oscillator transistors 136. As a result, the input signal The differential baseband injection is upconverted to the LO frequency to generate the differential injection current RF IRF, ,'RF- at the drain nodes of the baseband transistors 134, 135.
[0030] In another examples of mixer, the RF current generator 130 comprises a differential Quadrature mixer comprising a in-phase mixing unit 138 and a quadrature-phase mixing unit 140, as shown in Figure 5. In this embodiment, the input signal comprises a baseband input signal having a differential phase portion BB, BB,_ and a differential Quadrature phase portion BBQ+, BBo_ , where the differential outputs of each mixing unit 138, 140 are subjected to cross-coupling to combine the in-phase and Quadrature-phase output portions to provide IRE+ on one output and /RF on the other output. The phase mixing unit 138 mixes the differential phase portion BB, BB, with the differential phase local oscillator signal to generate the differential phase current RF IRF i+, IRF r- . The quadrature phase mixing unit 140 mixes the quadrature differential phase portion BBo, , BBQ with the differential quadrature phase local oscillator signal to generate the differential quadrature phase current RF /aF Q+, /RF o- . The differential outputs of each mixing unit 138, 140 are cross-coupled to combine the positive in-phase and Quadrature-phase portions of the output, IRF r+ and IRF Qy , to provide IRF+ in one output, and to combine the portions into negative phase and phase in Quadrature output, /RF ,- and IRF Q to provide IRF- on the other output.
[0031] In yet another example of mixer shown in Figure 6, the RF current generator 130 comprises a digital-analog converter/mixer. In this embodiment, the input signal comprises a digital baseband input signal, and the RF current generator 130 upconverts the bits of the digital baseband input signal based on the RF local oscillator signal to generate RF differential injection current IRF-, IRE- • An exemplary RF digital-to-analog converter is described in "A fully Digital Multimode Polar Transmitter Employing 17b RF DAC in 3G Mode" by Boos et al., and published in ISSCC 2011, Session 21, Cellular 21.7 (978-1-61284-3025/11), which is incorporated herein by reference. This exemplary RF digital-analog converter employs 10 a thermometer and 4 binary encoded bits with a high oversampling, utilizing a GHz band clock, and providing a full DAC resolution 17b in 3G mode, and 19b in EDGE mode. It will be appreciated that other RF digital to analog converters can also be used.
[0032] Again with reference to Figure 1, the cascode transistor unit 110 and the switching transistor unit 120 are described. The cascode transistor unit 110 comprises a pair of cascode transistors 112 subjected to cross coupling between the drain nodes and a pair of Cthp shunt capacitors 114 at the gate nodes. Shunt capacitors 114 are applied to the gate nodes to perform voltage division with the gate node capacitance (inherent in the gate node) to reduce gate voltage swing. For this purpose, the shunt capacitors 114 have a selected (adapted) capacitance to control the signal from the drain nodes subjected to cross-coupling applied to the gate nodes so that the amplitude of the gate node signal substantially equals the amplitude from the signal at the corresponding source node, or differs from the amplitude of the source signal at the corresponding source node by no more than 50%. This voltage split protects the cascode transistors 112 from oxide overvoltage, reduces the capacitive loading of the adaptive network 200, and allows the desired amount of mesh gain to be provided for auto-oscillation. The cross coupling between the cascode 112 transistors switches the phase of the signals applied to the gate nodes, for example, by 180 0. As a result, the amplitudes at the gate and source nodes can be substantially equal, but the signals at these nodes are out of phase. This results in only half the loads due to the parasitic capacitances Cpar,s which are dissipated to ground, eg ground signal ground, as compared to a classic cascade structure. Furthermore, this configuration reduces the signal oscillation and impedance of the source nodes of the cascode transistors 112, this alleviates the voltage effort and output power requirements of the switching transistors 122. Additionally, the use of a cascode-derived transistor structure subjected to cross-coupling, as shown in Figure 1, ensures that the gate node oscillation of the cascade transistors 112 tracks the output at the drain nodes over the entire bandwidth.
[0033] The switching transistor unit 120 comprises a pair of switching transistors 122 subjected to cross coupling between the drain and gate nodes. The differential current output by the drain nodes of the cross-coupled switching transistors 122 increases the injection current IRr , this results in a larger blocking range at a wideband node of the power amplifier circuit 100, ie, the source nodes of the cascode transistors 112. Furthermore, when the switching transistors 122 are turned on (for example, when the output power exceeds some threshold) most of the injection current is conducted through the cascode transistors 112. output is low (eg below threshold) switching transistors 122 are turned off. When the RF current generator 130 comprises the injection transistors 132 of Figure 3, the cross-coupling configuration of the switching transistors allows the size of the injection transistors 132 to be reduced as long as the injection transistors 132 remain large enough that switching transistors 122 maintain a switching mode of operation.
[0034] The wideband impedance at the node of the cascode transistors 112 combined with the switching properties of the switching transistors 122 (and in some cases, the injection transistors 132) provides square wave current and voltage signals with slanted edges at the source nodes of transistors cascode 112. Due to the fact that voltage and current are not simultaneously high except during injection by current generator 130, the resulting losses due to switching transistor unit 120 and current generator 130 are dominated by the injection current output by the RF current generator 130.
[0035] As shown in Figure 1, the power amplifier circuit 100 can be coupled to a matching network 200 configured to match the output impedance of the amplifier circuit 100 to that of an external load (not shown). Figures 7-10 show exemplary matching networks 200. It will be appreciated that the present invention is not limited to the shown matching networks 200.
[0036] Figure 7 shows an exemplary adaptation network 200 comprising the load, represented by RL , Cp , and LP, and the reactive components represented by Ls, LD, and Cs.
[0037] LS and Cs are connected as a resonance circuit in series with the external load, this results in a negative (capacitive) reactance for low frequencies and a positive (inductive) reactance for high frequencies. Lo comprises a current source. At low frequencies Lo is short, while at high frequencies Coa,d (in amplifier circuit 100) is short. Thus, the reactive components Lo and Coar d set the bandwidth limit over which the power amplifier can be efficient using the adaptive network 200 of Figure 7.
[0038] In some embodiments, it may be desired to provide a generally constant impedance to the drain nodes of the cascode transistors over a wide frequency range. As used here, generally constant could mean really constant, however the impedance is more likely to have some variation, with, for example, no more than 5% variation over the required or desired wideband frequency range. In other cases, a 1% variation may be required, while in still other cases 2%, 10%, 20%, or something in between is acceptable. Acceptable variation must be affected by the components, specific values, or operating conditions of the circuit. Preferably, the limited variation applies over the entire required or desired wideband frequency range. However, there may be frequency ranges where greater variation is acceptable. The total length of these gaps preferably constitutes no more than 20% of the required or desired wideband frequency range. In some cases, however, a total interval length relative to the broadband frequency range of 10%, 5%, 2%, 1%, or something in between may be required. Figure 8 shows an alternative higher order adaptive network 200 configured to provide a generally constant impedance. In this modality, the adaptation network 200 comprises a charge represented by Rs, and the reactive components represented by Cs, Ls, Lot, LD2, and co. In the adaptation network 200 of Figure 8, a first reactance unit comprises LDI and L02, which are coupled in series between the ground signal, which may, for example, correspond to the supply voltage VDD, and each drain node of the unit. of transistor cascode 110. A second reactance unit comprises Cs and LS serially coupled between a load resistor RL and each drain node of transistor cascode unit 110. A third reactance unit comprises at least one capacitor co coupled to a node between RL and Cs, and at the other node between the LOI and L02 inductors of the first reactance unit. The inductors of the first reactance unit generate a first high positive reactance at low frequencies, this keeps losses low, even at low frequencies, where a single inductor is considered short, and a second positive reactance at high frequencies. The second reactance unit generates a negative reactance at low frequencies and the third positive reactance high at high frequencies. As the operating frequency increases, Cpar,d (in amplifier circuit 100) is short, this results in increased power consumption. By reducing the reactance between the drain nodes of transistors cascode 112, for example, using the capacitor(s) co of the third reactance unit, such a short at higher frequencies, the effect of CPa, d decreases (this is effectively canceled). These reactance properties produce higher impedances in the drains of cascode 112 transistors, and therefore increase bandwidth and efficiency relative to frequency.
[0039] Figures 9 and 10 show other adaptation networks 200 comprising a transformer 230. In Figure 9, the transformer 230 is configured as a balun, where one side of the transformer is differentially connected to the power amplifier circuit 100 and the other side connects to the RL load with a single termination. In Figure 10, one side of the transformer is differentially connected to power amplifier circuit 100 while the other side is differentially connected to load RL. The performance of the adaptation networks 200 in Figures 9 and 10 is generally the same, and is generally comparable to that of the adaptation networks 200 of Figures 7 and 8. Furthermore, due to the fact that the adaptation network 200 of Figure 10 is not a balun, an additional balun might be needed before the antenna for this modality.
[0040] Figures 11-16 show various simulation results of exemplary modalities of the power amplifier described here. For example, Figures 11-14 show the parameter and performance results of a power amplifier configuration comprising the power amplifier circuit 100 of Figure 1, the RF current generator 130 of Figure 3, and the adaptive network 200 of Figure 7. Figures 1 IA and 1 IB respectively show the supply voltage (Voo) and the cascode bias voltage (8) in relation to the input power. For lower output power levels (linear operating mode), the supply voltage was kept constant at 0.48 V. As the input power increases, the supply voltage increases to allow more height for the output signal . As shown in Figure 1 IA, the supply voltage is 3.0 at peak input power. Figure 1 IB shows that the cascode bias voltage has similar characteristics to the supply voltage, except that the values originate from 0.865 V for linear operating mode at a maximum bias of 1.9 V.
[0041] Figure 12 shows the output power, gain, and PAE results as a function of input power at 2 GHz. As shown in Figure 12, output power tracks input power linearly, this is also demonstrated by stable gain response. The PAE peaks at 64%. When input power is backed up by 16 dB, PAE reduces to 37%. Considering the power range, Figure 12 demonstrates that the power amplifier operates beyond an 80 dB range, this satisfies WCDMA requirements.
[0042] Figures 13A and 13B show the frequency response of the output power and PAE for different input powers. At peak output power, Figure 13A demonstrates that the -3 dB bandwidth of the power 100 amplifier circuit is 1.2 GHz (between 1.4 and 2.6 GHz). Figure 13A further demonstrates that bandwidth increases for lower input powers. Furthermore, Figure 13B demonstrates that the PAE at peak output power is above 50% between 1.6 GHz and 2.6 GHz. When the output power is moved back by 18 dB, the PAE is at a constant value of 20% on bandwidth frequencies, and is quickly applied out of bandwidth.
[0043] Finally, Figures 14A and 14B show the linearity of the gain error and phase error, this was measured statically through the output power range WCDMA range of approximately 80 dB. As shown in Figure 14A, the power amplifier circuit 100 has a gain error of 0.2 dB over the entire range and a linear gain during class AB operations. For the AM-PM conversion (Figure 14B), this represents how much the phase changes as the amplitude changes, the total phase error is 170 over the entire output power range. The total error (AM-AM and AM-PM) in the power amplifier is within a range of pre-changeable values.
[0044] Figures 15A and 15B show linearity performance results of the power amplifier comprising the power amplifier circuit 100 of Figure 1, the RF current generator 130 of Figure 4, and the adaptation network 200 of Figure 7. Figure 15A demonstrates that the gain error degrades slightly when the transconductance amplifier replaces the injection transistor mode of the RF current generator 130, but the total phase error increases to almost 1 0 (Figure 15B). Again, the total error (AMAM and AM-PM) in the power amplifier is within pre-changeable values.
[0045] Figures 16A and 16B show the frequency response of the output power and the PAE of the power amplifier comprising the power amplifier circuit 100 of Figure 1, the RF current generator 130 of Figure 4, and the network of adaptation 200 of Figure 8. At peak output power, Figure 16A demonstrates that the -3 dB bandwidth of the power 100 amplifier circuit is 2.0 GHz (between 0.6 and 3.6 GHz). Figure 16A further demonstrates that the bandwidth remains the same or increases for lower input powers. Furthermore, Figure 16B demonstrates that the PAE at peak output power is above 50% between 0.6 GHz and 3.4 GHz. When the output power is moved back by 18 dB, the PAE is at a constant value of approximately 20% for frequencies between 0.7 and 2.5 GHz.
[0046] The power amplifier circuit described here comprises a switched mode RF power amplifier (SMPA). In an SMPA RF, switching typically dominates losses, for example, in energy dissipation due to charge and discharge capacitances between supply and ground. Using a tuned circuit, for example an LC oscillator, the reactive energy can be switched between capacitors and inductors in the adaptive network 200, instead of being dissipated in the switching resistors at each RF cycle. Some losses remain, however, due to inductor and capacitor losses, and due to non-zero currents and voltages in cascode transistors 112 and switching transistors 122. To reduce these losses, capacitance can be reduced, resulting in a low Q when connected to the resistive output load, and a wide bandwidth. For example, by integrating the cascode capacitances into the adaptive network 200, as shown in Figures 1 and 7 or 8, the losses can be reduced.
[0047] The power amplifier circuit 100 described here can be implemented in the STMicroelectronics 65 nm CMOS process with eight metal layers and MIM capacitors. In an exemplary embodiment, cascode 112 transistors can be implemented using 2.5 V thick oxide 1/0 devices. In an exemplary layout, all transistors are represented in a common centroid layout to reduce mismatch. Because the area of each individual transistor is also large, the resulting mismatch is small. In one implementation, the resulting chip has a chip area of 0.52x0.48 mmz, including pads.
[0048] It will be appreciated that the power amplifier circuit 100 described here also provides a single stage amplifier solution using 65 nm CMOS to obtain, in one modality, a bandwidth of 2 GHz, 29 dBm output power, 20 .5 dB of gain, and 64% of PAE. These performance results are as satisfying as some previous multi-stage solutions, and are generally better than most previous amplifier solutions.
[0049] Although not required, the power amplifier 100 and adaptation network 200 described here can be used in a Hybrid Envelopment Elimination and Restoration (H-EER) system, as shown in Figure 17, where the amplifier operates as a Mixed Mode Power Amplifier (MMPA). In this example, MMPA refers to operating the amplifier as a self-oscillating Switched Mode Power Amplifier (SMPA) for high output power levels, and as a linear class AB power amplifier for low output power levels, for example, when the power amplifier is not the main power consumer.
[0050] This increases the power range of the system, overcoming one of the main problems of SMPAs, which is their unsatisfactory power range. These enhancements are important for WCDMA operation, which has an 80 dB power control range.
[0051] The present invention can, of course, be carried out in other ways than those specifically presented herein without abandoning the essential features of the invention. The present embodiments are to be considered in all respects as illustrative and not restrictive, and all changes which are within the meaning and equivalence range of the appended claims are intended to be covered therein.

权利要求:
Claims (17)
[0001]
1. Power amplifier circuit (100), characterized in that it comprises: a current generator (130) configured to generate a radio frequency differential injection current at differential current generator (130) outputs based on a signal of Entrance; a pair of switching transistors (122) subjected to cross coupling, each including a source node, a gate node, and a drain node, the pair of switching transistors (122) subjected to cross coupling so that the the drain node of each of the switching transistors couples to the gate node of the other switching transistor, wherein the drain nodes are coupled to the differential current generator (130) outputs; a pair of cascode transistors (112) subjected to cross coupling, each including a source node, a gate node, and a drain node, said pair of cascode transistors (112) subjected to cross coupling so that the node of each of the cascode transistors (112) couples to the gate node of the other cascode transistor (112) via corresponding first and second shunt capacitors (114), wherein the source nodes of the cascode transistors (112) mate couple to the corresponding drain nodes of the switching transistors (122) and the differential current generator outputs, and wherein the pair of cascode transistors (112) subjected to cross coupling is configured to generate a differential amplified output signal at the nodes of cascode transistors drain (112) based on a supply voltage operatively coupled to the cascode transistors drain node (112) and differential injection current.
[0002]
2. Amplifier circuit (100) according to claim 1, characterized in that the input signal comprises an analog differential radio frequency input voltage signal and the current generator (130) comprises a pair of transistors of injection transistors (132), each comprising a source node, a gate node, and a drain node, wherein the drain node of each injection transistor (132) couples to the drain node of one of the injection transistors. corresponding switching (122) and the source node of one of the corresponding cascode transistors (112), and wherein the source nodes of each injection transistor (132) couple to the source node of one of the switching transistors (122) corresponding injection transistors (132) configured to convert the differential input voltage signal applied to the gate nodes of the injection transistors (132) to the differential injection current output at the drain nodes of the injection transistors (132).
[0003]
3. Amplifier circuit (100) according to claim 1, characterized in that the input signal comprises a baseband differential input signal and the current generator (130) comprises a mixer configured to generate the current injection system based on the baseband differential input signal.
[0004]
4. Amplifier circuit (100) according to claim 3, characterized in that the mixer comprises a Quadrature mixer and the input signal comprises a baseband phase differential input signal and a differential input signal in baseband Quadrature phase, the Quadrature mixer is configured to generate the differential injection current based on a Quadrature phased radio frequency local oscillator signal, a phased radio frequency local oscillator signal, and the differential input signals in baseband phase and Quadrature phase.
[0005]
5. Amplifier circuit (100) according to claim 3, characterized in that the input signal comprises an analog baseband differential input signal and the mixer comprises a transconductance mixer that includes a pair of first transistors of baseband (134), a pair of second baseband transistors (135), and a pair of local oscillator transistors (136), wherein the transconductance mixer is configured to generate the differential based injection signal. in the baseband differential input signal and a differential radio frequency local oscillator signal.
[0006]
6. Amplifier circuit (100) according to claim 5, characterized in that the drain nodes of the local oscillator transistors (136) couple to the corresponding source nodes of the first baseband transistors (134) and the corresponding source nodes of the second baseband transistors (135), the differential local oscillator signal is applied to the gate nodes of the local oscillator transistors (136), the differential input signal is applied to the gate nodes of the first transistors of baseband (134), the source nodes of the first baseband transistors (134) couple to the corresponding source nodes of the second baseband transistors (135), the drain nodes of the first baseband transistors (135) base (134) emit the differential injection current, and the drain nodes of the first baseband transistors (134) cross-coupled with the drain nodes of the second baseband transistors (135).
[0007]
7. Amplifier circuit (100) according to claim 3, characterized in that the input signal comprises a digital baseband input signal and the mixer comprises a digital-analog radio frequency converter configured to generate the differential injection current based on the digital baseband input signal and a local radio frequency oscillator signal.
[0008]
8. Amplifier circuit (100) according to claim 1, characterized in that the switching transistors (122) are configured to amplify the differential injection current in order to apply an amplified differential injection current to the source nodes of the cascode transistors (112).
[0009]
9. Amplifier circuit (100) according to claim 1, characterized in that it further comprises an adaptation unit configured to adapt a load of the amplifier circuit (100) to an external circuit.
[0010]
10. Amplifier circuit (100) according to claim 9, characterized in that the adaptation unit is further configured to provide a generally constant impedance to the drain nodes of the cascode transistors (112) over a frequency range of broadband.
[0011]
11. Amplifier circuit (100) according to claim 9, characterized in that the adaptation unit comprises: a first reactance unit comprising two or more inductors serially coupled between a ground signal and the drain node of a cascode transistor (112) and between the ground signal and the drain node of the other cascode transistor (112), the first reactance unit being configured to generate a first positive reactance at low frequencies and a second positive reactance at high frequencies frequencies; a second reactance unit comprising at least one series capacitor and at least one series inductor serially coupled between a resistor and the drain node of each cascode transistor (112), the second reactance unit is configured to generate a negative reactance at low frequencies and a third positive reactance at high frequencies; and a third reactance unit comprising at least one control capacitor coupled to one node between the resistor and the series capacitor of the second reactance unit and at the other node between the inductors of the first reactance unit, the third reactance unit is configured to short at high frequencies to reduce a parasitic capacitance at the drain nodes of cascode transistors (112) at high frequencies; wherein said first, second, and third reactance units work together to provide generally constant impedance over the wideband frequency range.
[0012]
12. Amplifier circuit (100), according to claim 11, characterized in that the ground signal corresponds to the supply voltage.
[0013]
13. Amplifier circuit (100) according to claim 1, characterized in that the cascode transistors (112) comprise one of the laterally diffused metal oxide semiconductor transistors and the extended drain metal oxide semiconductor transistors, and wherein the switching transistors comprise one of the transistor technologies CMOS, BiCMOS, HBT, and III-V (Bipolar and FET).
[0014]
14. Amplifier circuit (100) according to claim 1, characterized in that the first and second shunt capacitors (114) have a capacitance selected to control an amplitude of a gate signal at the gate nodes of the cascode transistors (112) to substantially equal an amplitude of a source signal at the corresponding source nodes of the cascode transistors (112), or to differ from the amplitude of the source signal at the corresponding source node by no more than 50%.
[0015]
15. Amplifier circuit (100) according to claim 1, characterized in that the amplifier circuit (100) comprises a wideband CMOS power amplifier circuit.
[0016]
16. Adaptation unit configured to adapt a load of an amplifier circuit (100) to an external circuit, characterized in that said adaptation unit comprises: a first reactance unit comprising two or more inductors serially coupled between a signal of ground and a first output of the amplifier circuit (100) and between the ground signal and a second output of the amplifier circuit (100), the first reactance unit is configured to generate a first positive reactance at low frequencies and a second positive reactance at high frequencies; a second reactance unit comprises at least one series capacitor and at least one series inductor serially coupled between a resistor and the first and second amplifier outputs, the second reactance unit is configured to generate a negative reactance at low frequencies and a third positive reactance at high frequencies; and a third reactance unit comprising at least one control capacitor coupled to a node between the resistor and the series capacitor of the second reactance unit and at the other node between the inductors of the first reactance unit, said third reactance unit is configured to short at high frequencies to reduce a parasitic capacitance at the first and second outputs of the amplifier at high frequencies, where the first, second, and third reactance units work together to provide generally constant impedance over the range. frequency bandwidth.
[0017]
17. Adaptation unit according to claim 16, characterized in that the ground signal corresponds to the supply voltage.

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同族专利:

公开号 | 公开日

EP2740213A1|2014-06-11|

CN103748785B|2017-07-18|

US8554162B2|2013-10-08|

BR112014002542A2|2020-10-27|

EP2740213B1|2019-04-17|

WO2013017407A1|2013-02-07|

US20130033321A1|2013-02-07|

CN103748785A|2014-04-23|

EP2854288A2|2015-04-01|

EP2854288B1|2018-03-07|

EP2854288A3|2015-04-29|

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法律状态:
2020-11-10| B25G| Requested change of headquarter approved|Owner name: ERICSSON MODEMS SA (CH) |

2020-11-10| B06F| Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]|

2020-11-17| B06U| Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]|

2020-12-01| B25A| Requested transfer of rights approved|Owner name: ERICSSON AB (SE) |

2020-12-22| B25A| Requested transfer of rights approved|Owner name: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL) (SE) |

2021-03-09| B09A| Decision: intention to grant [chapter 9.1 patent gazette]|

2021-05-18| B16A| Patent or certificate of addition of invention granted|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 17/07/2012, OBSERVADAS AS CONDICOES LEGAIS. |

优先权:

申请号 | 申请日 | 专利标题

US13/197,022|2011-08-03|

US13/197,022|US8554162B2|2011-08-03|2011-08-03|High efficiency power amplifier|

PCT/EP2012/064032|WO2013017407A1|2011-08-03|2012-07-17|A high efficiency power amplifier|

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