CHAIN MOVEMENT SPECIFICATION BLOCKS

专利摘要:
chaining motion specification blocks. a summary for the storage class memory is provided that hides the details of the storage class memory implementation from a program, and provides a standard channel programming interface to perform certain actions, such as data movement control between main storage and storage class memory or storage class memory management.
公开号:BR112013031825B1
申请号:R112013031825-2
申请日:2012-05-10
公开日:2021-03-23
发明作者:Peter Kenneth Szwed；Kenneth James Oakes；Peter Grimm Sutton；Peter Dana Driever；Harry Yudenfriend；Steven Gardner Glassen
申请人:International Business Machines Corporation；
IPC主号:

专利说明:

[0001] [0001] One or more aspects of the present invention relate, in general, to the auxiliary storage of a computing environment, and in particular, to the management of auxiliary storage aspects.
[0002] [0002] A computing environment can include main storage (also known as main memory), as well as auxiliary storage. Main storage is storage accessible to a processor that can be randomly addressed by, for example, an absolute address. Main storage is considered to be fast access storage compared to auxiliary storage, such as direct access storage devices (DASD) or storage class memory. In addition, addressing the main storage is considered simpler than addressing DASD or storage class memory.
[0003] [0003] Storage class memory, which is an external storage space outside of classic main storage, provides faster access than direct access storage devices. Unlike DASD, storage class memory is not typically implemented as mechanical arm rotating disks, but instead, non-mechanical solid-state parts. Typically, storage-class memory is implemented as groups of solid-state devices connected to a computing system through various input / output (I / O) adapters, which are used to map technology from an I / O device to the memory bus of the central processing units. Summary of the Invention
[0004] [0004] The disadvantages of the prior art are overcome and advantages are provided through the provision of a computer program product to execute a Start Subchannel instruction in a computing environment comprising main storage and storage class memory. The computer program product includes a computer-readable storage medium readable by a processing circuit and storage instructions for execution by the processing circuit to carry out a method. The method includes, for example, in response to determining that a subchannel identified by the Start Subchannel instruction is an Asynchronous Data Movement (ADM) subchannel, which performs: obtaining an operation request block from main storage, the operation request block comprising an address of an operation block; based on the address of the operating block, obtaining the operating block from main storage, the operating block consisting of a request block, a response block, and one or more first movement specification blocks (MSBs), where the request block comprises an MSB count field having a value indicating the number of one or more first MSBs included in and referenced by the operation block, where the response block is configured to retain exception conditions, in that each first motion specification block is configured to include a first opcode field, a first block count field, a first main storage address field, a first storage class memory address field, a first block size field and a first marker field; obtaining a first movement specification block of the one or more first movement specification blocks, wherein the first marker field of the first movement specification block comprises a branch indicator for the next MSB (BNM); in response to the BNM indicator having a first BNM value, performing an operation based on a first operation code in the first movement specification block obtained, the operation that is performed on a number of storage class memory blocks. a size determined by the first block size field, where the number of blocks is determined from the first block count field; and in response to the BNM indicator having a second BNM value: branching to a second MSB located at an address specified by the first main storage address field of the first MSB, where the second MSB includes a second block size field , a second block count field and a second operation code; and performing an operation based on the second operation code on the second obtained MSB, the operation which is performed on a number of storage class memory blocks of a size determined by the second block size field, in which the number of blocks is determined from the second block count field.
[0005] [0005] Methods and systems that refer to one or more aspects of the present invention are also described and claimed here. In addition, services that refer to one or more aspects of the present invention are also described and can be claimed here.
[0006] [0006] Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail here and are considered a part of the claimed invention. Brief Description of the Various Views of the Drawings
[0007] [0007] One or more aspects of the present invention are particularly highlighted and claimed distinctly as examples in the claims at the conclusion of the specification. The foregoing objectives and other objectives, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
[0008] [0008] Figure 1A represents an embodiment of a computing environment to incorporate and use one or more aspects of the present invention;
[0009] [0009] Figure 1B represents another embodiment of a computing environment for incorporating and using one or more aspects of the present invention;
[0010] [0010] Figure 2A represents an embodiment of an Extended Asynchronous Data Movement operation request block used in accordance with an aspect of the present invention;
[0011] [0011] Figure 2B represents an embodiment of an Extended Asynchronous Data Movement operation block used in accordance with an aspect of the present invention;
[0012] [0012] Figure 2C represents an embodiment of an Extended Asynchronous Data Movement request block used in accordance with an aspect of the present invention;
[0013] [0013] Figure 2D represents an embodiment of an Extended Asynchronous Data Movement response block used in accordance with an aspect of the present invention;
[0014] [0014] Figure 2E represents an embodiment of an Extended Asynchronous Data Movement movement specification block used in accordance with an aspect of the present invention;
[0015] [0015] Figure 2F represents an embodiment of an extended Asynchronous Data Movement indirect data address word used in accordance with an aspect of the present invention;
[0016] [0016] Figure 3A represents an embodiment of a Start Subchannel instruction used in accordance with an aspect of the present invention;
[0017] [0017] Figure 3B represents an embodiment of the logic associated with the Start Subchannel instruction, in accordance with an aspect of the present invention;
[0018] [0018] Figure 3C represents an embodiment of a Clean Subchannel instruction used in accordance with an aspect of the present invention;
[0019] [0019] Figure 3D represents an embodiment of a Test Subchannel instruction used in accordance with an aspect of the present invention;
[0020] [0020] Figure 3E represents an embodiment of a Modification Subchannel instruction used in accordance with an aspect of the present invention;
[0021] [0021] Figure 3F represents an embodiment of a Storage Subchannel instruction used in accordance with an aspect of the present invention;
[0022] [0022] Figure 4A represents an embodiment of an Extended Asynchronous Data Movement subchannel information block used in accordance with an aspect of the present invention;
[0023] [0023] Figure 4B represents an embodiment of an Extended Asynchronous Data Movement path control word used in accordance with an aspect of the present invention;
[0024] [0024] Figure 4C represents an embodiment of a subchannel status word used in accordance with an aspect of the present invention;
[0025] [0025] Figure 4D represents an embodiment of an Extended Asynchronous Data Movement extended status word used in accordance with an aspect of the present invention;
[0026] [0026] Figure 5A represents an embodiment of a storage information class Memory Information request block used in accordance with an aspect of the present invention;
[0027] [0027] Figure 5B represents an embodiment of a Storage Class Memory Information response block used in accordance with an aspect of the present invention;
[0028] [0028] Figure 5C represents an embodiment of a storage class memory address list entry used in accordance with an aspect of the present invention;
[0029] [0029] Figure 5D represents an embodiment of the logic associated with the Storage class Memory Information command in accordance with an aspect of the present invention;
[0030] [0030] Figure 6A represents an example of a state diagram representing various storage class memory states according to an aspect of the present invention;
[0031] [0031] Figure 6B represents an embodiment of a state diagram showing operating states and data states according to an aspect of the present invention;
[0032] [0032] Figure 7A represents an embodiment of a Configuration storage class Memory order block used in accordance with an aspect of the present invention;
[0033] [0033] Figure 7B represents an embodiment of a Configuration storage class Memory response block used in accordance with an aspect of the present invention;
[0034] [0034] Figures 7C-7D represent an embodiment of the logic associated with a Configuration storage class Memory command used in accordance with an aspect of the present invention;
[0035] [0035] Figure 8A represents an example of a notification response block used in accordance with an aspect of the present invention;
[0036] [0036] Figure 8B represents an embodiment of a Storage Event Information request block used in accordance with an aspect of the present invention;
[0037] [0037] Figure 8C represents an embodiment of a Storage Event Information response block used in accordance with an aspect of the present invention;
[0038] [0038] Figure 9A represents an embodiment of an Unconfiguration storage class Memory order block used in accordance with an aspect of the present invention;
[0039] [0039] Figure 9B represents an embodiment of a storage class memory order request list entry used in accordance with an aspect of the present invention;
[0040] [0040] Figure 9C represents an embodiment of an Unconfiguration storage class Memory response block used in accordance with an aspect of the present invention;
[0041] [0041] Figures 9D-9E represent an embodiment of the logic associated with an Unconfiguration storage class Memory command used in accordance with an aspect of the present invention;
[0042] [0042] Figure 10 represents an embodiment of a computer program product incorporating one or more aspects of the present invention;
[0043] [0043] Figure 11 represents an embodiment of a host computer system for incorporating and using one or more aspects of the present invention;
[0044] [0044] Figure 12 represents a further example of a computer system for incorporating and using one or more aspects of the present invention;
[0045] [0045] Figure 13 represents another example of a computer system comprising a computer network to incorporate and use one or more aspects of the present invention;
[0046] [0046] Figure 14 represents an embodiment of several elements of a computer system to incorporate and use one or more aspects of the present invention;
[0047] [0047] Figure 15A represents an embodiment of the execution unit of the computer system of Figure 14 to incorporate and use one or more aspects of the present invention;
[0048] [0048] Figure 15B represents an embodiment of the branching unit of the computer system of Figure 14 to incorporate and use one or more aspects of the present invention;
[0049] [0049] Figure 15C represents an embodiment of the loading / storage unit of the computer system of Figure 14 to incorporate and use one or more aspects of the present invention; and
[0050] [0050] Figure 16 represents an embodiment of an emulated host computer system to incorporate and use one or more aspects of the present invention. Detailed Description of the Invention
[0051] [0051] According to one or more embodiments, an abstraction for storage class memory is provided that hides the details of the storage class memory implementation from a program (eg, operating system), and provides a standard channel programming interface to perform certain actions, such as controlling movement of data between main storage and storage class memory.
[0052] [0052] In one example, an installation is provided, referred to as an Extended Asynchronous Data Movement Installation (EADM), which allows programs to request the transfer of data blocks between main storage and storage class memory, as well as request other operations. Aspects of this installation are described in detail below.
[0053] [0053] Additionally, associated with the EADM Installation is an optional installation referred to as an EADM Release Installation. When installed, the EADM Release Facility provides a means for the program to specify that it no longer requires data retention in one or more blocks of storage class memory. It is model dependent on whether the release operation is supported for all storage class memory blocks or only a subset of storage class memory.
[0054] [0054] Once a block of storage class memory has been released, the program can transfer new data to the block, otherwise subsequent requests to transfer data from the block to the main storage will not be successful.
[0055] [0055] An embodiment of a computing environment to incorporate and / or use one or more aspects of the present invention is described with reference to figure 1 A. Computing environment 100 is based, for example, on z / Architecture® offered by International Business Máquinas Corporation (IBM®), Armonk, New York. An embodiment of z / Architecture® is described in an IBM® publication entitled "z / Architecture Principles of Operation" IBM Publication No. SA22-7832-08, August 2010, which is incorporated herein by reference in its entirety. In one example, a z / Architecture®-based computing environment includes the zEnterprise 196 (zl96) system offered by International Business Máquinas Corporation. IBM® and z / Architecture® are registered trademarks, and zEnterprise 196 and zl96 are registered trademarks of International Business Máquinas Corporation, Armonk, New York, USA. Other names used here may be trademarks, brand or product names of International Business Máquinas Corporation or other companies.
[0056] [0056] As an example, computing environment 100 includes one or more central processing units 102 coupled with main memory 104 via one or more buses 106. One or more of the central processing units can run an operating system 108, such as the z / OS operating system offered by International Business Máquinas Corporation. In other examples, one or more of the central processing units can run other operating systems or no operating systems at all. z / OS® is a registered trademark of International Business Máquinas Corporation, Armonk, New York, USA.
[0057] [0057] Central processing units 102 and main memory 104 can be additionally coupled with an I / O hub 120 via one or more connections 122 (for example, busbars or other connections). The I / O hub provides connectivity with one or more I / O adapters 130, which are additionally coupled with one or more solid-state devices 140. The adapters and solid-state devices are an implementation of storage class memory ( for example, flash memory). The I / O cube is part of an I / O subsystem 145 facilitating one or more aspects of an embodiment.
[0058] [0058] In a further embodiment, as depicted in figure 1B, a computing environment 150 may include a central processing complex (CPC) 152, which is based on z / Architecture® offered by International Business Máquinas Corporation. The central processing complex 152 includes, for example, one or more partitions 154, a hypervisor 156, one or more central processors 158, and one or more components of an input / output subsystem 160. In this example, partitions 154 are partitions logic (for example, LPARs), each of which includes a set of system hardware resources, virtualized as a separate system.
[0059] [0059] Each logical partition 154 is capable of functioning as a separate system. That is, each logical partition can be restarted independently, initially loaded with an operation system or other control code, if desired, and operate with different programs. An operating system or application program that runs on a logical partition appears to have access to a full and complete system, but in reality, only a portion of it is available. A combination of hardware and licensed internal code (LIC), referred to as firmware, keeps a program in a logical partition from interfering with a program in a different logical partition. This allows several different logical partitions to operate on a single or multiple physical processors in a time-slice manner. As used here, firmware includes, for example, the processor's microcode, milicode and / or macrocode (or entity performing the processing). It includes, for example, hardware-level instructions and / or data structures used in the implementation of higher-level machine code. In one embodiment, it includes, for example, proprietary code that is typically distributed as microcode that includes trusted software or microcode specific to the underlying hardware and controls access from the operating system to the system hardware.
[0060] [0060] In this example, several logical partitions have a resident operating system (OS) 170, which can differ by one or more logical partitions. In one embodiment, at least one logical partition is running the z / OS® operating system, offered by International Business Máquinas Corporation, Armonk, New York.
[0061] [0061] Logical partitions 154 are managed by hypervisor 156, which is implemented by firmware running on central processors 158. Each of logical partitions 154 and hypervisor 156 comprises one or more programs that reside in respective portions of main memory 159 associated with the central processors. An example of hypervisor 156 is the Systems Manager / Processor Resource (PR / SM ™), offered by International Business Machinery Corporation, Armonk, New York.
[0062] [0062] Central processors 158 are physical processor resources that are allocated with logical partitions. For example, a logical partition 154 includes one or more logical processors, each of which represents all or part of a physical processor resource 158 allocated with the partition. The logical processors of a particular partition 154 can be both dedicated to the partition, so that the underlying processor resource is reserved for that partition; or shared with another partition, so that the underlying processor resource is potentially available to another partition.
[0063] [0063] The input / output subsystem 160 (of which only a portion is represented) provides connectivity for storage class memory 180. In this example, an address space is provided for the storage class memory that presents the memory as flat, hiding the details of the physical implementation of the program. As an example, there is an address space in the system for storage class memory, but from the view of a configuration (for example, LPAR or in another embodiment, a virtualized guest) there is an address space in which increments of Storage class memory is populated for each system configuration. The storage class memory address space is separated from and away from the main storage address space.
[0064] [0064] In a particular example of z / Architecture®, the I / O subsystem includes a channel subsystem, which not only directs the flow of information between peripheral I / O control units (and devices) and main memory , but also between storage class memory and main memory. However, the I / O subsystem can be different than a channel subsystem.
[0065] [0065] In the case of a channel subsystem, subchannels are used to perform EADM operations. These subchannels are referred to as Asynchronous Data Movement (ADM) subchannels and are associated with EADM operations, not I / O devices, like other I / O subchannels. An ADM type subchannel does not contain a number device, nor does it contain channel path information The number of ADM-type subchannels provided for a configuration is model dependent.M ADM-type subchannels are addressed by a subsystem identification word (SID).
[0066] • Um ou mais subcanais do tipo ADM são providos que são usados para as operações de EADM. • Operações de EADM são designadas por um bloco de operação de EADM especificado (AOB) . O AOB inclui um bloco de pedido de EADM (AQB) e um bloco de resposta de EADM (A SB) , e designa uma lista de Blocos de especificação de movimento de EADM (MSBs) . Para uma operação de movimento, os MSBs contêm informação sobre os blocos de dados a ser movidos, tais como o tamanho dos blocos, as localizações de fonte e de destino dos blocos, e a direção do movimento dos dados. [0066] ADM-type subchannels are used by the Extended Asynchronous Data Movement Installation, which is an extension to the channel subsystem. As described here, installing EADM allows a program to request the transfer of data blocks between main storage and storage class memory, as well as perform other operations, such as emptying a block of storage class memory or releasing a block of storage class memory. In one embodiment, when the EADM Installation is installed: • One or more sub-channels of the ADM type are provided that are used for EADM operations. • EADM operations are designated by a specified EADM operation block (AOB). The AOB includes an EADM request block (AQB) and an EADM response block (A SB), and designates a list of EADM motion specification blocks (MSBs). For a move operation, the MSBs contain information about the data blocks to be moved, such as the size of the blocks, the source and destination locations of the blocks, and the direction of movement of the data.
[0067] • Um programa inicia operações de EADM emitindo uma instrução de Subcanal de Partida que designa um subcanal do tipo de ADM e um bloco de pedido de operação de EADM (ORB). Por sua vez, o ORB de EADM designa um AOB. A instrução passa os conteúdos do ORB de EADM para o subcanal designado. • Quando o Subcanal de Partida é emitido para iniciar operações de EADM, o subsistema de canal realiza de maneira assíncrona a operação especificada. • Como observado pelo programa, memória de classe de armazenamento aparece para ser o bloco concorrente em um tamanho de bloco mínimo dependente do modelo. O valor dependente do modelo é chamado do tamanho de concorrência de bloco de SCM. • Quando operações de EADM estão completas, uma interrupção de I/O é feita pendendo para o programa para o subcanal do tipo ADM em que as operações foram iniciadas. [0067] The maximum number of MSBs that can be specified by an AOB is dependent on the model. The maximum count of blocks that an MSB can specify to be moved or operated is also dependent on the model. • A program initiates EADM operations by issuing a Start Subchannel instruction that designates an ADM type subchannel and an EADM operation request block (ORB). In turn, the EADM ORB designates an AOB. The instruction passes the contents of the EADM ORB to the designated subchannel. • When the Start Subchannel is issued to initiate EADM operations, the channel subsystem performs the specified operation asynchronously. • As noted by the program, storage class memory appears to be the concurrent block in a model-dependent minimum block size. The model-dependent value is called the SCM block concurrency size. • When EADM operations are complete, an I / O interruption is made pending for the program for the ADM-type subchannel where the operations were initiated.
[0068] [0068] The EADM ORB includes the specification of a subchannel key and the address of the AOB to be used. AOB is designated, for example, at a limit of 4 K-bytes and can be up to 4 K-bytes in size. And more MSBs are needed than can fit on a 4-K-byte AOB, the AOB can specify a list of MSBs that is extended to additional storage areas using MSBs that designate the address of the next MSB in the list, instead of designating one. storage area to be used for data transfer.
[0069] [0069] The first EADM operation is initiated by the channel subsystem using information in the designated EADM ORB and ARQB in the designated AOB to fetch an MSB. The MSB includes information that specifies and controls the EADM operation to be processed.
[0070] [0070] Each EADM operation is represented by an MSB. An MSB may specify, for example, a transfer of data blocks from main storage to storage class memory; a transfer of data blocks from storage class memory to main storage; an emptying of storage class memory blocks; and the release of storage class memory blocks.
[0071] [0071] If the storage blocks to be transferred are not contiguous in the main storage, a new MSB can be used or the MSB can use indirect addressing by specifying a list of indirect EADM data address words (AIDAWs) to designate the blocks not contiguous.
[0072] [0072] As an MSB specifies the transfer of data in only one direction, a new MSB must be used when there is a change in the direction of the transfer.
[0073] [0073] The completion of an EADM operation is usually indicated by the combined state conditions of the channel end and device end. This state combination represents the primary and secondary state combination indicating that the subchannel is available for another start function after the state is released.
[0074] [0074] An EADM operation can be terminated prematurely by a Clean Subchannel instruction. The execution of the Released Subchannel instruction ends the execution of the AOB in the subchannel, releases the subchannel from the AOB indications in execution, and performs the emptying function asynchronously.
[0075] [0075] Additional details regarding the EADM ORB and related control structures are described below with reference to figures 2A to 2F. Initially, with reference to figure 2A, an embodiment of an EADM ORB is described.
[0076] [0076] As an example, an EADM 200 ORB includes:
[0077] [0077] Interrupt Parameter 202: This field is preserved unmodified in the subchannel until it is replaced by a subsequent Modification Subchannel or Start Subchannel Instruction. These bits are placed in the I / O interrupt code when an I / O interrupt occurs for the subchannel and when an interrupt request is released by executing, for example, a Pending Test Interrupt.
[0078] [0078] Subchannel Key 204: This field forms the Subchannel Key for the EADM operations specified by the ARQB and applies to fetch the ARQB, search for MSBs, store the ARSB, and to evaluate the main storage for data transfer. The value of this field is a defined value; otherwise, either a program check condition is recognized by the channel subsystem or an operand exception is recognized.
[0079] [0079] ORB Extension Control (X) 205: This field specifies whether the ORB is extended. This field is a specified value when a subchannel of the ADM type is assigned; otherwise, both an operand exception and a program check condition are recognized.
[0080] [0080] EADM operation block (AOB) address 206: This field specifies an EADM operation block (AOB) address. If certain bits in this field do not include a defined value, then both an operand exception and a program check condition are recognized.
[0081] [0081] If this field designates a location protected against search or designates a location outside the configuration, the start function is not started. In this case, the subchannel becomes a pending state with a primary, secondary and alert status.
[0082] [0082] Channel Subsystem Priority (CSS) 208: This field includes a channel subsystem priority number that is assigned to the designated subchannel and used to order the selection of ADM-type Subchannels when a start function is to be started for one or more subchannels that are pending start.
[0083] [0083] Storage Class Memory (SCM) Priority 210: This field includes a storage class memory (SCM) priority number that specifies the priority level that is applied to all EADM operations associated with the role of departure.
[0084] [0084] It is dependent on the model if the contents of the SCM priority field are recognized by the EADM Installation. In models that do not recognize this field, the field contents are ignored and all EADM operations associated with the start function are assigned an implicit priority number.
[0085] [0085] Format (FMT) 212: This field specifies the ORB design. This field must include a specified value when a subchannel of the ADM type is designated; otherwise, an operand exception is recognized or a particular condition code is defined.
[0086] [0086] The EADM operation block (AOB) specified by the EADM 206 EADM AOB address of the EADM ORB includes the information used to invoke EADM operations. An AOB is allocated, in one example, to a 4K-byte limit and is variable in length.
[0087] [0087] In one example, as shown in figure 2B, an AOB of EADM 220 includes three sections: an EADM request block (ARQB) 222; an EADM response block (ARSB) 224; and an area of MSB 226 containing up to a defined number (e.g., 124) of MSBs. The ARQB can specify the use of more than the defined MSBs, however, when using the MSB branch (that is, using the branch for the next MSB marker in the MSB).
[0088] [0088] An embodiment of an EADM request block (ARQB) 222 is described with reference to figure 2C. In one example, ARQB 222 includes:
[0089] [0089] Format (FMT) 230: This field specifies the ARQB design. The value of this field is a defined value; otherwise, a program check condition is recognized by the channel subsystem and a command code error is indicated in the ARSB exception qualifier code field.
[0090] [0090] Command code 232: This field must specify the command of EADM movement blocks; otherwise, a program check condition is recognized by the channel subsystem and a command code error is indicated in the ARSB exception qualifier code field.
[0091] [0091] MSB count 234: This field specifies a count of MSBs that make up the EADM request. The maximum MSB count that can be specified is dependent on the model. The value of this field must be greater than zero and less than or equal to the maximum MSB Count value depending on the model; otherwise, a program check condition is recognized by the channel subsystem and an MSB Count error is indicated in the ARSB exception qualifier code field.
[0092] [0092] In addition to the EADM request block, the EADM ORB also specifies an EADM response block (ARSB). The EADM response block is significant, in this embodiment, only when an exception condition is recognized. Specifically, an ARSB is significant only when the alert state is present in the EADM subchannel status word (SCSW), the EADM extended status word (ESW) is significant, and the EADM response block storage bit ( R) is one in the extended EADM report (ERW) word, each of which is described below. When an ARSB is not significant, the contents of the ARSB in the AOB are unpredictable.
[0093] [0093] If a program stores in the ARSB while the associated subchannel is the active subchannel, unpredictable results can occur.
[0094] [0094] When an ARSB is stored, the amount of data that has been transferred, if any, is unpredictable.
[0095] [0095] An embodiment of an EADM response block is described with reference to figure 2D. In one example, ARSB 224 includes:
[0096] [0096] Format (FMT) 240: This field specifies the ARSB design. When an ARSB is stored, the value of this field is stored as a defined value.
[0097] [0097] Exception Markers (EF) 242: When an ARSB is stored, this field, when defined, specifies the exception reason for which the ARSB is stored. Example exception reasons include:
[0098] [0098] Program check: A programming error is detected.
[0099] [0099] Protection check: A storage access is prevented by the protection mechanism. The protection applies to the search for ARQB, MSB, AIDAWs, and data to be transferred to storage class memory, and for the storage of information in the ARSB and data transferred from storage class memory.
[0100] [0100] Channel data verification: An uncorrected storage error has been detected with respect to the data that is contained in the main storage and is currently used in the performance of an EADM operation. The condition can be indicated when detected, even if the data is not used when pre-fetched. The verification of channel data is indicated when data or the associated key has an invalid verification block code (CBC) in the main storage when the data is referenced by the channel subsystem.
[0101] [0101] Channel control check: Channel control check is caused by any malfunction of the machine that affects the controls of the channel subsystem. The condition includes invalid CBC in an ARQB, an ARSB, an MSB, an AID AW, or the associated associated key. The condition can be indicated when an invalid CBC is detected in a pre-fetched AID ARQB, MSB, AW or its associated key, even if that ARQB, MSB, or AID AW is not used.
[0102] [0102] Verification of installation of extended asynchronous data movement: An uncorrected error has been detected with respect to the data that is contained in the storage class memory and is currently used in the performance of an EADM operation.
[0103] • O bloco ou blocos de controle. • A área de dados de armazenamento principal. • A memória de classe de armazenamento. [0103] Exception Control Block Identifiers (ECBI) 244: When an ARSB is stored, this field is a multi-bit mask in which the bits, when set, specify any single component or combination of the following components that are associated with the recognized exception designated by the EF field: • The control block or blocks. • The main storage data area. • Storage class memory.
[0104] [0104] The bits that can be set represent, for example, an EADM motion specification block, an EADM indirect data address, data in main storage, and / or data in storage class memory.
[0105] [0105] The bits in the ECBI field describe the components associated with a single exception condition. If no component can be identified for the exception condition, this field contains, for example, zeros.
[0106] [0106] Field Validity Marker (FVF) 246: When an ARSB is stored, this field includes a multi-bit mask in which the bits indicate the validity of certain fields in the ARSB.
[0107] [0107] When a validity bit is set, the corresponding field has been stored and is useful for recovery purposes. The bits that can be set represent, for example, fault MSB address field, fault AID AW field, fault main storage address field, and / or fault storage class memory address field .
[0108] [0108] Exception Qualifier Code (EQC) 248: When an ARSB is stored, this field includes a code value that further describes the exception specified by the exception marker field. Code values can represent the following as examples:
[0109] [0109] No further description is provided. For this case, the Exception Control Block Identifiers (ECBI) field and those fields validated by the field validity markers field can identify the control blocks for which the exception is recognized.
[0110] [0110] Format Error: The format specified by the format field is reserved. For this case, the Exception Control Block Identifiers (ECBI) field and those fields validated by the field validity markers field can identify the control blocks for which the exception is recognized.
[0111] [0111] Command code error: The value specified in the ARQB command code field is not recognized.
[0112] [0112] MSB count error: The value specified in the ARQB MSB count field is zero or exceeds the maximum depending on the MSB model that can be specified.
[0113] [0113] Bookmark error: Bookmark bits specified by the bookmark field are reserved. For this case, the Exception Control Block Identifiers (ECBI) field and those fields validated by the field validity markers field can identify the control blocks for which the exception is recognized.
[0114] [0114] Operation code error: A reserved operation code value is specified. If the field of field validity markers indicates that the fault MSB address field is valid, the field contains the address of the MSB for which the exception is acknowledged.
[0115] [0115] Block size error: A reserved block size value is specified. If the field of field validity markers indicates that the fault MSB address field is valid, the field contains the address of the MSB for which the exception is acknowledged.
[0116] [0116] Block count error: The value specified in the block count field of an MSB is zero or exceeds the maximum count depending on the model of blocks that can be specified by an MSB. If the field of field validity markers indicates that the fault MSB address field is valid, the field contains the address of the MSB for which the exception is acknowledged.
[0117] [0117] Main storage address specification error: A main storage address is specified at an incorrect limit. Such an address can be designated by an MSB or an AW from AID. If the field of field validity markers indicates that the fault MSB address field is valid, the field contains the address of the MSB for which the exception is acknowledged. If the field of field validity markers indicates that the failure AID AW address field is valid, the field contains the AID AW address for which the exception is recognized. If the field of field validity markers indicates that the failure main storage address field is valid, the field contains the main storage address for which the exception is recognized.
[0118] [0118] Storage class memory address specification error: a storage class memory address is specified at an incorrect limit. Such an address is called an MSB. If the Field Validity Marker indicates that the failure MSB address field is valid, the field contains the address of the MSB for which the exception is acknowledged. If the field of field validity markers indicates that the failure AID AW address field is valid, the field contains the AID AW address for which the exception is recognized. If the field of field validity markers indicates that the failure storage class memory address field is valid, the field contains a storage class memory address for which the exception is recognized.
[0119] [0119] Main storage address exception: EADM Setup attempted to use an address that is not available in the configuration or wrapped around the maximum storage address. Such an address can be designated by an MSB or that results from the increment of main storage addresses during data transfer. If the field of field validity markers indicates that the fault MSB address field is valid, the field contains the address of the MSB for which the exception is acknowledged. If the field of field validity markers indicates that the failure AID AW address field is valid, the field contains the AID AW address for which the exception is recognized. If the field of field validity markers indicates that the failure main storage address field is valid, the field contains the main storage address for which the exception is recognized.
[0120] [0120] Storage class memory address exception: EADM Setup attempted to use a storage class memory address that is unavailable in the configuration. Such an address can be designated by an MSB or that results from the increase of storage class memory addresses during data transfer. If the field of field validity markers indicates that the fault MSB address field is valid, the field contains the address of the MSB for which the exception is acknowledged. If the field of field validity markers indicates that the failure AID AW address field is valid, the field contains the AID AW address for which the exception is recognized. If the field of field validity markers indicates that the failure storage class memory address field is valid, the field contains a storage class memory address for which the exception is recognized.
[0121] [0121] Main storage error: An uncorrected main storage error is detected. If the field of field validity markers indicates that the fault MSB address field is valid, the field contains the address of the MSB for which the exception is acknowledged. If the field of field validity markers indicates that the failure AID AW address field is valid, the field contains the AID AW address for which the exception is recognized. If the field of field validity markers indicates that the failure main storage address field is valid, the field contains the main storage address for which the exception is recognized.
[0122] [0122] MSB list error: AOB specifies an MSB list that crosses a 4K byte limit without specifying a branch to the next MSB (BNM) to cross the limit or the MSB is the last MSB in the specified MSB list and BNM is specified by the MSB. If the field of field validity markers indicates that the fault MSB address field is valid, the field contains the address of the MSB for which the exception is acknowledged.
[0123] [0123] MSB branching error: AOB specifies an MSB list in which an MSB (branch source MSB) specifies a branch for the next MSB (BNM) and the MSB that is a branch target also specifies BNM. If the field of field validity markers indicates that the failure MSB address field is valid, the field contains the address of an MSB branch source for which the exception is recognized.
[0124] [0124] AID AW list error: An MSB specifies an EADM indirect data address word list (AID AW) that crosses a 4K byte boundary without specifying branch to the next AID AW (BNA) for cross the line. If the field of field validity markers indicates that the fault MSB address field is valid, the field contains the address of the MSB for which the exception is acknowledged. If the field of field validity markers indicates that the failure AID AW address field is valid, the field contains the AID AW address for which the exception is recognized.
[0125] [0125] AID AW branching error: An MSB specifies an EADM indirect data address word list (AID AW) where an AID AW (branch source AID AW) specifies an AID AW branch to source (BNA) and the AID AW which is a branch target also specifies BNA. If the field of field validity markers indicates that the fault MSB address field is valid, the field contains the address of the MSB for which the exception is acknowledged. If the field of field validity markers indicates that the failure AID AW address field is valid, the field contains the branch AID AW address for source for which the exception is recognized.
[0126] [0126] Temporary storage class memory error: A recoverable storage class memory error is detected. If the Field Validity Marker field indicates that the failing MSB address field is valid, the field contains the address of the MSB for which the exception is recognized. If the field of field validity markers indicates that the failure AID AW address field is valid, the field contains the AID AW address for which the exception is recognized. If the field of field validity markers indicates that the failure storage class memory address field is valid, the field contains a storage class memory address for which the exception is recognized.
[0127] [0127] Release operation not supported error: A release operation has been specified for storage class memory for which the release operation is not supported. If the field of field validity markers indicates that the fault MSB address field is valid, the field contains the address of the MSB for which the exception is acknowledged. If the field of field validity markers indicates that the failure AID AW address field is valid, the field contains the AID AW address for which the exception is recognized. If the field of field validity markers indicates that the failure storage class memory address field is valid, the field contains a storage class memory address for which the exception is recognized.
[0128] [0128] Error reading data released: A read operation was specified for the storage class memory for which the last successful operation was a release operation. If the field of field validity markers indicates that the fault MSB address field is valid, the field contains the address of the MSB for which the exception is acknowledged. If the field of field validity markers indicates that the failure AID AW address field is valid, the field contains the AID AW address for which the exception is recognized. If the field of field validity markers indicates that the failure storage class memory address field is valid, the field contains a storage class memory address for which the exception is recognized.
[0129] [0129] Fault 250 MSB address: When a specified bit of the field validity markers field is set, this field indicates an MSB address for which an exception is recognized.
[0130] [0130] Fault AID AW address 252: When a specified bit of the field validity markers field is set, this field indicates an AIDAW address for which an exception is recognized.
[0131] [0131] Fault 254 main storage address: When a specified bit of the field validity markers field is set, this field indicates an address of the main storage block for which an exception is recognized.
[0132] [0132] Failure storage class 256 memory address: When a specified bit of the field validity markers field is set, this field includes the (for example, 64 bit) SCM address of the memory class block storage for which an exception is recognized.
[0133] [0133] In addition to the EADM request block and the EADM response block, the EADM operation block (AOB) also specifies one or more EADM motion specification blocks (MSBs). The AOB can contain up to, for example, 124 MSBs. However, the program can specify more than 12 4 MSBs by assigning a larger number of MSBs in the ARQB count field and using the branch to next MSB marker (BNM) to branch to a continuation of the MSB list. There may be multiple continuations on the MSB list, but in one embodiment, none of these continuations can cross a 4K-byte boundary without using BNM to cross that boundary. Continuations of the MSB list are not required to be contiguous. Each continuation of the MSB list, if designated to start at a 4K-byte limit, can contain up to 128 MSBs. The total number of MSBs in an MSB list is specified by the MSB count field in the ARQB.
[0134] [0134] An EADM motion specification block describes, for example, the storage blocks to be moved between main storage and storage class memory or an operation to be performed on a storage block. An embodiment of MSB 226 is described with reference to figure 2E, and includes, for example:
[0135] [0135] Format (FMT) 260: This field specifies the MSB design. The value of this field is a defined value; otherwise, an MSB Format error is indicated in the ARSB exception qualifier code field.
[0136] [0136] Operation code (OC) 262: This field specifies the operation to be performed. In an example when a specified bit of the marker field, described below, is a defined value, this field specifies the operation to be performed. Example operations include:
[0137] [0137] Release storage class memory: When this code is assigned, the storage class memory specified by a storage class memory address, block size, and block count field is released (for example, set to zeros). The main storage address field is meaningless for this operation.
[0138] [0138] Read: When this code is assigned, data is specified to be transferred from storage class memory to main storage. The block count, block size, main storage address and storage class memory address field have meaning for this operation.
[0139] [0139] Writing: When this code is assigned, data is specified to be transferred from main storage to storage class memory. The block count, block size, main storage address, and storage class memory address field have meaning for this operation.
[0140] [0140] Release: When this code is assigned and the EADM Release Facility is installed, the storage class memory specified by a storage class memory address, block size, and block count field is released. The main storage address field is meaningless for this operation. When the EADM Release Installation is not installed, this code is reserved.
[0141] [0141] If a reserved value is specified, a program check condition is recognized by the channel subsystem and an opcode error is indicated in the ARSB exception qualifier code field.
[0142] [0142] When the marker bit specified in the marker field is not the defined value, this field is reserved and not verified.
[0143] [0143] Markers 264: This field identifies one or more markers that can be defined. Marker bits that are reserved are set to a defined value; otherwise a marker error is indicated in the ARSB exception qualifier code field. Example labels include:
[0144] [0144] Branching to the next MSB (BNM): When defined, this marker indicates that the MSB does not specify an EADM operation and is not used to transfer data. Instead, the main storage address field specifies the address of the next MSB to be used to specify an EADM operation.
[0145] [0145] When the BNM marker is defined (for example, one) and the main storage address field specifies an MSB in which the BNM marker is also defined, a program check condition is recognized by the channel subsystem, the address of an MSB branch source is stored in the ARSB failure MSB address field, and an MSB branch error is indicated in the ARSB exception qualifier code field.
[0146] [0146] If an MSB ends at a 4K-byte limit, the AOB specifies additional MSBs, and the BNM marker is not defined, a program check condition is recognized by the channel subsystem, the MSB address is stored in ARSB failure MSB address field, and an MSB list error is indicated in the ARSB exception qualifier code field.
[0147] [0147] If an MSB is the last MSB in the specified MSB list and the BNM marker is defined, a program check condition is recognized by the channel subsystem, the MSB address is stored in the fault MSB address field ARSB, and an MSB list error is indicated in the ARSB exception qualifier code field.
[0148] • Endereçamento indireto: Quando definido, este marcador indica que o campo de endereço de armazenamento principal designa um endereço de uma palavra de endereço de dados indiretos de EADM (AW de AID) ou do primeiro AW de AID de uma lista de AIDAWs que designa a localização ou as localizações de armazenamento principal, respectivamente, a ser usadas para transferência de dados. Quando não definido, este marcador indica que o campo de endereço de armazenamento principal designa um endereço da localização de armazenamento principal a ser usada para transferência de dados. [0148] When the BNM marker is set, the remaining markers, the operation code field, the block size field, the defined block count field, and a storage class memory address are meaningless. • Indirect addressing: When defined, this marker indicates that the main storage address field designates an EADM indirect data address (AID AW) address or the first AID AW from a list of AIDAWs that designates the address. location or primary storage locations, respectively, to be used for data transfer. When not defined, this marker indicates that the primary storage address field designates an address for the primary storage location to be used for data transfer.
[0149] [0149] Block size (BS) 266: This field specifies the size and limit of the data blocks to be transferred to both main storage and storage class memory, or the size and limit of a memory block storage class to be operated (for example, emptied or released). Examples include:
[0150] [0150] 4K: When the code value is a defined value, the data blocks to be transferred are at a 4K-byte limit and are 4K-byte in size.
[0151] [0151] 1M: When the code value is another defined value, the data blocks to be transferred are at a limit of 1M-byte and are 1M-byte in size.
[0152] [0152] If a reserved value is specified, a program check condition is recognized by the channel subsystem and a block size error is indicated in the ARSB exception qualifier code field.
[0153] [0153] When the BNM marker is defined, this field is ignored.
[0154] [0154] Block count 268: This field includes a count of the data blocks to be transferred or operated (for example, emptied or released). Based on the block size field, this is the block count of both 4K-byte and 1M-byte.
[0155] [0155] The value of this field must be greater than zero and less than or equal to the maximum block count depending on the model that can be specified by an MSB; otherwise, a program check condition is recognized by the channel subsystem and a block count error is indicated in the ARSB exception qualifier code field.
[0156] [0156] When the BNM marker is defined, this field is reserved and not verified.
[0157] • Quando o campo de tamanho de bloco especifica blocos de 4K-byte, bits especificados deste campo contêm um valor definido (por exemplo, zero); de outra forma, uma condição de verificação de programa é reconhecida pelo subsistema de canal e um erro de especificação de armazenamento principal é indicado no campo de código qualificador de exceção do ARSB. • Quando o campo de tamanho de bloco especifica blocos de 1M-byte, bits especificados deste campo contêm um valor definido (por exemplo, zeros); de outra forma, uma condição de verificação de programa é reconhecida pelo subsistema de canal e um erro de especificação de armazenamento principal é indicado no campo de código qualificador de exceção do ARSB. [0157] Main storage address 270: When the operation code field has meaning (for example, the BNM marker is not defined) and specifies both a read operation and a write operation, and the indirect addressing indicator in the bookmark field is not defined, this field includes a primary storage address to be used for data transfer and the string applies: • When the block size field specifies 4K-byte blocks, specified bits of this field contain a defined value (for example, zero); otherwise, a program check condition is recognized by the channel subsystem and a master storage specification error is indicated in the ARSB exception qualifier code field. • When the block size field specifies 1M-byte blocks, specified bits of this field contain a defined value (for example, zeros); otherwise, a program check condition is recognized by the channel subsystem and a master storage specification error is indicated in the ARSB exception qualifier code field.
[0158] [0158] When the operation code field has meaning and specifies both a read operation and a write operation and the indirect addressing indicator in the marker field is defined, the field includes a primary storage address of an AID AW or the first in a list of AIDAWs to be used for data transfer. For this case, certain bits in this field contain a defined value; otherwise, a program check condition is recognized by the channel subsystem and a master storage specification error is indicated in the ARSB exception qualifier code field.
[0159] [0159] When the BNM marker is defined, the operation code has no meaning and the MSB does not specify an EADM operation. Instead, this field includes a primary storage address for the next MSB that specifies an EADM operation. For this case, specified bits of this field contain a defined value; otherwise, a program check condition is recognized by the channel subsystem and a master storage specification error is indicated in the ARSB exception qualifier code field.
[0160] • Quando o campo de tamanho de bloco especifica blocos de 4K-byte, bits especificados deste campo contêm um valor definido (por exemplo, zeros); de outra forma, uma condição de verificação de programa é reconhecida pelo subsistema de canal e um erro de especificação de memória de classe de armazenamento é indicado no campo de código qualificador de exceção do ARSB. • Quando o campo de tamanho de bloco especifica Blocos de 1M-byte, bits especificados deste campo contêm um valor definido; de outra forma, uma condição de verificação de programa é reconhecida pelo subsistema de canal e um erro de especificação de memória de classe de armazenamento é indicado no campo de código qualificador de exceção do ARSB. [0160] Storage class memory address 272: When the operation code field has meaning, this field includes (for example, 64 bit) the storage class memory address to be used for data transfer or for be operated (for example, emptied, released) and the sequence apply: • When the block size field specifies 4K-byte blocks, specified bits of this field contain a defined value (for example, zeros); otherwise, a program check condition is recognized by the channel subsystem and a storage class memory specification error is indicated in the ARSB exception qualifier code field. • When the block size field specifies 1M-byte blocks, specified bits of this field contain a defined value; otherwise, a program check condition is recognized by the channel subsystem and a storage class memory specification error is indicated in the ARSB exception qualifier code field.
[0161] [0161] When the BNM marker is defined, this field is reserved and not verified.
[0162] [0162] As indicated above, an EADM indirect data address word can be specified.
[0163] [0163] The EADM indirect data address word (AW from AID) allows the program to specify the transfer of data blocks between storage class memory and non-contiguous main storage blocks. An AID AW or AIDAW list is designated by an MSB when the indirect address bookmark in the MSB is defined.
[0164] [0164] The amount of data transferred by a single AW from AID is specified by the block size field in the MSB. The number of AIDAWs in an AID AW list is the sum of the number specified by the block count field in the MSB plus the number of AIDAWs that specify branching for the next AID AW. Data transfers can be processed in orders that are different from those specified in an AIDAW list. In addition, data transfers specified by multiple AIDAWs in an AIDAW list can be processed concurrently.
[0165] [0165] An AIDAW is allocated, for example, in a quadruple word limit. A list of AIDAWs can be any length, but in one example, they should not cross a 4K-byte boundary unless the branch to the next AIDAW (BNA) is specified to cross the boundary. There is no requirement that the AIDAW that is the target of a branch be contiguous with the AIDAW that specifies the BNA. However, the program must create an AIDAW list in as few 4K-byte blocks as possible; otherwise, performance degradation can occur.
[0166] [0166] Referring to figure 2F, in an example, an EADM 280 indirect data address word includes:
[0167] [0167] Bookmarks 282: An example bookmark includes:
[0168] [0168] Branching to the next AIDAW (BNA): When defined, this marker indicates that the main storage address field does not specify a main storage address to be used to transfer data. Instead, the main storage address field specifies the address of the next AIDAW to be used to transfer the data.
[0169] [0169] When the BNA marker is defined and the main storage address field specifies an AIDAW where the BNA marker is also defined, the MSB address is stored in the ARSB's failure MSB address field, the address from branch to source AIDAW is stored in the ARSB's main fault storage address field, and an AIDAW branch error is indicated in the exception qualifier code field in ARSB.
[0170] [0170] If an AIDAW ends at a 4K-byte limit, the MSB specifies additional AIDAWs, and the BNA marker is not set, the MSB address is stored in the ARSB's fault MSB address field, the address of the AIDAW is stored in the ARSB's main fault storage address field, and an AIDAW list error is indicated in the exception qualifier code field in the ARSB.
[0171] • Quando o campo de tamanho de bloco no MSB especifica blocos de 4K-byte, bits especificados deste campo contêm um valor definido (por exemplo, zero); de outra forma, uma condição de verificação de programa é reconhecida pelo subsistema de canal e um erro de especificação de armazenamento principal é indicado no campo de código qualificador de exceção do ARSB. • Quando o campo de tamanho de bloco no MSB especifica blocos de 1M-byte, bits especificados deste campo contêm um valor definido (por exemplo, zeros); de outra forma, uma condição de verificação de programa é reconhecida pelo subsistema de canal e um erro de especificação de armazenamento principal é indicado no campo de código qualificador de exceção do ARSB. • Quando o marcador de BNA é definido, este campo inclui um endereço de armazenamento principal do próximo AW de AID a ser usado para transferência de dados. [0171] Main storage address 284: When the BNA field is not defined, this field includes an address in the main storage to be used for data transfer and the sequence applies: • When the block size field in the MSB specifies 4K-byte blocks, specified bits of this field contain a defined value (for example, zero); otherwise, a program check condition is recognized by the channel subsystem and a master storage specification error is indicated in the ARSB exception qualifier code field. • When the block size field in the MSB specifies 1M-byte blocks, specified bits of this field contain a defined value (for example, zeros); otherwise, a program check condition is recognized by the channel subsystem and a master storage specification error is indicated in the ARSB exception qualifier code field. • When the BNA marker is set, this field includes a primary storage address for the next AID AW to be used for data transfer.
[0172] [0172] As described above, EADM operations are specified by a Start Subchannel instruction. That is, the program initiates EADM operations by issuing a Start Subchannel instruction that designates a ADM-type subchannel and an EADM ORB. The execution of the instruction passes the contents of the EADM ORB to the designated subchannel. The EADM ORB includes the Subchannel Key specification (used for protection) and the AOB address to be used.
[0173] [0173] In one example, as depicted in figure 3A, a Start Subchannel instruction 300 includes an operation code 302 specifying the Start Subchannel function, a first operand 304, which is an implicit operand located in, for example, general register 1, which includes the subsystem identifier designating the ADM-type subchannel to be started; and a second operand 306, which is the logical address of the EADM ORB. The EADM ORB specifies the parameters used to control the start function. The contents of the EADM ORB are positioned on the designated subchannel during the execution of the Start Subchannel, before setting the condition code. If the execution of the Start Subchannel results in the definition of a different condition code than a code that indicates success, the contents of the EADM ORB are not positioned in the designated subchannel.
[0174] 1. Buscar o ARQB a partir de AOB. 2. Executar as operações de EADM como especificado pelo ARQB e as designações de MSBs. 3. Armazenar de maneira condicional informação de completação no ARSB no AOB. 4. Fazer com que o subcanal do tipo ADM seja feito estado pendente, indicando a completação da função de partida. [0174] Subsequent to the execution of the Start Subchannel for a subchannel of the ADM type, the channel subsystem performs the start function asynchronously to start EADM operations with the EADM Installation. The start function includes, for example, the following: 1. Fetch the ARQB from AOB. 2. Perform EADM operations as specified by the ARQB and the MSB designations. 3. Conditionally store completion information in the ARSB in the AOB. 4. Make the ADM-type subchannel a pending state, indicating the completion of the start function.
[0175] [0175] In one embodiment, with reference to figure 3B, when the Start Subchannel instruction is executed and the SID designates a ADM type subchannel and the second operand designates an EADM ORB, an EADM operation is specified, STEP 320.
[0176] [0176] Parameters in the EADM ORB are passed to the designated subchannel, STEP 322, and the channel subsystem is required to perform a start function with the EADM Installation, STEP 324. The channel subsystem performs the function asynchronously. departure using information on the subchannel, including information passed during the execution of the Departure Subchannel Instruction, to initiate EADM operations, STEP 326.
[0177] [0177] Performing an EADM operation (for example, the first operation) includes using information from the EADM ORB to obtain the AOB, STEP 328, and the information is used in the AOB to obtain the EADM request block ( ARQB) and a designation of one or more motion specification blocks (MSBs) from EADM, STEP 330. The one or more designated MSBs are then fetched from the main storage, STEP 332, and the information specified in the MSBs is used for control the requested EADM operation. The first operation is considered to be initiated when the channel subsystem attempts to initiate data transfer or attempts an emptying or flushing operation.
[0178] [0178] The channel subsystem performs the requested operations in MSB (s), STEP 334. This processing is asynchronous for the execution of the start command.
[0179] [0179] When EADM operations initiated by the Departure Subchannel end, STEP 336, the channel subsystem generates state conditions, STEP 338. The generation of these conditions is brought to the attention of the program through an I / O interruption , STEP 339. The program can also request these conditions by executing a Pending Test Interrupt Instruction.
[0180] [0180] The generated status conditions are presented to the program in the form of an EADM subchannel status word (SCSW). The EADM SCSW is stored as part of the EADM interrupt response block (IRB) by executing the Test Subchannel instruction.
[0181] [0181] When EADM operations specified in the EADM operation block (AOB) are terminated, the channel subsystem generates a primary and secondary interrupt state.
[0182] [0182] EADM operations can be terminated by the EMPTY SUB-CHANNEL or a recognized abnormal condition while performing the start function.
[0183] [0183] The processing of an MSB by the channel subsystem, for a movement operation, controls the flow of an information unit to or from the main storage. To change the direction of data movement during MSB processing, a new MSB is required. The ARQB designates the count of MSBs that understand the requirement.
[0184] • A transferência de blocos de dados a partir do armazenamento principal para a memória de classe de armazenamento. • A transferência de blocos de dados a partir da memória de classe de armazenamento para o armazenamento principal. • O esvaziamento dos blocos de memória de classe de armazenamento. • A liberação dos blocos de memória de classe de armazenamento, quando a Instalação de Liberação de EADM é instalada. [0184] Each EADM operation is represented by an MSB. An MSB can specify any of the following: • Transferring blocks of data from main storage to storage class memory. • Transferring blocks of data from storage class memory to main storage. • Emptying storage class memory blocks. • The release of storage class memory blocks, when the EADM Release Facility is installed.
[0185] [0185] If the storage blocks to be transferred for a move operation are not contiguous in the main storage, a new MSB can be used or the MSB can use indirect addressing by specifying a list of EADM indirect data address words (AIDAWs ) to designate the non-contiguous blocks. Since an MSB can specify data transfer in only one direction, a new MSB must be used when there is a change in the direction of data transfer.
[0186] • Transferências de dados podem ser processadas fora de ordem com relação à ordem da lista de MSB especificada. • Transferências de dados especificadas por múltiplos MSBs em uma lista de MSB podem ser processadas de maneira concorrente. • Transferências de dados podem ser processadas fora de ordem com relação à ordem de uma lista de AW de AID especificada. [0186] The following are characteristics of EADM data transfers: • Data transfers can be processed out of order with respect to the order of the specified MSB list. • Data transfers specified by multiple MSBs in an MSB list can be processed concurrently. • Data transfers can be processed out of order with respect to the order of a specified AID AW list.
[0187] [0187] Data transfers specified in multiple AIDAWs in an AID AW list can be processed concurrently.
[0188] [0188] Accesses to main storage and storage class memory are not necessarily single access references and are not necessarily carried out in a left-to-right direction, as noted by the program and other CPUs.
[0189] [0189] If two or more EADM operations are currently active and address the same SCM locations, the main storage location, or both, operations can be performed concurrently and content from different operations can be interlaced ; However:
[0190] [0190] For inbound operations, the data stored by the EADM Facility in each main storage block that is a size equal to the concurrent SCM block size consists of data transferred from the storage class memory by only one of the competing EADM operations.
[0191] [0191] For outbound operations, each storage class memory block that is at a limit and is a size equal to the concurrent SCM block size contains the data specified by only one of the competing EADM operations.
[0192] • Quando operações de EADM estão ativas para um subcanal, é imprevisível se alterações feitas pelo programa para o A QB, MSBs, AIDAWs, e dados de transferência associados com a operação ativa são observados pela Instalação de EADM. [0192] The above is true regardless of whether EADM operations are specified by a single AOB and are being processed by the same case as the start function or EADM operations are specified by different AOBs and are being processed by different cases of starting function. • When EADM operations are active for a subchannel, it is unpredictable whether changes made by the program to A QB, MSBs, AIDAWs, and transfer data associated with the active operation are observed by the EADM Facility.
[0193] [0193] When all blocks designated by all MSBs specified by the AOB have been transferred or released or emptied, the subchannel generates the state, which is stored in the subchannel, and requests an I / O interruption for the ADM type subchannel.
[0194] [0194] The completion of an EADM operation is usually indicated by the combined state conditions of the channel end and device end. This state combination represents the primary and secondary state combination indicating that the subchannel is available for another start function after the state is released.
[0195] [0195] As described above, an MSB can specify the data transfer operation, an empty operation, or a release operation, each of which is described below.
[0196] [0196] When a move operation is requested, one or more blocks of data are moved between main storage and storage class memory. For example, for a read operation, SCM data is obtained from SSDs that provide the content designated by the specified SCM address, and then that the content is stored in main memory. The process is reverted to a write operation. The adapters that control the SSDs perform the storage. In further detail, to perform a move operation, the system firmware first translates a given SCM address into an adapter address (for example, logical volume address, where a logical volume includes one or more SSDs). For example, a translation table is used that correlates the SCM address with an adapter address. The system firmware then submits one or more corresponding adapter move commands (for example, read or write) to one or more of the I / O adapters. An adapter move command contains a primary storage address, an adapter address, and a transfer size. The adapter then uses another translation table to find one or more physical SSD addresses that match the adapter address. The I / O adapter performs the movement operation either by searching for data from the main storage or by storing it in the SSDs, or by searching for data from the SSDs and storing it in the main memory. Additional details are additionally provided in a code-filed patent application entitled "Firmware Management Storage Class Memory", POU920110090US1, which is incorporated herein by reference in its entirety.
[0197] [0197] When an emptying operation is performed, the designated increments of the storage class memory are emptied by setting the contents to zero.
[0198] [0198] Additionally, when a release operation is performed, one or more standard CUT commands can be submitted for SSDs containing the corresponding SCM addresses. The CUT command allows a program to provide tips on using the block, allowing better garbage collection by SSDs. The CUT command allows an operating system to inform an SSD from which storage blocks are no longer considered in use and can be cleaned.
[0199] [0199] An EADM operation can be terminated prematurely by a Clean Subchannel instruction. The execution of the Released Subchannel instruction ends the execution of the AOB in the subchannel, releases the subchannel from the AOB indications in execution, and performs the emptying function asynchronously. When the emptying function is performed, before the subchannel becomes a pending state, data transfer is terminated and the amount of data transferred is unpredictable. The execution of the emptying function does not result in the generation of the state, but causes the channel subsystem to make a pending I / O interruption.
[0200] [0200] In one embodiment, referring to figure 3C, a Clean Subchannel instruction 350 includes an operation code 352 designating the EMPTY SUBCANAL function. The subchannel to be released is designated by a subsystem identification word in, for example, general register 1.
[0201] 1. Garantir que a transferência de dados corrente seja terminada. 2. Modificar campos no subcanal e condicionalmente o ARSB. Por exemplo, a palavra de estado de subcanal é modificada para indicar a função de esvaziamento no campo de Controle de Função e no campo de Controle de Atividade. O ARSB pode ser modificado para refletir quaisquer erros detectados. 3. Fazer com que o subcanal seja feito estado pendente indicando a completação da função de esvaziamento. [0201] The emptying function for a subchannel of the ADM type includes: 1. Ensure that the current data transfer is completed. 2. Modify fields in the subchannel and conditionally the ARSB. For example, the subchannel status word is modified to indicate the emptying function in the Function Control field and in the Activity Control field. The ARSB can be modified to reflect any errors detected. 3. Make the subchannel a pending state indicating completion of the emptying function.
[0202] [0202] Other instructions may also be issued that may specify a subchannel of the ADM type, including Test Subchannel, Modification Subchannel and Storage Subchannel, each of which is described below.
[0203] [0203] Referring to figure 3D, in one example, a Test Subchannel instruction 360 includes, for example, an operation code 362 specifying the Test Subchannel function; a first operand 364, which is an implicit operand located in, for example, general register 1 which contains the subsystem identification word designating the subchannel to be tested; and a second operand 366 which is the logical address of the response block information (IRB) in which information is stored.
[0204] [0204] When the Test Subchannel is executed by specifying a subchannel of the ADM type, the subchannel is pending state, and information is stored in the designated EADM IRB (Interrupt Response Block), a specified condition code is defined. When the subchannel is not pending status and status information is stored in the designated EADM IRB, a defined condition code is defined. When the subchannel is not provided or is not enabled, no action is taken.
[0205] [0205] In one example, the EADM IRB includes a subchannel status word (SSW) and an Extended Status Word (ESW), as well as an Extended Control Word that can provide information dependent on the additional model that describes the conditions that may exist in the installation. Each of these words is further described below after discussing several instructions that can specify a subchannel of the type of ADM.
[0206] [0206] Referring to figure 3E, in one embodiment, a Modification Subchannel instruction 370 includes an operation code 372 specifying the Modification Subchannel function; a first operand 374, which is an implicit operand located in, for example, general register 1, which includes the subsystem identification word designating the subchannel to be modified; and a second operand 376, which is the logical address of a subchannel information block (SCHIB) associated with the subchannel.
[0207] [0207] When the Modification Subchannel is executed by specifying a subchannel of the ADM type, and information from the specified Subchannel Information Block (SCHIB) is positioned in the subchannel, a specific condition code is defined. When the subchannel is in a pending state, no action is taken and a defined condition code is defined. When the subchannel is engaged for a start or empty function, no action is taken.
[0208] [0208] With reference to figure 3F, an example of a Storage Subchannel instruction is described. In one example, a Storage Subchannel instruction 380 includes an operation code 382 identifying the Storage Subchannel function; a first operand 384, which is an implicit operand located in, for example, general register 1 that includes a subsystem identification word designating the subchannel for which the information is being stored; and a second operand 386 which is the logical address of the SCHIB.
[0209] [0209] When the Storage Subchannel is issued specifying a subchannel of the ADM type, and an SCHIB is stored, a specified condition code is defined. When the designated subchannel is not provided in the channel subsystem, no action is taken.
[0210] [0210] An example of a subchannel information block for a subchannel of the ADM SCHIB type (EADM) is described with reference to figure 4A. In one example, a SCHIB of (EADM) 400 includes a model 401 dependent area, which includes model dependent information. In addition, SCHIB 400 includes a path management control word (PMCW) 402, and a subchannel status word (SCSW) 404, each of which is described below.
[0211] [0211] In one example, EADM PMCW 402 includes, for example, the following fields as shown in figure 4B:
[0212] [0212] Interrupt Parameter 410: This field includes the Interrupt parameter that is stored in the I / O interruption code. The Interrupt parameter can be set to any value by the Start Subchannel and Modification Subchannel. The initial value of the Interrupt parameter field on the subchannel is zero.
[0213] [0213] Interrupt Subclass (ISC) 412: This field includes a plurality of bits that are an unassigned binary integer, in a specified range, that corresponds with the bit position of the I / O Interrupt Subclass mask bit. in a specified control record for each CPU in the configuration. Setting the mask bit in a CPU's control register controls the recognition of interrupt requests that refer to the subchannel by that CPU. The ISC can be set to a value by the Modification Subchannel. The initial value of the ISC field in the subchannel is, for example, zero.
[0214] [0214] Enabled (E) 414: This field, when defined, indicates that the subchannel is enabled for all EADM functions.
[0215] [0215] Subchannel Type (ST) 416: This field designates the type of subchannel.
[0216] [0216] Depending on the model and configuration, one or more of the following types of subchannel can be provided: I / O subchannel or ADM subchannel.
[0217] [0217] The value of this field is determined when the subchannel is configured and cannot be changed by the Modification Subchannel.
[0218] [0218] When the Modification Subchannel Instruction is executed and designates a ADM type subchannel, ST is to indicate subchannel ADM; otherwise, an operand exception is recognized.
[0219] [0219] Returning to figure 4A, the subchannel information block also includes the subchannel status word 404. The EADM subchannel status word (SCSW) provides indications for the program that describe the status of a subchannel of the type of ADM and associated EADM operations. In an example, as shown in figure 4C, subchannel status word 404 includes:
[0220] [0220] Sub-Channel Key (Key) 420: When the EADM start function indicator in the Function Control field (described below) is defined, this field includes the storage access key used by the channel subsystem. These bits are identical with the key specified in the EADM ORB when the Start Subchannel was executed.
[0221] • Verificação de programa • Verificação de proteção • Verificação de dados de canal • Verificação de controle de canal • Verificação de instalação de movimento de dados assíncronos estendidos (EADMF) [0221] Extended Status Word Format (L) 422: When the pending status indicator of the state controls field (described below) is defined, this field, when defined, indicates that a format-0 ESW has been stored. A format-0 ESW is stored when an interrupt condition containing any of the following indications is released by the Test Subchannel: • Program verification • Protection check • Checking channel data • Channel control check • Verification of installation of extended asynchronous data movement (EADMF)
[0222] [0222] Deferred condition code (CC) 424: When the EADM start function indicator is set and the pending status indicator is also set, this field indicates the general reason that the subchannel was pending status when the Test Subchannel or Storage Subchannel has been performed. The deferred condition code is significant when the subchannel is pending state with any combination of the state and only when the start function indicator of the Function Control field in the SCSW is set.
[0223] [0223] The deferred condition code, if defined, is used to indicate whether conditions have been found that oppose the subchannel becoming active subchannel while the subchannel is pending departure.
[0224] [0224] Example of deferred condition codes include:
[0225] [0225] A normal I / O interruption has been presented.
[0226] [0226] The state is present in the EADM SCSW that was generated by the channel subsystem for conditions that oppose the EADM start function being started successfully. That is, the subchannel does not transition to the active subchannel state.
[0227] [0227] CCW format (F) 426: When the EADM start function indicator is set, this field is stored as a defined value.
[0228] [0228] Pre-fetch (P) 428: When the EADM start function indicator is set, this field is stored as a defined value.
[0229] [0229] Extended Control (E) 430: This field, when defined, indicates that model-dependent information is stored in the EADM Extended Control (ECW) word.
[0230] • Função de partida de EADM: Quando definido, indica que uma função de partida de EADM foi requisitada e é tanto pendente quanto está em progresso no subcanal do tipo ADM. A função de partida de EADM é indicado no subcanal quando um código de condição de sucesso é definido para o Subcanal de Partida. A função de partida de EADM é liberada no subcanal quando o Subcanal de Teste é executado e o subcanal é de estado pendente. A função de partida de EADM também é liberada no subcanal durante a execução do SUBCANAL DE ESVAZIAMENTO. • Função de esvaziamento de EADM: Quando definido, indica que uma função de liberação de EADM foi requisitada e é tanto pendente quanto está em progresso no subcanal do tipo ADM. A função de esvaziamento de EADM é indicado no subcanal quando um código de condição de sucesso é definido para o Subcanal Liberado. A indicação de função de esvaziamento de EADM é liberada no subcanal quando o Subcanal de Teste é executado e o subcanal é de estado pendente. [0230] Function Control (FC) 432: The Function Control field indicates the EADM functions that are indicated in the subchannel. Example functions include: • EADM start function: When defined, it indicates that an EADM start function has been requested and is both pending and in progress on the ADM type subchannel. The EADM start function is indicated on the subchannel when a success condition code is set for the Start Subchannel. The EADM start function is released at the subchannel when the Test Subchannel is executed and the subchannel is in a pending state. The EADM start function is also released at the subchannel during the execution of the EMPTY SUBCANAL. • EADM flush function: When defined, it indicates that an EADM release function has been requested and is both pending and in progress on the ADM-type subchannel. The EADM emptying function is indicated on the subchannel when a success condition code is set for the Released Subchannel. The EADM empty function indication is released at the subchannel when the Test Subchannel is executed and the subchannel is in a pending state.
[0231] [0231] Activity Control (AC) 434: The Activity Control field indicates the current progress of the EADM function previously accepted in the subchannel.
[0232] [0232] All conditions that are represented by bits in the Activity Control field are reset in the ADM type subchannel when the Test Subchannel is executed and the subchannel is in a pending state.
[0233] • Partida pendente: Quando definido, indica que o subcanal é de partida pendente. [0233] Examples of activities include: • Pending start: When defined, it indicates that the subchannel is pending start.
[0234] [0234] The channel subsystem may or may not be in the process of performing the EADM start function. The subchannel becomes pending start when a success condition code is set for the Start Subchannel. The subchannel remains pending starting when performing the EADM start function and the channel subsystem determines what conditions exist that avoids searching for A QB.
[0235] • O subsistema de canal tenta iniciar a primeira transferência de dados especificada pelo AOB. • SUBCANAL DE ESVAZIAMENTO é executado. • Subcanal de Teste libera uma condição de estado no subcanal. [0235] The subchannel is no longer pending start when any of the following occurs: • The channel subsystem attempts to initiate the first data transfer specified by the AOB. • SUB-CHANNEL EMPTY is performed. • Test subchannel releases a status condition on the subchannel.
[0236] [0236] Pending emptying: When defined, the subchannel is pending emptying. The channel subsystem may or may not be in the process of performing the EADM emptying function. The subchannel becomes pending empty when a specified condition code is defined for the EMPTY SUBCANAL.
[0237] • A função de esvaziamento de EADM é realizada. • Subcanal de Teste libera a condição de estado pendente sozinha. [0237] The subchannel is no longer pending emptying when any of the sequence occurs: • The EADM emptying function is performed. • Test subchannel releases the pending state condition alone.
[0238] [0238] Active subchannel: When defined, it indicates that the ADM type subchannel is the active subchannel. The ADM-type subchannel is said to be the active subchannel when the channel subsystem attempts to initiate the first data transfer specified by AOB or performs a first operation (which always happens first).
[0239] • O subcanal se torna estado pendente. • SUBCANAL DE ESVAZIAMENTO é executado. [0239] The subchannel is no longer the active subchannel when any of the sequence occurs: • The subchannel becomes a pending state. • SUB-CHANNEL EMPTY is performed.
[0240] [0240] State Control (SC) 436: The state control field provides the program with summary level indication of the interruption condition described by the information in the subchannel status and device status fields. More than one status control indicator can be defined as a result of conditions in the subchannel.
[0241] [0241] Examples of state controls include:
[0242] • O subcanal do tipo ADM é de partida pendente e a condição do estado se opõe à iniciação da primeira transferência de dados. • O subcanal é o subcanal ativo e uma condição anormal, que está sendo reportado como estado de subcanal, terminou as operações de EADM. [0242] Alert state: When defined, it indicates that an alert interruption condition exists. An alert interrupt condition is recognized when the alert state is present in the subchannel. The alert state is generated by the channel subsystem under any of the following conditions: • The ADM type subchannel is pending start and the state condition is opposed to the initiation of the first data transfer. • The subchannel is the active subchannel and an abnormal condition, which is being reported as a subchannel status, has ended EADM operations.
[0243] [0243] When the Test Subchannel or SUB-CHANNEL EMPTY is executed, the alert state is released in the subchannel.
[0244] [0244] Primary state: When defined, indicates a primary interrupt condition exists. A primary interrupt condition is recognized when the primary state is present in the subchannel. A primary interrupt condition is a requested interrupt condition that indicates, when accompanied by the secondary interrupt condition, completion of the EADM start function on the subchannel.
[0245] [0245] When the Test Subchannel or EMPTY SUBChannel is executed, the primary interrupt condition is released at the subchannel.
[0246] [0246] Secondary state: When defined, it indicates that a secondary interrupt condition exists. A secondary interrupt condition is recognized when the secondary state is present in the subchannel. A secondary interrupt condition is a requested interrupt condition that indicates, when accompanied by the primary interrupt condition, completion of the EADM start function at the subchannel.
[0247] [0247] When the Test Subchannel or EMPTY SUB-CHANNEL is executed, the secondary interrupt condition is released at the subchannel.
[0248] [0248] Pending state: When defined, it indicates that the subchannel is in a pending state and that the information describing the cause of the interruption condition is available. When the Test Subchannel is executed, the storage of an EADM SCSW with the pending status bit set, all EADM SCSW indications are released in the subchannel that positions the subchannel in the idle state. The pending state condition is also released at the subchannel during the execution of the EMPTY SUBCANAL.
[0249] [0249] When the pending state is defined, all access to main storage and storage class memory for subchannel A SB has ended.
[0250] [0250] Subchannel status 438: ADM-type subchannel status conditions are detected and stored in the subchannel status field by the channel subsystem. The subchannel status field is significant when the subchannel is pending state. Except for conditions caused by equipment malfunction, the subchannel status can only occur when the channel subsystem is involved with the processing of an EADM function.
[0251] • Verificação de programa: Verificação de programa ocorre quando erros de programação são detectados pelo subsistema de canal. • Verificação de proteção: Verificação de proteção ocorre quando o subsistema de canal tenta um acesso de armazenamento que é proibido pelo mecanismo de proteção. A proteção se aplica à busca de A QB, MSBs, AIDAWs, e dados a ser transferidos para a memória de classe de armazenamento, e para o armazenamento de informação no ARSB e dados transferidos a partir da memória de classe de armazenamento. • Verificação de dados de canal: Verificação de dados de canal indica que um erro de armazenamento não corrigido foi detectado com relação à busca de dados a partir do armazenamento principal ou o armazenamento de dados para o armazenamento principal. • Verificação de controle de canal: Verificação de controle de canal indica que um erro de armazenamento não corrigido foi detectado com relação à busca ou o armazenamento de AOB, MSBs, ou AIDAWs, ou que um mau funcionamento de máquina foi encontrado pelo subsistema de canal e o mau funcionamento afeta as operações de EADM. • Verificação de Instalação de Movimento de Dados Assíncrono Estendido (EADM): [0251] Examples of state conditions include: • Program check: Program check occurs when programming errors are detected by the channel subsystem. • Protection check: Protection check occurs when the channel subsystem attempts storage access that is prohibited by the protection mechanism. The protection applies to the search for A QB, MSBs, AIDAWs, and data to be transferred to storage class memory, and for the storage of information in the ARSB and data transferred from storage class memory. • Channel data check: Channel data check indicates that an uncorrected storage error has been detected with regard to fetching data from main storage or data storage to main storage. • Channel control check: Channel control check indicates that an uncorrected storage error has been detected with respect to the search or storage of AOB, MSBs, or AIDAWs, or that a machine malfunction has been found by the channel subsystem and malfunction affects EADM operations. • Verification of Extended Asynchronous Data Movement (EADM) Installation:
[0252] [0252] The EADM Installation check indicates that an error has been detected by the EADM Installation with respect to transferring data to or from storage class memory or with respect to performing an operation on storage class memory.
[0253] [0253] When a program check, protection check, channel data check, channel control check, or EADM Install check condition is recognized by the channel subsystem, EADM operations are terminated and the channel is done pending status with primary state, secondary state, and alert state.
[0254] [0254] EADM 440 Operation Block Address: This field includes the EADM Block Address operation.
[0255] [0255] Device state 442: This includes the device end or the channel end.
[0256] [0256] When the ESW format 422 of the subchannel status word is defined and the subchannel is pending state, an EADM subchannel extended status word (ESAD DE EADM) is provided that specifies additional information about the type subchannel ADM.
[0257] [0257] In one example, with reference to Figure 4D, an extended EADM 450 subchannel status word includes:
[0258] • Marcadores de Estado Estendido (ESF): Um campo em que bits, quando presentes, especifica que um erro foi detectado pelo subsistema de canal. [0258] EADM 452 Subchannel Output: The EADM subchannel output includes, in an example: • Extended Status Markers (ESF): A field in which bits, when present, specify that an error has been detected by the channel subsystem.
[0259] [0259] Examples of Extended Status Markers include:
[0260] • Validade de endereço de AOB: Quando definido, indica que o endereço armazenado no campo de endereço de AOB da SCSW é útil para os propósitos de recuperação. [0260] Key verification: When defined, it indicates that the channel subsystem has detected an invalid verification block code (CBC) in the associated storage key when referencing data in the EADM operation block (AOB), in a block of EADM movement specification (MSB), or in an EADM indirect data address word (AW from AID). • AOB address validity: When defined, it indicates that the address stored in SCSW's AOB address field is useful for recovery purposes.
[0261] [0261] EADM 454 extended report word that includes, for example:
[0262] [0262] An EADM Operation Block Error indicator (B) which, when defined, specifies that the exception state stored in the EADM SCSW is associated with the specified EADM operation block (AOB); and a Stored EADM response block indicator (R) which when defined indicates that the EADM response block (ARSB) is stored.
[0263] [0263] When the SCSW Extended Control indicator and the SCSW Extended Status Word Format indicator are defined, the EADM Extended Control word provides additional information of a model-dependent nature that describes the conditions that may exist in the EADM installation.
[0264] [0264] Additionally, the following channel report words (CRWs) can be reported for ADM-type Subchannels: installed subchannel parameters initialized; installed subchannel parameters restored; the available subchannels; pending channel event information.
[0265] [0265] Unsolicited events and malfunctions occurring at the EADM Facility can be reported by the CRW pending channel event information.
[0266] [0266] Described in detail above is an Extended Asynchronous Data Movement Installation used to move block data between main storage and storage class memory and to perform other operations in storage class memory. In one embodiment, information about the EADM Installation and storage class memory is obtained using an EADM command. In particular, as storage class memory is not directly accessible, a capacity is provided to determine whether storage class memory is allocated, and if so, to obtain information regarding the configuration. In particular, in one example, a capacity is provided to communicate with a control program (for example, operating system) whether any storage class memory has been allocated or not, and if so, how much and in which locations. The ability to determine available storage class memory is referred to here as discovery and an example of a discovery function is provided by a Storage Class Memory Information (SSI) command.
[0267] • Contagem máxima dos blocos de especificação de movimento (MSBs) per AOB. • Contagem máxima de bloco por MSB. [0267] The Storage Storage Class Memory Information (SSI) command is used to obtain information about storage class memory and the Extended Asynchronous Data Movement Installation. The SSI command returns the following information obtained, for example, from the channel subsystem. This information is described in further detail below: 1. Features of the EADM Installation, including: • Maximum count of movement specification blocks (MSBs) per AOB. • Maximum block count per MSB.
[0268] • Tamanho de incremento de SCM. • Lista de incrementos de endereço de SCM dentro de espaço de endereço de SCM. [0268] 2. Storage class memory characteristics, including: • SCM increment size. • List of SCM address increments within the SCM address space.
[0269] [0269] Dependent on the maximum model SCM address.
[0270] [0270] Execution of the Storage SCM Information command, which is synchronous, does not change any information contained in the channel subsystem.
[0271] [0271] Additional details regarding the SSI command are described with reference to figures 5A-5D. Referring initially to Figure 5A, in one embodiment, a command request block 500 for the Storage SCM Information command includes, for example:
[0272] [0272] Length 502: A value specifying a length of the command request block.
[0273] [0273] Command code 504: A value that specifies the command code for the Storage SCM Information command.
[0274] [0274] Format (FMT) 506: A value that specifies the format of the command request block.
[0275] [0275] Continuation Token 508: A value that you can request for a continuation point where you can summarize from a previous response that was not complete. If the value of the continuation token is zero, a fresh start is made. If the value of the continuation token is not zero and is not recognized, a fresh start is made.
[0276] [0276] An embodiment of a response block 520 of the SSI command is described with reference to figure 5B, and includes, for example:
[0277] [0277] Length 522: A value that indicates the length in bytes of the command response block.
[0278] [0278] Response code 524: A value that describes the results of the attempt to execute the SSI command. The response code value dictates the length of the response block. For example, if a selected Response Code is stored, the length specifies 96 + Nx16 bytes, where N is the number of storage class memory address list entries, described below. In one example, N is in the range 1 <N <248.
[0279] [0279] Format (FMT) 526: A value that indicates the format of the command response block. The field value is, for example, zero.
[0280] [0280] RQ 528: A response qualifier value, as defined below:
[0281] [0281] No response qualification exists.
[0282] [0282] The specified continuation token is not recognized and zero has been handled.
[0283] [0283] Maximum block count per MSB (MBC) 530: A value that indicates the maximum value that can be used in the block count field of a motion specification block (MSB).
[0284] [0284] Maximum SCM Address (MSA) 532: A value that indicates the Maximum SCM Address depending on the model. It is the SCM address of the last byte in the highest addressable SCM increment.
[0285] [0285] SCM Increment Size (IS) 534: A value that represents the size of each SCM increment in the SCM address list and is, for example, a power of two.
[0286] [0286] Maximum MSB Count (MMC) 536: A value indicating the maximum count of the motion specification blocks (MSB) that can be specified in an EADM operation block (AOB).
[0287] [0287] Maximum Configurable SCM Increments (MCI) 538: A value that is the maximum number of SCM increments that can be configured for the requirement configuration.
[0288] [0288] In one embodiment, MCI does not exceed 2 (-64'IS For example, for a SCM increment size of 16G-byte, MCI <2 (64_34), since all 16G-byte SCM increments must be addressed within the 64-bit addressing constraint Additionally ((MCI + 1) x IS) - 1 does not exceed the maximum SCM address depending on the model.
[0289] [0289] The number of configured SCM increments (NCI) reduces the total size (TS) that can be specified when a Successful Configuration storage class Memory command, described below, is executed, such that TS <(MCI) -NCI). However, based on all system capacity and allocations already made for other configurations, the number of SCM increments in the initialized state may or may not be able to fully satisfy a requirement to otherwise validly configure up to the limit of Requirement configuration MCI.
[0290] [0290] Total Initialized SCM Increments of CPC 540: A value that represents the number of SCM increments in the initialized state for the system (for example, for a central processing complex (CPC)). If the system is partitioned logically, this is the number of increments available in total for allocation to / by the partitions.
[0291] [0291] Total Initialized SCM Increments of CPC 542: A value that represents the number of SCM increments in the uninitialized state for the system (for example, for CPC).
[0292] [0292] SCM Measurement block size 544: A value that is the block size (BS) in bytes of an SCM measurement block. In one example, it is a power of 2, and the maximum SCM Measurement block size is, for example, 4096 bytes.
[0293] [0293] Maximum number of SCM Resource Parts 546: A value that is the maximum number in the CPM of SCM Resource Parts (RP) (for example, I / O Adapters). Each SCM increment is associated with an SCM resource part. Each SCM resource (for example, one or more I / O adapters and one or more SSDs) includes one or more parts. The maximum number of SCM Appeal Parts is, for example, 509.
[0294] [0294] In one example, the term "resource part" is defined for use in obtaining measurement information that refers to storage class memory. Each SCM increment can be distributed across multiple adapters and each adapter has some usage / measurement data to transmit. Thus, each measurement block returned is identified by a tuple consisting of the increment identifier plus the resource identifier.
[0295] [0295] SCM Data unit size 548: A model-dependent value that indicates the number of bytes that are included in an SCM data unit. In one example, the data unit is defined for use in obtaining measurement information that refers to storage class memory. The count that is reported is the count of data units, instead of bytes.
[0296] [0296] Continuation Token 550: A model-dependent value where a subsequent issue of the SSI command can continue at the continuation point represented by the token. The contents of a token continuation are model dependent.
[0297] [0297] Storage class memory address list 552: An origin of the SCM address list.
[0298] [0298] When the stored Response Code is a predefined value, a plurality of SCM (SALE) address list entries are stored (for example, (Length - 96) / 16 SALEs are stored).
[0299] [0299] In one example, the number of SALEs stored depends on the number of SCM increments in the requester's configuration, the state of each when the command is executed, and the channel subsystem model. Zero or more SALEs are stored and the actual number stored is determined, in an example, by subtracting 96 from the size of the response block (Length), and then dividing that result by 16.
[0300] [0300] Each SCM address list (SALE) entry represents an increment of SCM that occupies a range of SCM addresses. The starting SCM address of the SCM increment represented by SALE is contained in SALE and is the SCM address of the first byte of the corresponding SCM increment. The final address is calculated, in an example, by adding the SCM increment size, in bytes, to the starting SCM address and then subtracting one. This is the SCM address of the last byte of the SCM increment. The storage class memory represented by a SALE is a contiguous set of SCM byte Locations, which begins at a natural byte boundary, in one embodiment.
[0301] [0301] A SALE is stored when the corresponding SCM increment is in the configured state and space is available in the response block for SALE. If space in the response block's SCM address list is exhausted, a value is stored in the continuation token and the execution is completed with a specific Response Code.
[0302] [0302] Two or more SALEs are stored in ascending order of their SCM addresses.
[0303] [0303] An embodiment of a SALE is described with reference to figure 5C. In one example, a SALE 552 includes, for example:
[0304] [0304] SCM (SA) address 560: A value that is the 0 byte start SCM address of the corresponding SCM increment in the SCM address space, aligned with the natural limit determined by the SCM increment size (2IS bytes) ).
[0305] [0305] Persistence Attribute (P) 562: A value that indicates the current persistence rule applicable to the SCM increment. Any location within the SCM increment inherits the persistence rule. Possible persistence rules include:
[0306] [0306] Rule 1 - Retain data when the power is off.
[0307] [0307] Rule 2 - Retain data until power on or IML is restarted.
[0308] [0308] Operating Status 564: A value that indicates the operating status of the storage class memory increment represented by SALE. The operating state is valid only when the associated SCM Increment is in the configured state.
[0309] [0309] Examples of the state of operation include:
[0310] [0310] Operational (Op): The storage class memory represented by SALE is available for all I / O operations. The operational state is entered into a successful configuration and can be re-entered via the output from the temporary or permanent error state.
[0311] [0311] Temporary error (TE): The storage class memory represented by SALE is not available for any of the I / O operations. The data state is invalid but the data content in the transition from operational to temporary error is preserved. The temporary error state is entered from the operational state when access to the SCM increment does not exist.
[0312] [0312] Permanent error (PE): The storage class memory represented by SALE is not available for any of the I / O operations. The data state is invalid and the data is lost. The permanent error state is entered from the temporary error state or operational state when an error condition that cannot be corrected is recognized.
[0313] [0313] When an operation is completed with a permanent error indication defined in the Exception Qualifier code of the EADM response block, at least the corresponding SCM increment has entered the permanent error state. However, more than an increment of SCM they entered the state of permanent error.
[0314] [0314] When an SCM increment is not in the operational state, an I / O operation that references a location in the increment recognizes an extended asynchronous data movement installation check with either a temporary error or a permanent error defined in the code Exception qualifier of the EADM response block.
[0315] [0315] Data State 566: A value that indicates the data status of the contents of the storage class memory increment represented by SALE. The data state is valid when the associated SCM increment is in the configured and operational states.
[0316] [0316] Example data states include:
[0317] [0317] Zeroed - The contents of the SCM increment are all zeros.
[0318] [0318] Valid - The contents of the SCM increment is the accumulation of all successful writing operations. Increment locations not yet written remain as zero as well as unpredictable.
[0319] [0319] Unpredictable - The contents of the SCM increment before any write-type I / O operation are well known. After one or more write-type operations are performed, data content from other unwritten locations remains unpredictable even if the locations successfully written result in the state of the SCM increment data becoming valid.
[0320] [0320] A transition from both the zeroed and the unpredictable state to the valid state occurs with the first successful writing. Due to any difference between written data size and SCM Increment target size, the change to valid does not describe the actual condition of any unwritten data location. Such a location, having not been accessed for writing, is still effectively described as zeroed or unpredictable.
[0321] [0321] Classification 568: A value that indicates the conceptual quality of the storage class memory increment represented by SALE. The classification is valid only when the associated SCM Increment is in the configured and operational states. A value of zero means that no classification exists. A non-zero value in a specified range means that a classification exists. In this example, a rating value of one is the highest or the best rating. A rating value of fifteen is the lowest or worst rating. All the same, a SCM with a higher rating is preferred over a SCM with a lower rating.
[0322] 1. Um bloco liberado primeiro deve ser escrito antes de ser lido, de outra forma um erro em uma operação de leitura é reconhecida se uma leitura precede uma escrita. Para tal erro, o incremento de SCM permanece no estado operacional. 2. Com a configuração inicial, o estado dos dados é zerado. 3. O programa pode fazer uma operação especial, chamada de uma liberação, que posiciona um bloco especificado na condição liberada. [0322] R 570: This field indicates that the SCM increment recognizes a release operation. The following behaviors are related: 1. A block released first must be written before it can be read, otherwise an error in a read operation is recognized if a read precedes a write. For such an error, the SCM increment remains in the operational state. 2. With the initial configuration, the data status is reset to zero. 3. The program can perform a special operation, called a release, which positions a specified block in the released condition.
[0323] [0323] Resource ID 572: A non-zero value is a resource identifier (RID) of the resource that provides the SCM increment represented by SALE. When the RID is zero, no resource ID is indicated. In a particular example, the RID represents so many adapters and SSDs that it provides storage for the SCM increment. As certain RAID algorithms can be applied, or extracting improved performance by allowing competing I / O Operations across multiple adapters / SSDs, the RID can represent a composite entity.
[0324] [0324] Additional details regarding the storage class memory configuration states, and the operation and data states of a storage class memory address list are described below.
[0325] [0325] Initially, with reference to figure 6A, the configuration states and the events / actions that result in transitions within these states are described. As shown, SCM states are configured, held, and reserved. An SCM can be placed on hold from reserved, and then from hold to configured. Once configured, the SCM can be unconfigured and enter a reserved state.
[0326] [0326] Referring to figure 6B, operating states and the events that result in transitions within these states are shown. An SCM increment must be in the waiting state to be configured and is in the operational state through the successful completion of a configure action.
[0327] [0327] A first write for an increment of SCM in the zeroed state moves it to the valid state. An intervening shutdown and then switching on an SCM increment that is not indicated as having a rule persistence moves the SCM increment to the unpredictable state.
[0328] [0328] An error (E) can cause the transition to the temporary error state (TE) or the permanent error state (PE), depending on the specificity depending on the error model.
[0329] [0329] Acquisition (A) of connectivity can cause the transition from the temporary error state to the operational state (Op). A deconfiguration of an SCM increment can occur regardless of its state of operation.
[0330] • A partir de espera - zerado (z) • A partir de erro temporário - válido (v) • A partir de erro permanente - imprevisível (u) ou zerado (z) • A partir de operacional - válido (v) - primeira escrita • A partir de operacional - imprevisível (u) -energia em ciclo e persistência não é regra 1. [0330] Figure 6B also illustrates the data states when in the operational state, according to how the operational state was entered. The data status is valid and applies to the corresponding SCM increment when it is configured and in the operational state. Valid data states are zeroed, unpredictable, and valid. The following are the possible data states at the various entries for the operational state: • From standby - reset (z) • From temporary error - valid (v) • From permanent error - unpredictable (u) or zero (z) • From operational - valid (v) - first writing • From operational - unpredictable (u) - cycle energy and persistence is not a rule 1.
[0331] [0331] When not in the operational state, the data state is invalid.
[0332] [0332] When first configured and before the first writing, the data of an SCM increment is in the zeroed state, which means that its contents are all zeros.
[0333] [0333] As long as the data content of an SCM increment is not changed when it moves to or in a temporary error state, the increment is not accessible. Thus, saying that the data is valid must be descriptive, but not excessively significant due to the lack of accessibility of the program. Therefore, the state of the data is invalid in this scenario. Also, based on the error that causes the transition from operational to temporary error, if the data integrity is affected, the permanent error state is entered, the data state remains invalid, and the data is lost. If a concurrent repair can move an SCM increment from the permanent error state to the operational state without being both misconfigured and then configured again, the original data is still lost, and it is model dependent on whether the data state is both unpredictable or zero .
[0334] [0334] The persistence of an increase in SCM and its RAS (reliability, accessibility and serviceability) characteristics can also determine a change of Data State from valid to unpredictable. If persistence is exceeded, the state of the data is expected to change from valid to unpredictable.
[0335] [0335] A transition from both zero or unpredictable data states to the valid Data State occurs with the first successful writing. Due to any difference between writing data size and SCM Increment target size, the change to valid does not describe the actual condition of any data location not yet written. Such a location, prior to a first write access, is still effectively described as zero or unpredictable.
[0336] 1. Estado de operação muda de operacional para erro temporário ou erro permanente, mas não reporta uma operação de falha. 2. Estado de operação muda de erro temporário para operacional. 3. Estado de operação muda de erro temporário para erro permanente. 4. Alteração de classificação. [0336] After an SCM increment is configured, an unsolicited notification is made pending when any one or more events occur that can be observed in response to the Storage SCM Information command. Examples are: 1. Operation status changes from operational to temporary error or permanent error, but does not report a failure operation. 2. Operation status changes from temporary to operational error. 3. Operating status changes from temporary error to permanent error. 4. Change of classification.
[0337] 1. Estado de Dados muda de zerado ou imprevisível para válido. 2. Um comando de Memória de classe de armazenamento de Configuração se completa. 3. Um comando de Memória de classe de armazenamento de Desconfiguração se completa. [0337] Examples where unsolicited notifications are not made pending include the following: 1. Data State changes from zero or unpredictable to valid. 2. A Configuration storage class Memory command is completed. 3. An Unconfiguration storage class Memory command is completed.
[0338] [0338] When a notification is pending, the program observes the notification and can issue the Storage SCM Information command to obtain the information. The Storage SCM Information command can also be issued at other times when the program would like information about SCM and / or SALE.
[0339] [0339] In one example, a notification includes a machine check interrupt that is issued to the program, with a corresponding CRW that indicates an event report. The program issues the CHSC Storage Event Information command and obtains a response block with a content code that signals a storage class memory change notification.
[0340] [0340] In one embodiment, the Storage SCM Information (SSI) command is a channel subsystem command issued by the program (for example, operating system) to obtain information about storage class memory and / or a SCM address list entry. In one example, the program issues a Channel Subsystem Call instruction and the SSI command is indicated on an instruction command block, which is sent to the channel subsystem. The command is performed on the channel subsystem and a response is returned in a response block, which is the remaining portion of the 4K-byte control block (that is, the requested information is stored in the main storage area designated for the block Give me an answer). Additional details regarding the operation of the command are described with reference to figure 5D.
[0341] [0341] Initially, the program generates the order block indicated above to request the Storage SCM Information command, STEP 580. The order block is obtained by the channel subsystem, STEP 582, and one or more verification of validity are made as for the validity of the order block (for example, valid length field, valid command order block format, installed command, etc.). If the requirement is not valid, INQUIRY 584, then a Response Code that indicates that the problem is placed in the response block, STEP 586, and the response block is returned, STEP 592.
[0342] [0342] However, if the requirement is valid, SURVEY 584, then the channel subsystem obtains the information from the machine (for example, processors, etc.), STEP 588, and fills in the response block, STEP 590. The response block is returned, STEP 592. For example, the information is contained in the machine's non-volatile storage and is loaded by firmware into the main storage accessible only by firmware during system startup. The channel subsystem (that is, firmware in this case) obtains the information by reading it from the main storage only accessible by firmware, and populates the response block.
[0343] [0343] In response to receiving information about storage class memory or otherwise, a decision can be made to change the configuration of storage class memory. This decision can be made manually or automatically by the program or another entity. The setting can be changed by adding increments or deleting increments, as described below.
[0344] [0344] In one example, to configure storage class memory, a Configuration Storage Class Memory command is used. This command requests an amount of storage class memory to be configured from the available group of the system. The quantity is specified as a size, encoded as an SCM increment count.
[0345] [0345] Unless otherwise stated, the number of SCM increments used to satisfy the requirement is in the initialized state. If the number of requested SCM increments can cause the limit of the maximum Configurable SCM increments to be exceeded, a specific Response Code is provided.
[0346] [0346] The contents of each increment are zeroes with a valid CBC. The applicable persistence rule associated with each configured SCM Increment is defined, for example, through manual controls.
[0347] [0347] An embodiment of a command request block for the Configuration Storage Class Memory command is shown in figure 7A. In one example, a Configuration 700 storage class Memory order block includes:
[0348] [0348] Length 702: A value that specifies a length of the command block request length.
[0349] [0349] Command code 704: A value that specifies the command code for the Configuration storage class Memory command.
[0350] [0350] Format (FMT) 706: A value that specifies the format of the command request block.
[0351] [0351] Total Size (TS) 708: A value that specifies the size of the requested storage class memory, encoded as an SCM increment count. The count of SCM increments already configured plus TS is not to exceed the limit of maximum Configurable SCM increments (MCI). If the number of SCM increments in the initialized state is less than the total specified size, a specific Response Code is provided.
[0352] [0352] Asynchronous Completion Correlator (ACC) 710: A value that is returned in the asynchronous completion notification field of a notification response described below. The correlator serves to summarize the original segment that initiated the requirement.
[0353] [0353] An embodiment of a command response block for the Configuration Storage Class Memory command is shown in figure 7B. In one embodiment, a command response block 730 includes:
[0354] [0354] Length 732: A value indicating the length of the response block command.
[0355] [0355] Response Code 734: A value that describes the results of trying to run the Configuration storage class Memory command.
[0356] [0356] If a defined Response Code is stored in the Response Code field, an asynchronous process is started to finish processing the command. If a Response Code other than the defined code is stored in the Response Code field, no SCM Increment is configured, no asynchronous process is started, and no subsequent notification is made. Completion of the asynchronous process is indicated in a notification response.
[0357] [0357] Format (FMT) 736: A value that indicates the format of the response block command.
[0358] [0358] The Configuration storage class Memory command is issued by the program to request an amount of storage class memory to be configured for the SCM address space. An embodiment of the logic used to configure the SCM is described with reference to figure 7C.
[0359] [0359] Initially, the program issues a Channel Subsystem Call instruction that includes a Configuration SCM command, STEP 740. The order block of the Configuration SCM command is obtained by the channel subsystem, STEP 742, and the channel subsystem attempts to execute the command, STEP 744. If the attempt to execute the command produces a Response Code that does not indicate success, INQUIRY 746, then the Response Code is placed in the response block of the Configuration SCM command , STEP 748, and the response block is returned, STEP 750.
[0360] [0360] If a successful Response Code is indicated, SURVEY 746, then the Response Code is placed in the response block, STEP 752, and the response block is returned, STEP 754. In this example, a Response Code of success indicates that the order block length field is valid; the command is available on the system; the command request block has a valid format; the channel subsystem is capable of carrying out the command (that is, not occupied); the total size requested does not exceed the limit of maximum configurable SCM increments of the requested configuration; and the total size requested does not exceed the number of SCM increments in the initialized state.
[0361] [0361] Additionally, an asynchronous process to complete the configuration is started, STEP 756. Additional details regarding this processing are described with reference to figure 7D.
[0362] [0362] In one embodiment, asynchronous processing performs the configuration to allocate the one or more increments, STEP 760. For example, for each SCM Increment configured, internal controls are changed to allow the newly configured increment to be accessible for security requirements. I / O movement for that partition. In particular, in response to the channel subsystem receiving the CHSC Configuration command, the channel subsystem firmware examines internal tables to confirm that there are sufficient increments to satisfy the requirement and to ensure that the requirement does not exceed the configurable SCM increments maximum values for the configuration. If the requirement is valid, the firmware updates one or more tables to allocate the increments for the configuration and to place the increments in the operational state for the configuration. The increments are then accessible for I / O movement requirements (described above) from the configuration. Completion of the asynchronous process is indicated in a notification response, STEP 762.
[0363] [0363] Notification response data for the Configuration storage class Memory command is returned in a response block of a Storage Event Information (SEI) command. An embodiment of the notification response block format used for the Configuration storage class Memory command is described with reference to figure 8A.
[0364] [0364] In one embodiment, a notification response block 800 from the Configuration storage class Memory command includes:
[0365] [0365] Length 802: A value indicating the command length response block.
[0366] [0366] Response Code 804: A value that describes the results of trying to execute the CHSC Storage Event Information command.
[0367] [0367] Format (FMT) 806: A value that indicates the format of the response block command.
[0368] [0368] Notification Type 808: A value indicating that this is an EADM related notification.
[0369] [0369] P 810: When defined, it specifies that the channel subsystem has pending event information in addition to the information provided in response to this CHSC command.
[0370] [0370] V 812: When defined, it specifies that the channel subsystem recognized an overflow condition and event information was lost.
[0371] [0371] Content Code 814: A value that indicates that it is a response to the completion of the asynchronous process execution initiated by the Configuration storage class Memory command request.
[0372] [0372] Secondary Response Code 816: A value that further describes the results of the attempt to execute the Configuration SCM command.
[0373] [0373] When the Secondary Response Code is a specified value, the full amount of storage class memory, as originally requested, has been configured. Otherwise, Response Codes can be provided that indicate, for example, in the valid length field, Configuration SCM Command not installed, Configuration SCM command block has an invalid format, total requested size may exceed the limit of MCI, total size requested exceeds the number of SCM increments in the initialized state, busy channel subsystem.
[0374] [0374] Asynchronous Completion Correlator (ACC) 818: A value that is originally specified in the corresponding command request block.
[0375] [0375] An embodiment of the Storage Event Information command used to return the notification response block to the Configuration storage class Memory command is described with reference to figures 8B-8C.
[0376] [0376] The Storage Event Information command is used for the Storage Event Information that has been made pending by the channel subsystem. This command is usually executed as a result of the program having received a pending channel report of event information.
[0377] [0377] The execution of the Storage Event Information command can change the information contained in the channel subsystem. The Storage Event Information command is executed synchronously.
[0378] [0378] One embodiment of a command request block for the Storage Event Information command is described with reference to figure 8B. In one example, an order block 830 includes:
[0379] [0379] Length 832: This field specifies a length of the command request block.
[0380] [0380] Command code 834: This field specifies the Storage Event Information command.
[0381] [0381] Format (FMT) 836: A value that specifies the format of the command request block.
[0382] [0382] Notification Type Selection Mask (NTSM) 838: A mask where each bit position corresponds with a logical processor selector (LPS) value of the same numeric value. In one example, bit 0 is ignored and assumed to be one. When a bit position in a specified range starting at 1 is zero, a type of notification that corresponds to that bit position is not stored in the response block, and is discarded if it is recognized as pending. When such a bit is one, a type of notification that corresponds with the position of the bit can be stored in the response block.
[0383] [0383] In one embodiment, with reference to figure 8C, a response block 850 for the Storage Event Information command is described below:
[0384] [0384] Length 852: A value that specifies the length response block of the initial command. The completion length depends on the Response Code that is stored as a result of trying to run the Storage Event Information command.
[0385] [0385] If a Response Code other than a code indicating success is stored in the Response Code field, no information is stored in the response data area.
[0386] [0386] If a Response Code that indicates success is stored in the Response Code field, event information is stored in the response data area.
[0387] [0387] Response Code 854: A value that describes the results of trying to execute the Storage Event Information command.
[0388] [0388] For the Storage Event Information command, the response data area contains a portion of fixed length and a portion of variable length.
[0389] [0389] For a specified format response, when NT is non-zero, the format depends on the particular Notification Type, and the format of the Content Code dependent field depends on the particular Notification Type and the Content Code field ( CC), taken together.
[0390] [0390] Format (FMT) 856: A value that specifies the format of the response block command.
[0391] [0391] Notification Type (NT) 858: A value that indicates a type of notification (NT). A specific value is provided for the SCM Configuration command.
[0392] [0392] Marker P 860: When defined, it specifies that the channel subsystem has pending event information in addition to the information provided in response to this CHSC command. The program can obtain additional information by running the Storage Event Information command again. When not defined, this marker specifies that the channel subsystem has no additional pending event information.
[0393] [0393] Marker V 862: When defined, it specifies that the channel subsystem recognized an overflow condition and event information was lost. The overflow condition was recognized while the event information not contained in the response data area was the most recently pending information. Overflow does not affect the information contained in the response data area.
[0394] [0394] Content Code (CC) 864: A value that describes the type of information that is contained in the response data area. In one example, the value indicates a storage class memory change notification where one or more SCM Increments have changed state or state.
[0395] [0395] Field Dependent on Content Code 866: This field may include additional information regarding the event.
[0396] [0396] Success Notification of a configuration change can request the program to issue the Storage SCM Information command for details regarding the configuration.
[0397] [0397] In addition to increasing storage class memory, storage class memory can be decreased. An Unconfiguration Storage Class Memory command requires an amount of storage class memory to be removed from the SCM address space of the requirement configuration. An SCM increment to be unconfigured must be in the configured state.
[0398] [0398] The SCM increments to be unconfigured are specified in an SCM requirement list increment, described here. One or more contiguous SCM Increments can be specified in an SCM increment requirement list entry (SIRLE). A separate SIRLE can be specified for each list of increments (also known as an extension) that is not contiguous with any other list of increments.
[0399] [0399] Regardless of persistence rules, a successful deconfiguration of an SCM increment places the increment in the uninitialized state. When the zeroing step is complete, an SCM increment changes from the uninitialized state to the initialized state.
[0400] [0400] An embodiment of a command request block for the unconfiguration storage class memory command is shown in figure 9A. A 900 command request block for the Unconfiguration storage class Memory command includes, for example:
[0401] [0401] Length 902: A value that specifies a length of the command request block. In one example, the length is 32+ (Nxl6) bytes, where N is the SCM Increment count requirement list entries (SIRLEs). A valid length in this example is equally divisible by 16 and is in the range (32 + 1x16) <LI <(32 + 253x16).
[0402] [0402] Command code 904: A value that specifies the command code for the Unconfiguration storage class Memory command.
[0403] [0403] Format (FMT) 906: A value that specifies the format of the command request block.
[0404] [0404] Asynchronous Completion Correlator (ACC) 908: A value that is returned in the asynchronous completion notification, described above.
[0405] [0405] SCM Increment Requirement List 910: This field includes an SCM Increment Requirement List (SIRL). An SCM increment requirement list includes one or more entries (SIRLEs). The length of the SIRL is determined from the length field value.
[0406] [0406] An SCM requirement list entry increment (SIRLE) specifies the size and location of a specified extent of storage class memory (for example, a list of increments). An SCM extension or extension is the specified size of storage class memory.
[0407] [0407] Referring to figure 9B, in one example, SIRLE 920 includes:
[0408] [0408] Total Size (TS) 922: A value that specifies the size of the storage class memory to be unconfigured, encoded as an SCM increment count.
[0409] [0409] Departure SCM address (SA) 924: A value that is an SCM address and is the location in the SCM address space from which to remove the first or only SCM Increment configured by SIRLE. Less significant bit positions that can constitute an offset within the first SCM Increment are ignored and assumed to be zeroes, in this example.
[0410] [0410] When the total size is greater than one, each additional SCM Increment in addition to the first increment is located at an SCM address that is equally divisible by the SCM increment size, which contains a configured SCM Increment, and in that the location is contiguous with the last byte of the previous SCM Increment. In other words, at the next consecutive location.
[0411] [0411] If the space described by the starting address and the total size, taken together, is not completely full of SCM increments configured to the specified Response Code is provided, no SCM Increment is misconfigured, no asynchronous process is started, and no subsequent notification occurs.
[0412] [0412] Upon successful completion, each unconfigured SCM Increment enters the reserved state and is then reset to zero before being placed in the waiting state.
[0413] [0413] A command response block for the Unconfiguration storage class Memory command is shown in figure 9C. In one embodiment, a 950 command response block includes:
[0414] [0414] Length 952: A value indicating the command length response block.
[0415] [0415] Response Code 954: A value that describes the results of trying to execute the Unconfiguration storage class Memory command.
[0416] [0416] If the Response Code of a specified value is stored in the Response Code field, an asynchronous process is started to finish processing the command. If the Response Code other than the specified value is stored in the Response Code field, no SCM Increment is misconfigured, no asynchronous process is started, and no subsequent notification is made. Completion of the asynchronous process is indicated in a notification response.
[0417] [0417] Before the synchronous part of the Unconfiguration storage class Memory command completes with a specified Response Code, all entries in the SCM increment requirement list are examined to ensure that all specified SCM Increments are in the configured state.
[0418] [0418] Format (FMT) 956: A value that indicates the format of the response block command.
[0419] [0419] An embodiment of the logic associated with the Unconfiguration SCM command is described with reference to figures 9D-9E.
[0420] [0420] Initially, the program issues a Channel Subsystem Call instruction that includes a SCM Command, STEP 970. The order block of the SCM Command is obtained by the channel subsystem, STEP 972, and the channel subsystem tries to execute the command, STEP 974. If the attempt to execute the command produces the Response Code that does not indicate success, INQUIRY 976, then the Response Code is placed in the response block of the Unconfiguration SCM command , STEP 978, and the response block is returned, STEP 980.
[0421] [0421] If a successful Response Code is indicated, SURVEY 976, then the Response Code is placed in the response block, STEP 982, and the response block is returned, STEP 984. In this example, a Response Code of success indicates that the order block length field is valid; the command is available on the system; the command request block has a valid format; the channel subsystem is capable of carrying out the command (that is, not occupied); and the SCM increments were originally in the configured state.
[0422] [0422] Additionally, an asynchronous process to complete the deconfiguration is initiated, STEP 986. Additional details regarding this processing are described with reference to figure 9E.
[0423] [0423] In one embodiment, asynchronous processing performs the unconfiguration, STEP 990. For example, the one or more increments are deallocated. An SCM increment is moved from the configured state to the reserved state. Upon entering the reserved state, a zeroed process ensures, and when complete, that the SCM increment changes to the standby state. Completion of the asynchronous process is indicated in a notification response, STEP 992.
[0424] [0424] The notification response data for the Unconfiguration storage class Memory command is returned in the response block of the Storage Event Information (SEI) CHSC command. An example of this response block is described with reference to figure 8A. However, the Content Code in this example indicates that this is a response to the completion of the asynchronous process execution initiated by the unconfiguration Storage Class Memory command request. Similarly, the secondary Response Code further describes the results of attempting to execute the Unconfiguration storage class Memory command.
[0425] [0425] In an additional embodiment, the allocation and deallocation of storage increments can be requested through a panel presented to a user. For example, a service element is used to provide a graphical interface through which a user can specify parameters for the system.
[0426] 1. Especificar os incrementos configuráveis máximos (MCI) para uma dada configuração; 2. Alocar incrementos a uma configuração; 3. Desalocar incrementos a partir de uma configuração. [0426] For storage class memory, a panel called the storage class memory allocation panel allows the user to perform the following operations: 1. Specify the maximum configurable increments (MCI) for a given configuration; 2. Allocate increments to a configuration; 3. Deallocate increments from a configuration.
[0427] [0427] The panel also allows observing allocations of configuration and MCI increments, and the number of increments in the available, unavailable, and uninitialized clusters. When, due to an action in the SE, an allocation of increments changes or when the size of one of the clusters changes, a notification is sent to the settings.
[0428] [0428] Described in detail above is an installation to manage storage class memory. It provides an abstraction to allow the program to access memory without specific knowledge of memory. According to one or more aspects of the present invention, a capability is provided to move data between main storage and SCM; to empty or release SCM; to configure or unconfigure SCM; and to find out the SCM configuration. Other capabilities are also provided.
[0429] [0429] In one embodiment, storage class memory is presented as a flat memory space for user-level programs, regardless of their physical implementation by multiple devices and I / O adapters.
[0430] [0430] Details regarding channel subsystems and / or an ADM installation are described in U.S. Patent No. 5,377,337, entitled "Method and Means for Enabling Virtual Address Control By Software Users Over A Hardware Page Transfer Control Entity, "Antognini et al, issued on December 27, 1994; US Serial No. 5,442,802, entitled "Asynchronous Co-Processor Data Mover Method and Means," Brent et al, issued August 15, 1995; and U.S. Patent No. 5,526,484, entitled "Method and System for Pipelining processing of Channel Command Words," issued June 11, 1996, each of which is incorporated herein by reference in its entirety.
[0431] [0431] Additionally, additional information regarding a channel subsystem and instructions associated with it (for a particular z / Architecture® implementation) is provided below:
[0432] [0432] Input / Output (I / O)
[0433] [0433] The terms "input" and "output" are used to describe the transfer of data between I / O devices and main storage. An operation that involves this type of transfer is referred to as an I / O operation. the facilities used to control I / O operations are collectively referred to as the channel subsystem. (I / O devices and their control units attach to the channel subsystem.)
[0434] [0434] The channel subsystem
[0435] [0435] The channel subsystem directs the flow of information between I / O devices and main storage. It retrieves CPUs from the communication task directly with I / O devices and allows data processing to proceed concurrently with I / O processing. The channel subsystem uses one or more channel paths as the communication link in managing information flow to or from I / O devices. As part of I / O processing, the channel subsystem also performs a path management operation by testing the availability of the channel path, chooses an available channel path, and initiates the performance of the I / O operation by the device.
[0436] [0436] Within the channel subsystem are the subchannels. A subchannel is provided for and dedicated to each I / O device accessible to the program via the channel subsystem.
[0437] [0437] The installation of multiple defined subchannels is an optional installation. When it is installed, subchannels are partitioned into multiple sets of subchannels, and each set of subchannels can provide a dedicated subchannel for an I / O device. Depending on the model and the interface used, some I / O devices can only be allowed to be accessed through certain sets of subchannels.
[0438] [0438] Each subchannel provides information regarding the associated I / O device and its attachment to the channel subsystem. The subchannel also provides information regarding I / O operations and other functions that involve the associated I / O device. The subchannel is the means by which the channel subsystem provides information about I / O devices associated with CPUs, which obtain this information by executing I / O instructions. The actual number of subchannels provided depends on the model and configuration; the maximum addressing capacity is 0-65,535 in each subchannel set.
[0439] [0439] I / O devices are attached via control units to the channel subsystem via channel paths. Control units can be attached to the channel subsystem by more than one channel path, and an I / O device can be attached to more than one control unit. In all, an individual I / O device can be accessible to the channel subsystem by as many as eight different channel paths via a subchannel, depending on the model and configuration. The total number of channel paths provided by a channel subsystem depends on the model and configuration; the maximum addressing capacity is 0 to 255.
[0440] [0440] The performance of a channel subsystem depends on its use and on the system model in which it is implemented. Channel paths are provided with different data transfer capabilities, and an I / O device designed to transfer data only at a specified rate (a tape drive or disk storage, for example) can operate on only one channel path that can accommodate at least this data rate.
[0441] [0441] The channel subsystem contains common facilities for controlling I / O Operations. When these facilities are provided in the form of separate standalone equipment designed specifically to control I / O devices, I / O operations are completely overlapped with activity on the CPUs. The only major storage cycles required by the channel subsystem during operations I / O units are those needed to transfer data and control information to or from the final locations in the main storage, along with these cycles that may be required for the channel subsystem to access the subchannels when they are implemented as part of non-addressable main storage. These cycles do not delay CPU programs, except when both the CPU and the channel subsystem concurrently attempt to reference the same main storage area.
[0442] [0442] Subchannel Sets
[0443] [0443] When the installation of multiple defined subchannels is installed, subchannels are partitioned into multiple sets of subchannels. There can be up to four subchannel sets, each identified by a subchannel set identifier (SSID). When the installation of multiple defined subchannels is not installed, there is only one set of subchannels with an SSID of zero. When the installation of multiple defined subchannels is not allowed, only a set of zero subchannels is visible to the program.
[0444] [0444] Subchannels
[0445] [0445] A subchannel provides the logical appearance of a device for the program and contains the information necessary to support a single I / O operation. The subchannel consists of internal storage that contains information in the form of a channel program designation, channel path identifier, device number, count, status indications, and I / O interrupt subclass code, as well as information in the path availability and functions pending or being performed. I / O operations are initiated with a device by executing I / O Instructions that designate the subchannel associated with the device.
[0446] [0446] Each device is accessible via a subchannel in each channel subsystem to which it is assigned during configuration at installation time. The device can be a physically identifiable unit or it can be housed inside a control unit. For example, on certain disk storage devices, each actuator used for data recovery is considered to be a device. In all cases, a device, from the point of view of the channel subsystem, is an entity that is uniquely associated with a subchannel and that responds to the selection by the channel subsystem using the communication protocols defined for the type of communication path. channel through which it is accessible.
[0447] [0447] In some models, subchannels are provided in blocks. In these models, more subchannels can be provided than there are attached devices. The subchannels that are provided but do not have devices designed for those are not used by the channel subsystem to perform any function and are indicated by storing the valid bit of the associated device number as zero in the subchannel information block of the subchannel.
[0448] [0448] The number of subchannels provided by the channel subsystem is independent of the number of channel paths for the associated devices. For example, a device accessible via alternate channel paths is still represented by a single subchannel. Each subchannel is addressed using a 16-bit binary subchannel number and a two-bit SSID when the subchannel assembly installation is installed.
[0449] [0449] After I / O processing at the subchannel was requested by executing the SUBCANAL DEPARTURE, the CPU is released for another job, and the channel subsystem assembles or dismounts data and synchronizes the transfer of data bytes between the device I / O and main storage. To achieve this, the channel subsystem maintains and updates an address and count that describe the destination or data source in the main store.
[0450] [0450] Similarly, when an I / O device provides signals that must be brought to the attention of the program, the channel subsystem transforms the signals into state information and stores the information in the subchannel, where it can be retrieved by the program .
[0451] [0451] Attaching Input / Output Devices
[0452] [0452] Channel paths
[0453] [0453] The channel subsystem communicates with I / O devices through channel paths between the channel subsystem and control units. A control unit can be accessible by the channel subsystem by more than one channel path. Similarly, an I / O device can be accessible by the channel subsystem via more than one control unit, each having one or more channel paths to the channel subsystem.
[0454] [0454] Devices that are attached to the channel subsystem by multiple channel paths configured for a subchannel, can be evaluated by the channel subsystem using any of the available channel paths. Similarly, a device having dynamic reconnection functionality and operating in multipath mode can be initialized to operate such that the device can choose any of the available channel paths configured for the subchannel, when it logically reconnects to the subchannel. channel subsystem to continue an I / O Operations chain.
[0455] [0455] The channel subsystem can contain more than one type of channel path.
[0456] [0456] Examples of channel path types used by the channel subsystem are the ESCON I / O interface, FICON I / O interface, FICON converted I / O interface, and System I / O interface IBM / 360 and System / 370. The term "serial I / O interface" is used to refer to the ESCON I / O interface, the FICON I / O interface, and the converted FICON I / O interface. The term "Parallel I / O Interface" is used to refer to the IBM / 360 and System / 370 System I / O Interface.
[0457] [0457] The ESCON I / O interface is described in the IBM Enterprise Systems Architecture / 390 System Library publication ESCON I / O Interface, SA22-7202, which is incorporated here by reference in its entirety.
[0458] [0458] The FICON I / O interface is described in the Fiber Channel of ANSI standards document - -2 Single Byte Command Code Sets (FC-SB-2).
[0459] [0459] The IBM / 360 and System / 370 System I / O Interface is described in the IBM / 360 and System / 370 System Library Publishing System I / O Interface Channel to control the OEMI Unit , GA22-6974, which is incorporated herein by reference in its entirety.
[0460] [0460] Depending on the type of channel path, the facilities provided by the channel path, and the I / O device, an I / O operation can take place in one of three modes, frame multiplexing mode, pulse mode , or byte multiplexing mode.
[0461] [0461] In frame multiplexing mode, the I / O device can be logically connected to the channel path for the duration of the execution of a channel program. The installations of a channel path capable of operating in the frame multiplexing mode can be divided by a number of I / O devices that operate concurrently. In this mode, the information needed to complete an I / O operation is divided into frames that can be interlaced with I / O operations frames for other I / O devices. During this period, multiple I / O devices are considered to be logically connected to the channel path.
[0462] [0462] In pulse mode, the I / O device monopolizes a channel path and is logically connected to the channel path for the transfer of an information pulse. No other device can communicate on the channel path during the time that an explosion is transferred. The pulse can consist of a few bytes, a complete data block, a sequence of blocks with associated control and status information (block lengths can be zero), or status information that monopolizes the channel path. Channel path installations capable of operating in impulse mode can be divided by a number of I / O devices that operate concurrently.
[0463] [0463] Some channel paths can tolerate an absence of data transfer for about half a minute during a pulse mode operation, such as when a long gap in the magnetic tape is read. Equipment malfunction can be indicated when an absence of data transfer exceeds the prescribed limit.
[0464] [0464] In the byte multiplexing mode, the I / O device is logically connected to the channel path only for a short time. The installations of a channel path capable of operating in byte multiplexing mode can be divided by a number of I / O devices that operate concurrently. In this mode, all I / O Operations are divided into short time intervals during which only one segment of information is transferred over the channel path. During such an interval, only one device and its associated subchannel are logically connected with the channel path. The intervals associated with the concurrent operation of multiple I / O devices are sequenced in response to demands from the devices. The installation of a channel subsystem associated with a subchannel exercises its controls for any operation only for the time necessary to transfer a segment of information. The segment can consist of a single byte of data, a few bytes of data, a status report from the device, or a control sequence used to start a new operation.
[0465] [0465] Ordinarily, devices with high data transfer rate requirements operate with the channel path in frame multiplexing mode, smaller devices operate in pulse mode, and the slower devices operate in byte multiplexing mode . Some control units have a manual switch to set the desired operating mode.
[0466] [0466] An I / O operation that occurs on a type of channel path parallel I / O interface can occur in both pulse mode and byte multiplexing mode depending on the facilities provided by the channel path and the device of I / O. For improved performance, some channel paths and control units are provided with facilities for high speed transfer and data transfer. View the IBM Library Publishing System system / 360 and System / 370 I / O
[0467] [0467] The Interface Channel to control the OEMI Unit, GA22-6974, for a description of those two facilities, which is incorporated here by reference in its entirety.
[0468] [0468] An I / O operation that takes place on a type of serial I / O interface of the channel path can occur in both frame multiplexing and pulse mode. For improved performance, some control units that attach to the serial I / O Interface provide the ability to provide detection data for the concurrent program with the presentation of the unit verification status, if allowed to do so by the program.
[0469] [0469] Depending on the control unit or channel subsystem, access to a device via a subchannel can be restricted to a single type of channel path.
[0470] [0470] The modes and features described above affect only the protocol used to transfer information about the channel path and transmission speed. No effect is observed by the CPU or channel programs with respect to the way these programs are run.
[0471] [0471] Control units
[0472] [0472] A control unit provides the necessary logical capabilities to operate and control an I / O device and adapts the characteristics of each device so that it responds to the standard form of control provided by the channel subsystem.
[0473] [0473] Communication between the control unit and the channel subsystem occurs over a channel path. The control unit accepts control signals from the channel subsystem, controls the timing of data transfer over the channel path, and provides indications that refer to the state of the device.
[0474] [0474] The I / O device attached to the control unit can be designed to perform only certain limited operations, or it can perform many different operations. A typical operation is moving a recording medium and recording data. To achieve its operations, the device needs detailed signal sequences peculiar to its type of device. The control unit decodes the commands received from the channel subsystem, interprets them for the particular type of device, and provides the signal sequence necessary for the performance of the operation.
[0475] [0475] A control unit can be housed separately, or it can be integrated physically and logically with the I / O device, the channel subsystem, or a CPU. In the case of most electromechanical devices, a well-defined interface exists between the device and the control unit because of the difference in the type of equipment that the control unit and the device require. These electromechanical devices are generally of a type where only one device in a group attached to a control unit is needed to transfer data at a time (magnetic tape drives or disk access mechanisms, for example), and the drive control is divided among a number of I / O devices. On the other hand, in some electronic I / O devices, such as the channel-to-channel adapter, the control unit does not have its own identity.
[0476] [0476] From the programmer's point of view, most of the functions performed by the control unit can be merged with those performed by the I / O device. Therefore, normally no specific mention of the control unit function is made in this description; the performance of the I / O Operations is described as if the I / O devices communicated directly with the channel subsystem. Reference is made to the control unit only when emphasizing a function performed by it or when describing how the division of the control unit among a number of devices affects the performance of I / O operations.
[0477] [0477] I / O devices
[0478] [0478] An input / output (I / O) device provides external storage, a means of communication between data processing systems, or a means of communication between a system and its environment. I / O devices include such equipment as magnetic tape drives, direct access storage devices (for example, disks), display units, keyboard-type devices, printers, teleprocessing devices, and sensor-based equipment . An I / O device can be physically distinct equipment, or it can share equipment with other I / O devices.
[0479] [0479] Most types of I / O devices, such as printers, or tape devices, use external media, and these devices are physically distinguishable and identifiable. Other types are electronic only and do not directly manipulate physical recording media. The channel-to-channel adapter, for example, provides for data transfer between two channel paths, and the data never reaches a physical recording medium outside of main storage. Similarly, communication controllers can handle the transmission of information between the data processing system and a remote station, and its input and output are signals on a transmission line.
[0480] [0480] In the simplest case, an I / O device is attached to a control unit and is accessible from a channel path. Switching equipment is available to make some devices accessible from two or more channel paths by switching devices between control units and switching control units between channel paths. Such switching equipment provides multiple paths by which an I / O device can be evaluated. Multiple channel paths to an I / O device are provided to improve I / O performance or availability, or both, within the system. The management of multiple channel paths for devices is under the control of the channel subsystem and the device, but the channel paths can be controlled indirectly by the program.
[0481] [0481] I / O addressing
[0482] [0482] Four different types of I / O addressing are provided by the channel subsystem for the necessary addressing of the various components: channel path identifiers, subchannel numbers, number of devices, and, although not visible to programs, addresses dependent on the type of channel path. When the installation of multiple defined subchannels is installed, the subchannel pool identifier (SSID) is also used in I / O addressing.
[0483] [0483] Subchannel set identifier
[0484] [0484] The subchannel set identifier (SSID) is a two-bit value assigned to each provided subchannel set.
[0485] [0485] Channel path identifier
[0486] [0486] The channel path identifier (CHPID) is a system-unique eight-bit value assigned to each installed channel path on the system. A CHPID is used to address a channel path. A CHPID is specified by the address of the second operand of the RESTART CHANNEL PATH and used to designate the channel path that must be restarted. The channel paths through which a device is accessible are identified in the subchannel information block (SCHIB), each by its associated CHPID, when the Storage Subchannel is executed. CHPID can also be used in operator messages when it is necessary to identify a particular channel path. A system model can provide as many as 256 channel paths. The maximum number of channel paths and the designation of CHPIDs for channel paths depends on the system model.
[0487] [0487] Subchannel number
[0488] [0488] A subchannel number is a unique 16-bit value from the system used to address a subchannel. This value is unique within a subchannel set of a channel subsystem. The subchannel is addressed by eight I / O Instructions: CANCELLATION SUB-CHANNEL, EMPTY SUB-CHANNEL, MODIFICATION SUB-CHANNEL, SUMMARY SUB-CHANNEL, START SUB-CHANNEL, STORAGE SUB-CHANNEL, and TEST SUB-CHANNEL. All I / O functions for a specific I / O device are specified by the program by designating a subchannel designated for the I / O device. the subchannels in each subchannel set are always subchannel numbers designated within a single range of contiguous numbers. The lowest subchannel is subchannel 0. The highest subchannel of the channel subsystem has a subchannel number equal to one less than the number of subchannels provided. A maximum of 65,536 subchannels can be provided in each subchannel set. Typically, subchannel numbers are used only in communication between the CPU program and the channel subsystem.
[0489] [0489] Device number
[0490] [0490] Each subchannel that has an I / O device assigned to it also contains a parameter called the device number. The device number is a 16-bit value that is designated as one of the subchannel parameters at the time the device is assigned to the subchannel. The device number uniquely identifies a device for the program.
[0491] [0491] The device number provides a means to identify a device, regardless of any limitations imposed by the system model, configuration, or channel path protocols. The device number is used in communications that refer to the device that may occur between the system and the system operator. For example, the device number is entered by the system operator to designate the input device to be used for the initial program load.
[0492] [0492] Programming Note: The device number is assigned at device installation time and can have any value. However, the user must observe any restrictions on the device number assignment that may be required by the control program, support programs, or the particular control unit or particular I / O device.
[0493] [0493] Device Identifier
[0494] [0494] A device identifier is an address, not apparent to the program, that is used by the channel subsystem to communicate with the I / O devices. The type of device identifier used depends on the type of specific channel path and the protocols provided. Each subchannel contains one or more device identifiers.
[0495] [0495] For a parallel I / O interface type channel path, the device identifier is called a device address and consists of an eight-bit value. For an ESCON I / O interface, the device identifier consists of a four-bit control unit address and an eight-bit device address.
[0496] [0496] For a FICON I / O interface, the device identifier consists of an eight-bit control unit image ID and an eight-bit device address. For a converted FICON I / O interface, the device identifier consists of a four-bit control unit address and an eight-bit device address.
[0497] [0497] The device address identifies the particular I / O device (and, on the parallel I / O Interface, the control unit) associated with a subchannel. The device address can identify, for example, a particular magnetic tape drive, disk access mechanism, or transmission line. Any number in the range 0 to 255 can be designated as a device address.
[0498] [0498] Fiber channel extensions
[0499] [0499] The installation of fiber channel extensions (FCX) is an optional installation that provides the formation of a channel program that is composed of a transport control word (TCW) that designates a transport command control block (TCCB) and a transport status block (TSB). The TCCB includes a transport command area (TCA) that contains a list of up to 30 I / O commands that are in the form of device command words (DCWs). The TCW and its TCCB can specify both a read operation and a write operation. In addition to the IRB, the TSB contains the completion status and other information related to the TCW channel program.
[0500] [0500] The FCX facility provides the ability to designate directly or indirectly any or all of the TCCB, the input data storage area, and the output data storage area. When a storage area is assigned directly, TCW specifies the location of a single contiguous storage block. When a storage area is designated indirectly, TCW designates the location of a list of one or more indirect transport data address words (TIDAWs). TIDAW lists and the storage area designated by each TIDAW in a list are restricted from crossing 4K-byte limits.
[0501] [0501] The FCX installation still provides an interrogation operation that can be initiated by the CANCELING SUBChannel instruction to determine the status of an I / O operation.
[0502] [0502] I / O Command Words
[0503] [0503] An I / O command word specifies a command and contains information associated with the command. When the FCX installation is installed, there are two elementary forms of I / O command words which are the channel command word (CCW) and the device command word (DCW).
[0504] [0504] A CCW is 8-bytes in length and specifies the command to be executed. For commands that initiate certain operations, CCW also designates the storage area associated with the operation, the count of data bytes, the action to be taken when the command completes, and other options. All I / O devices recognize CCWs.
[0505] [0505] A DCW is 8-bytes long and specifies the command to be executed, the count of data bytes, and other options. I / O devices that support FCX recognize DCWs.
[0506] [0506] Transport Command Word (TCW)
[0507] [0507] A TCW designates a transport command control block (TCCB) that contains a list of commands to be transported and executed by an I / O device. the TCW also designates the storage areas for the commands in the TCCB as well as a transport status block (TSB) to contain the status of the I / O operation.
[0508] [0508] Channel Program Organization
[0509] [0509] When the FCX installation is not installed, there is a single form of channel program which is the CCW channel program. When the FCX installation is installed, there is an additional form of channel program which is the TCW channel program. Both forms of channel programs are described below.
[0510] [0510] CCW channel program
[0511] [0511] A channel program that is composed of one or more CCWs is called a CCW channel program (CCP). Such a channel program contains one or more CCWs that are connected and arranged logically for sequential execution by the channel subsystem.
[0512] [0512] TCW channel program
[0513] [0513] A channel program that is made up of a single TCW is called a TCW channel program. A TCW designates a transport command control block (TCCB) that contains 1 to 30 DCWs. The DCWs within the TCCB are connected and arranged in a logical way for sequential execution. For DCWs that specify control information, the TCCB also contains the control information for these commands. The TCW also designates the storage area or areas for the DCWs that specify the transfer of data from or to the device and the location of a transport status block (TSB) for the completion state. The TCCB and storage areas for data transfer can be specified as either contiguous or non-contiguous storage.
[0514] [0514] TCW also designates a TSB for completion status.
[0515] [0515] Execution of I / O Operations
[0516] [0516] I / O operations are initiated and controlled by information in four types of formats: the SUBCANAL DEPARTURE instruction, transport command words, I / O command words, and orders. The Start Subchannel instruction is performed by a CPU and is part of the CPU program that supervises the flow of requests for I / O operations from other programs that manage or process I / O data.
[0517] [0517] When the SUBChannel START is executed, parameters are passed to the subchannel target that requires the channel subsystem to perform a start function with the I / O device associated with the subchannel. The channel subsystem performs the start function using information in the subchannel, including information passed during the execution of the Start Subchannel instruction, to find an accessible channel path for the device.
[0518] [0518] Once the device has been selected, the execution of an I / O operation is achieved by decoding the CCW execution by the channel subsystem and the I / O device, for the CCW channel programs, or for the TCW channel programs, transporting the TCCB to the I / O device through the channel subsystem and decoding and executing a DCW by the device. I / O command words, and transport command words are fetched from main storage, although the modifier bits in the command code of a CCW DCW can specify device-dependent conditions for performing an operation on the device .
[0519] [0519] Operations peculiar to a device, such as tape rewinding or positioning the access mechanism on a disk drive, are specified by orders that are decoded and performed by the I / O devices. Orders can be transferred to the device as modifier bits in the command code of a control command, can be transferred to the device as data during a control or writing operation, or can be made available to the device by other means.
[0520] [0520] Start of the Start Function
[0521] [0521] CPU programs initiate I / O Operations with the instruction from the SUBCANAL DEPARTURE. This instruction passes the contents of an operation-order block (ORB) to the subchannel.
[0522] [0522] If the ORB specifies a CCW channel program, the contents of the ORB include the Sub-Channel Key, the address of the first CCW to be executed, and a specification of the format of the CCWs. The CCW specifies the command to be executed and the storage area, if any, to be used. If the ORB specifies a TCW channel program, the contents of the ORB include the Subchannel Key and the address of the TCW to be executed. The TCW designates the TCCB that contains the commands to be carried to the device for execution, the storage area or the areas, if any, to be used for data transfer, and the TSB to contain the status of the data transfer operation. I / O.
[0523] [0523] When the ORB contents pass to the subchannel, the SUBCANAL DEPARTURE execution is complete. The results of executing the instruction are indicated by the condition code defined in the program status word.
[0524] [0524] When installations become available and the ORB specifies a CCW channel program, the channel subsystem fetches the first CCW and decodes it according to the format bit specified in the ORB. If the format bit is zero, format-0 CCWs are specified. If the format bit is one, format-1 CCWs are specified. and format-0 and format-1 CCWs contain the same information, but the fields are arranged differently in the format-1 CCW so that 31-bit addresses can be specified directly in the CCW. When facilities become available and the ORB specifies the TCW channel program, the channel subsystem fetches the designated TCW and transports the assigned TCCB to the device. The storage areas designated by TCW for transferring data to or from the device are 64-bit addresses.
[0525] [0525] Sub-Channel Operating Modes
[0526] [0526] There are two modes of operation for the Subchannel. A subchannel enters the transport mode when the FCX installation is installed and the start function is defined in the subchannel as a result of executing a Start Subchannel instruction that specifies a TCW channel program. The subchannel remains in the transport mode until the start function is restarted on the subchannel. At all other times, the subchannel is in command mode.
[0527] [0527] Path Management
[0528] [0528] If the ORB specifies a CCW channel program and the first CCW passes certain validity tests and does not have the drop-down marker specified as one or if the ORB specifies a TCW channel program and a designated TCW passes certain validity, the channel subsystem attempts to select the device by choosing a channel path from the group of channel paths that are available for selection. A control unit that recognizes the device identifier logically connects to the channel path and responds to your selection.
[0529] [0529] If the ORB specifies a CCW channel program, the channel subsystem sends the CCW command code portion over the channel path, and the device responds with a status byte that indicates whether the command can be executed . The control unit can logically disconnect from the channel path at this point, or it can remain connected to initiate data transfer.
[0530] [0530] If the ORB specifies a TCW channel program, the channel subsystem uses information in a designated TCW to transfer the TCCB to the control unit. The contents of the TCCB are ignored by the channel subsystem and only have meaning for the control unit and I / O device.
[0531] [0531] If the attempted selection does not occur as a result of either a busy indication or a non-operational path condition, the channel subsystem attempts to select the device by an alternate channel path if one is available. When the selection has been attempted on all paths available for selection and the occupied condition persists, the operation remains pending until one path becomes free. If a non-operational path condition is detected on one or more of the channel paths on which the device selection was attempted, the program is alerted by a subsequent I / O interruption. I / O interruption occurs either by executing the channel program (assuming the device was selected on an alternate channel path) or as a result of the execution being abandoned since non-operational path conditions were detected in all paths channel on which device selection was attempted.
[0532] [0532] Channel Program Execution
[0533] [0533] If the command is initiated on the device and the execution of the command does not require any data to be transferred to or from the device, the device can signal the end of the operation immediately with the receipt of the command code. In operations involving date transfer, the subchannel is defined so that the channel subsystem will respond to service requests from the device and takes on additional control of the operation.
[0534] [0534] An I / O operation may involve transferring data to or from a storage area, designated by a single CCW or TCW, or to or from a number of non-contiguous storage areas. In the latter case, in general a list of CCWs is used to perform the I / O operation, with each CCW designating a contiguous storage area and the CCWs are coupled by chaining data. The data chaining is specified by a marker on the CCW and causes the channel subsystem to search for another CCW by exhausting or filling the storage area designated by the current CCW. The storage area designated by the CCW sought in the data chaining belongs to the I / O operation already in progress on the I / O device, and the I / O device is not notified when a new CCW is fetched.
[0535] [0535] The provision is made in the CCW format for the programmer to specify that when the CCW is decoded, the channel subsystem requests an I / O interruption as early as possible, thereby notifying a CPU program that the thread progressed at least as much as that CCW in the channel program.
[0536] [0536] To complement the dynamic address translation in CPUs, indirect CCW data addressing and modified CCW indirect data addressing are provided.
[0537] [0537] When the ORB specifies a CCW channel program and CCW indirect data addressing is used, a marker in the CCW specifies that an indirect data address list should be used to designate the storage areas for that CCW. Each time the limit of a storage block is reached, the list is referenced to determine the next storage block to be used. The ORB specifies whether the size of each storage block is 2K bytes or 4K bytes.
[0538] [0538] When the ORB specifies a CCW channel program and modified CCW indirect data addressing is used, a marker in the ORB and a marker in the CCW specifies that a modified indirect data address list should be used to designate the areas storage for that CCW.
[0539] [0539] Every time the specified byte count for a storage block is reached, the list is referenced to determine the next storage block to be used. Unlike when indirect data addresses are used, the block can be specified at any limit and length up to 4K, provided that data transfer over a 4K-byte limit is not specified.
[0540] [0540] When the ORB specifies a TCW channel program and indirect transport data addressing is used, markers in the TCW specify whether a list of indirect transport data addresses should be used to designate the storage areas containing the TCCB and whether an indirect transport data address list is used to designate the data storage areas associated with the DCWs in the TCCB. Each time the specified byte count for a storage block is reached, the corresponding indirect transport data address list is referenced to determine the next storage block to be used.
[0541] [0541] CCW indirect data addresses and modified CCW indirect data addresses allow essentially the same CCW strings to be used for a program that runs with dynamic address translation active on the CPU since it can be used if the CPU was operating with equivalent contiguous actual storage. CCW indirect data addresses allow the program to designate data blocks having absolute storage addresses of up to 264-1 regardless of whether format-0 or format-1 CCWs have been specified in the ORB. Modified CCW indirect data addresses allow the program to designate blocks of data having absolute storage addresses of up to 264-1, regardless of whether format-0 or format-1 CCWs have been specified in the ORB.
[0542] 1. Exceto para efetuar devido à integração da CPU e equipamento de subsistema de canal, uma CPU está ocupada para a duração da execução do SUBCANAL DE PARTIDA, que dura até o subcanal de endereço ter passado os conteúdos de ORB. 2. O subcanal está ocupado para um novo SUBCANAL DE PARTIDA a partir do recebimento dos conteúdos de ORB até a condição de interrupção primária ser liberada no subcanal. 3. O dispositivo de I/O está ocupado a partir do início da primeira operação no dispositivo até tanto o subcanal se tornar suspenso ou a condição de interrupção secundária ser olocada no subcanal. No caso de um subcanal suspenso, o dispositivo novamente se torna ocupado quando a execução do programa de canal suspenso é resumida. [0542] In general, the execution of an I / O operation or chain of operations involves as much as three levels of participation: 1. Except to perform due to the integration of the CPU and channel subsystem equipment, a CPU is occupied for the duration of the START SUBChannel execution, which lasts until the address subchannel has passed the ORB contents. 2. The subchannel is busy for a new SUBCANAL DEPARTURE from the receipt of ORB contents until the primary interrupt condition is released at the subchannel. 3. The I / O device is busy from the beginning of the first operation on the device until either the subchannel becomes suspended or the secondary interrupt condition is placed on the subchannel. In the case of a suspended subchannel, the device again becomes busy when the execution of the suspended channel program is resumed.
[0543] [0543] Completion of I / O Operations
[0544] [0544] The completion of an I / O operation is usually indicated by the two status conditions: channel end and device end. The channel end condition indicates that the I / O device received or provided all data associated with the operation and no longer needs channel subsystem installations. This condition is called the primary interrupt condition, and the channel end in this case is the primary state. In general, the primary interrupt condition is any interrupt condition that refers to an I / O operation and that signals completion at the subchannel of the I / O operation or I / O Operations chain.
[0545] [0545] The device end signal indicates that the I / O device has finished executing and is ready to perform another operation. This condition is called the secondary interrupt condition, and the device endpoint in this case is the secondary state. In general, the secondary interrupt condition is any interrupt condition that refers to an I / O operation and that signals the completion of the I / O operation or chain of operations on the device. The secondary interruption condition can occur concurrently with, or after, the primary interruption condition.
[0546] [0546] Concurrent with the primary or secondary interruption conditions, both the channel subsystem and the I / O device can provide indications of unusual situations.
[0547] [0547] Conditions indicate that the completion of an I / O operation can be brought to the attention of the program by I / O interruptions or, when CPUs are disabled for I / O interruptions, by programmed interrogation of the subsystem of channel. In the previous case, these conditions cause the storage of the I / O interruption code, which contains information that refers to the interruption source. In the latter case, the interrupt code is stored as a result of executing PENDING TEST INTERRUPTION.
[0548] [0548] When the primary interrupt condition is recognized, the channel subsystem attempts to notify the program, by means of an interrupt request, that a subchannel contains information that describes the completion of an I / O operation at the subchannel. For command mode interruptions, the information identifies the last CCW used and can provide its residual byte count, thus describing the extent of the main storage used. For transport mode interruptions, the information identifies the current TCW and the TSB associated with the channel program which contains additional status on the I / O operation, such as residual byte count. In addition to the channel program information, both the channel subsystem and the I / O device can provide additional indications of unusual conditions as part of both the primary interrupt condition and the secondary interrupt condition. The information contained in the subchannel can be stored by executing the SUBCANAL TEST or executing the SUBCANAL STORAGE. This information, when stored, is called a subchannel status word (SCSW).
[0549] [0549] Chaining When using a CCW channel program
[0550] [0550] When the ORB specifies a CCW channel program, facilities are provided for the program to initiate the execution of a chain of I / O operations with a single Start Subchannel Instruction. When the current CCW specifies command chaining and no unusual conditions were detected during the operation, receiving the end of device signal causes the channel subsystem to search for a new CCW. If the CCW passes certain validity tests and the suspended marker is not specified as one in the new CCW, the execution of a new command is started on the device. If the CCW fails to pass the validity tests, the new command is not started, command chaining is suppressed, and the state associated with the new CCW causes an interrupt condition to be generated. If the drop-down marker is specified as one and this value is valid because of a value of one in the drop-down control, bit 4 of word 1 of the associated ORB, the execution of the new command is not started, and chain of command is completed.
[0551] [0551] Execution of the new command is initiated by the channel subsystem in the same way as in the previous operation. The end signals that occur at the completion of an operation caused by the CCW specifying command chain are not made available to the program. When another I / O operation is initiated by command chaining, the channel subsystem continues to execute the channel program. If, however, an unusual condition has been detected, command chaining is suppressed, the channel program is terminated, an interrupt condition is generated, and the end signals make the termination available to the program.
[0552] [0552] The suspend and resume function provides the program with control over the execution of a channel program. The start of the suspended function is controlled by setting the suspended control bit in the ORB. The suspend function is signaled to the channel subsystem during the execution of the channel program when the suspend control bit in the ORB is one and the suspended marker in the first CCW or in a CCW sought during the command chain is one.
[0553] [0553] Suspension occurs when the channel subsystem fetches the CCW with the suspended marker validity (because of a value of one of the suspension control bit in the ORB) specified as one. The command on this CCW is not sent to the I / O device, and the device is signaled that the chain of commands is complete. A subsequent SUMMARY SUBCANAL instruction informs the channel subsystem that the CCW that caused the suspension may have been modified and that the channel subsystem must fetch the CCW again and examine the current setting of the suspended marker. If the suspended marker is found to be zero in the CCW, the channel subsystem summarizes the execution of the chain of commands with the I / O device.
[0554] [0554] Chaining When using a TCW channel program
[0555] [0555] When the ORB specifies a TCW channel program, facilities are also provided for the program to initiate the execution of a chain of device operations with a single Start Subchannel Instruction. Command chaining can be specified for these DCWs designated by a single TCW. When the current DCW specifies command chaining and no unusual conditions were detected during the operation, recognition of the successful execution of the DCW causes the next DCW in the current TCCB to be processed.
[0556] [0556] If the next DCW passes certain validity tests, the execution of a new command is started on the device and the DCW becomes the current DCW. If the DCW fails to pass the validity tests, the new command is not started, the command chain is suppressed, the channel program is terminated, and the state associated with the new DCW causes an interrupt condition to be generated.
[0557] [0557] The execution of the new command starts in the same way as in the previous operation. Termination signals that occur at the completion of an operation caused by a DCW that is not the last specified DCW are not made available to the program. When another I / O operation is initiated by command chaining, the execution of the channel program continues. If, however, an unusual condition has been detected, command chaining is suppressed, the channel program is terminated, an interrupt condition is generated, and the state is made available to the program that identifies the non-real condition.
[0558] [0558] Premature Completion of I / O Operations
[0559] [0559] Channel program execution can be terminated prematurely by the CANCELLATION SUB-CHANNEL, SUSPENSION SUB-CHANNEL or EMPTY SUB-CHANNEL. The execution of the CANCELLATION SUBCANAL causes the channel subsystem to end the start function in the subchannel if the channel program has not been started on the device. When the start function is terminated by executing the CANCELLATION SUBChannel, the channel subsystem sets condition code 0 in response to the CANCELLATION SUBChannel instruction. The execution of SUSPENSION SUBCANAL causes the channel subsystem to send the suspend signal to the I / O device and finish the execution of the channel program in the subchannel. When the execution of the channel program is terminated by the execution of SUSPENSION SUB-CHANNEL, the program is notified of the termination by means of an I / O interruption request. When the subchannel is in command mode, the interrupt request is generated when the device is in status for the completed operation. When the subchannel is in transport mode, the interruption request is generated immediately. If, however, the stop signal was issued to the device during command chaining after receiving the end of device but before the next command is transferred to the device, the interrupt request is generated after the device has been signaled. In the latter case, the SCSW device status field will contain zeros. The execution of the EMPTY SUBChannel releases the subchannel of the indications of the channel program being executed, causes the channel subsystem to send the release signal to the I / O device, and cause the channel subsystem to generate an interrupt request. I / O to notify the program of the completion of the emptying function.
[0560] [0560] I / O interruptions
[0561] [0561] Conditions causing I / O interrupt requests are asynchronous for CPU activity, and more than one condition can occur at the same time. Conditions are preserved in the subchannels until released by the TEST SUBCANAL or EMPTY SUBCANAL, or restarted by a restart of the I / O system.
[0562] [0562] When an I / O interrupt condition has been recognized by the channel subsystem and indicated in the subchannel, an I / O interrupt request is made pending for the I / O Interrupt Subclass specified in the subchannel. The I / O Interrupt Subclass for which the interruption is pending is under programmed control through the use of the SUB-CHANNEL OF MODIFICATION. A pending I / O interrupt can be accepted by any CPU that is enabled for interrupts from its I / O Interrupt Subclass. Each CPU has eight mask bits, in control register 6, which controls the enabling of that CPU for each of the eight I / O Interrupt Subclasses, with the I / O mask, bit 6 on the PSW, being the mask main I / O interrupt to the CPU.
[0563] [0563] When an I / O interrupt occurs on a CPU, the I / O interrupt code is stored in the I / O communication area of the CPU, and the I / O interrupt request is released. The I / O interrupt code identifies the subchannel for which the interruption was pending. The conditions mean that the generation of the interruption request can then be retrieved from the subchannel explicitly by the SUBCANAL TEST or by the SUBCANAL STORAGE.
[0564] [0564] A pending I / O interruption request can also be released by the PENDING TEST INTERRUPTION when the corresponding I / O Interruption Subclass is enabled but PSW has I / O Interruptions disabled or by the TEST SUB-CHANNEL when the CPU is disabled for I / O interrupts from the corresponding I / O interruption subclass. a pending I / O interruption request can also be released by the EMPTY SUBCANAL. Both the SUBCANAL OF RELEASE and the SUBCANAL TEST also empty the condition of interruption preserved in the subchannel.
[0565] [0565] Normally, unless the interruption request is released by the SUBCANAL OF RELEASE, the program issues SUBCANAL TEST to obtain information regarding the execution of the operation.
[0566] [0566] SUB-CHANNEL EMPTYING
[0567] [0567] The designated subchannel is released, the start or stop function, if any, is terminated at the designated subchannel, and the channel subsystem is signaled to perform the emptying function on the designated subchannel and the associated device asynchronously. .
[0568] [0568] General register 1 contains a subsystem identification word (SID) that designates the subchannel to be released.
[0569] [0569] If a start or stop function is in progress, it is terminated at the subchannel.
[0570] [0570] The subchannel is no longer done in the pending state. All activity, as indicated in the SCSW activity control field, is released at the subchannel, except that the subchannel is made pending released. Any functions in progress, as indicated in the SCSW function control field, are released in the subchannel, except for the emptying function that must be performed because of the execution of this instruction.
[0571] [0571] When the subchannel is operating in transport mode and condition code 2 is set, the CPU can signal the channel subsystem to perform the interrogation function asynchronously, and end the instruction.
[0572] [0572] The channel subsystem is signaled to perform the emptying function asynchronously. The emptying function is summarized below in the "Associated Functions" section and is described in detail below.
[0573] [0573] Condition code 0 is defined to indicate that the actions described above have been taken.
[0574] [0574] Associated Functions
[0575] [0575] Subsequent to the execution of the EMPTY SUBCANAL, the channel subsystem performs the emptying function asynchronously. If conditions permit, the channel subsystem chooses a channel path and attempts to send the release signal to the device to terminate the I / O operation, if any. The subchannel then becomes a pending state. The conditions encountered by the channel subsystem that precede the emission of the release signal to the device do not prevent the subchannel from becoming a pending state.
[0576] [0576] When the subchannel becomes a pending state as a result of performing the emptying function, the data transfer, if any, with the associated device has been terminated. The SCSW stored when the resulting state is released by the TEST SUB-CHANNEL has the release function bit stored as one. If the channel subsystem can determine that the release signal has been sent to the device, the pending release bit is stored as zero in the SCSW. Otherwise, the pending release bit is stored as one, and other indications are provided that describe in more detail the condition that was found.
[0577] [0577] Measurement data is not accumulated, and device connection time is not stored in the extended status word for the subchannel, for a start function that is terminated by the EMPTY SUBCANAL.
[0578] [0578] Special Conditions
[0579] [0579] Condition code 3 is defined, and no further action is taken, when the subchannel is not operational for the EMPTY SUB-CHANNEL. A subchannel is not operational for the EMPTY SUBCANAL when the subchannel is not provided in the channel subsystem, has no valid device number assigned to it, or is not enabled.
[0580] [0580] THE EMPTY SUBCANAL can find the program exceptions described or listed below.
[0581] [0581] When the installation of multiple defined subchannels is not installed, bits 32-47 of general register 1 must contain 0001 hex; otherwise, an operand exception is recognized.
[0582] [0582] When the installation of multiple defined subchannels is installed, bits 32-44 of general register 1 must contain zeros, bits 45-46 must contain a valid value, and bit 47 must contain the value one; otherwise, an operand exception is recognized.
[0583] [0583] Resulting condition code:
[0584] [0584] 0 Function started
[0585] [0585] 1-
[0586] [0586] 2-
[0587] [0587] 3 Non-Operational
[0588] • Operando • Operação Privilegiada [0588] Program Exceptions: • Operating • Privileged Operation
[0589] [0589] Subsequent to the execution of the EMPTYING SUBCANAL, the channel subsystem performs the emptying function. Performance of the emptying function consists of (1) performing a path management operation, (2) modifying fields in the subchannel, (3) sending the release signal to the associated device, and (4) making the subchannel be done of the pending state, indicating the completion of the emptying function. Release Function Path Management
[0590] [0590] A path management operation is performed as part of the emptying function in order to examine the conditions of the channel path for the associated subchannel and to try to choose an available channel path in which the release signal can be output to the associated device.
[0591] 1. Se o subsistema de canal está se comunicando de maneira ativa ou tentando estabelecer comunicação ativa com o dispositivo a ser sinalizado, o caminho de canal que está em uso é escolhido. 2. Se o subsistema de canal está no processo de aceitação de uma indicação de não mais ocupado (que não vai fazer com que uma condição de interrupção seja reconhecida) a partir do dispositivo a ser sinalizado, e o subcanal associado não tem fidelidade com qualquer caminho de canal, o caminho de canal que está em uso é escolhido. 3. Se o subcanal associado possui uma fidelidade dedicada para um caminho de canal, aquele caminho de canal é escolhido. 4. Se o subcanal associado possui uma fidelidade de trabalho para um ou mais caminhos de canal, um daqueles caminhos de canal é escolhido. 5. Se o subcanal associado não tem fidelidade para qualquer caminho de canal, se um último caminho de canal usado é indicado, e se aquele caminho de canal está disponível para a seleção, aquele caminho de canal é escolhido. Se aquele caminho de canal não está disponível para a seleção, tanto nenhum caminho de canal é escolhido quanto um caminho de canal é escolhido a partir do conjunto de caminhos de canal, se existe algum, que estão disponíveis para a seleção (como pensado nenhum caminho de canal usado por último foi indicado). 6. Se o subcanal associado não tem fidelidade por qualquer caminho de canal, se nenhum caminho de canal usado por último é indicado, e se existe um ou mais caminhos de canal que estão disponíveis para a seleção, um daqueles caminhos de canal é escolhido. [0591] The channel path conditions are examined in the following order: 1. If the channel subsystem is actively communicating or trying to establish active communication with the device to be signaled, the channel path that is in use is chosen. 2. If the channel subsystem is in the process of accepting a no-busy indication (which will not cause an interrupt condition to be recognized) from the device to be signaled, and the associated subchannel has no fidelity to any channel path, the channel path that is in use is chosen. 3. If the associated subchannel has a dedicated fidelity for a channel path, that channel path is chosen. 4. If the associated subchannel has a working fidelity for one or more channel paths, one of those channel paths is chosen. 5. If the associated subchannel has no fidelity for any channel path, if a last used channel path is indicated, and if that channel path is available for selection, that channel path is chosen. If that channel path is not available for selection, either no channel path is chosen or a channel path is chosen from the set of channel paths, if any, that are available for selection (as no path is thought) channel used last was indicated). 6. If the associated subchannel has no fidelity to any channel path, if no channel path used last is indicated, and if there are one or more channel paths that are available for selection, one of those channel paths is chosen.
[0592] [0592] If none of the channel path conditions listed above apply, no channel path is chosen.
[0593] 1. Uma condição terminal de caminho de canal existe para o caminho de canal. 2. Para um caminho de canal de ESCON ou paralelo: Outro subcanal possui uma fidelidade ativa para o caminho de canal. [0593] For item 4, item 5 under the specified conditions, and item 6, the channel subsystem chooses a channel path from a set of channel paths. In these cases, the channel subsystem may try to choose a channel path, provided that the following conditions do not apply: 1. A channel path end condition exists for the channel path. 2. For an ESCON or parallel channel path: Another subchannel has active fidelity for the channel path.
[0594] [0594] For a FICON channel path: The channel path is currently being used to communicate actively with the maximum number of subchannels that can have concurrent active communications. 3. The device to be signaled is attached with a type 1 control unit, and the subchannel for another device attached with the same control unit has a fidelity with the same channel path, unless the fidelity is a fidelity of work and the primary state was accepted by that subchannel. 4. The device to be signaled is attached with a type 3 control unit, and the subchannel for another device attached with the same control unit has a dedicated fidelity with the same channel path. Release Function Subchannel Modification
[0595] 1. O estado de todos os oito possíveis caminhos de canal no subcanal é definido para operacional para o subcanal. 2. A indicação de último caminho usado é redefinida para indicar nenhum caminho de canal último caminho usado. 3. Condições de caminho não operacional, se existe alguma, são reiniciadas. [0595] Path management control indications in the subchannel are modified during the performance of the emptying function. In effect, this modification occurs after attempting to choose a channel path, but before attempting to select the device to emit the release signal. The path management control indications that are modified are as follows: 1. The status of all eight possible channel paths in the subchannel is set to operational for the subchannel. 2. The last used path indication is reset to indicate no last used path channel. 3. Non-operational path conditions, if any, are reset.
[0596] [0596] Release and Completion Function Signaling
[0597] [0597] Subsequent to the attempt to choose a channel path and the modification of the path management control fields, the channel subsystem, if conditions permit, attempts to select the device to emit the release signal. Conditions associated with the subchannel and the chosen channel path, if any, affect (1) whether an attempt is made to emit the release signal, and (2) whether the attempt to emit the release signal is successful. Regardless of these conditions, the subchannel is subsequently defined in the pending state, and the performance of the emptying function is complete. These conditions and their effect on the emptying function are described as follows:
[0598] 1. Nenhum caminho de canal foi escolhido. 2. O caminho de canal escolhido não está mais disponível para a seleção. 3. Uma condição terminal de caminho de canal existe para o caminho de canal escolhido. 4. Para os caminhos de canal de ESCON e paralelos: O caminho de canal escolhido atualmente está sendo usado para se comunicar de maneira ativa com um dispositivo diferente. Para os caminhos de canal de FICON: O caminho de canal escolhido atualmente está sendo usado para se comunicar de maneira ativa com o número máximo de dispositivos que podem ter comunicações ativas concorrentes. 5. O dispositivo a ser sinalizado é anexado com uma unidade de controle do tipo 1, e o subcanal para outro dispositivo anexado com a mesma unidade de controle tem uma fidelidade com o mesmo caminho de canal, a menos que a fidelidade seja uma fidelidade de trabalho e estado primário foi aceitado por aquele subcanal. 6. O dispositivo a ser sinalizado é anexado com uma unidade de controle do tipo 3, e o subcanal para outro dispositivo anexado com a mesma unidade de controle possui uma fidelidade dedicada para o mesmo caminho de canal. [0598] No attempt is made to output the release signal: The channel subsystem does not attempt to output the release signal to the device if any of the following conditions exist: 1. No channel path has been chosen. 2. The chosen channel path is no longer available for selection. 3. A channel path end condition exists for the chosen channel path. 4. For ESCON and parallel channel paths: The channel path currently chosen is being used to communicate actively with a different device. For FICON channel paths: The channel path currently chosen is being used to communicate actively with the maximum number of devices that can have concurrent active communications. 5. The device to be signaled is attached with a type 1 control unit, and the subchannel for another device attached with the same control unit has a fidelity with the same channel path, unless the fidelity is a fidelity of work and primary status was accepted by that subchannel. 6. The device to be signaled is attached with a type 3 control unit, and the subchannel for another device attached with the same control unit has a dedicated fidelity for the same channel path.
[0599] [0599] If any of the above conditions exist, the subchannel remains pending release and the pending state is defined, and the emptying function is complete.
[0600] 1. A unidade de controle ou dispositivo sinaliza uma condição ocupada quando o subsistema de canal tenta selecionar o dispositivo para emitir o sinal de liberação. 2. Uma condição de caminho não operacional é reconhecida quando o subsistema de canal tenta selecionar o dispositivo para emitir o sinal de liberação. 3. Uma condição de erro é encontrada quando o subsistema de canal tenta emitir o sinal de liberação. [0600] The attempt to send the release signal is unsuccessful: When the channel subsystem tries to send the release signal to the device, the attempt may be unsuccessful because of the following conditions: 1. The control unit or device signals a busy condition when the channel subsystem attempts to select the device to emit the release signal. 2. A non-operational path condition is recognized when the channel subsystem attempts to select the device to emit the release signal. 3. An error condition is encountered when the channel subsystem attempts to emit the release signal.
[0601] [0601] If any of the above conditions exist and the channel subsystem both determines that the attempt to send the release signal was unsuccessful or cannot determine whether the attempt was successful, the subchannel remains pending release and a pending state is defined, and the performance of the emptying function is complete.
[0602] [0602] The attempt to send the release signal is successful: When the channel subsystem determines that the attempt to send the release signal was successful, the subchannel is no longer pending release and the pending state is defined, and performance of the emptying function is complete. When the subchannel becomes a pending state, the I / O operation, if any, with the associated device has been terminated.
[0603] [0603] Programming Note: Subsequent to the emptying function performance, any state other than zero, except the end of the control unit alone, which is presented to the channel subsystem by the device is passed to the program as a non-alert state. requested. Unsolicited state consisting of end of the control unit alone or zero state is not presented to the program. SUB-CHANNEL OF MODIFICATION
[0604] [0604] The information contained in the subchannel information block (SCHIB) is placed in the program changeable fields in the subchannel. As a result, the program influences, for that subchannel, certain aspects of I / O processing for the release, stop, summary, and start functions and certain I / O support functions.
[0605] [0605] Registrar General 1 contains a subsystem identification word (SID) that designates the subchannel that must be modified as specified by certain fields in the SCHIB. The address of the second operand is the logical address of the SCHIB and must be designated in a word boundary; otherwise, a specification exception is recognized.
[0606] • Processamento de I/O (campo E) • Processamento de interrupção (parâmetro de Interrupção e campo de ISC) • Gerenciamento de caminho (campos D, LPM, e POM) • Monitoramento e verificação de limite de endereço (índice de bloco de medição, campos LM, e MM) • Controle de formato de bloco de medição (campo F) • Modo de palavra de medição estendida habilitado (campo X) • Instalação de detecção concorrente (campo S) • Endereço de bloco de medição (MBA) [0606] The channel subsystem operations that can be influenced due to the positioning of the information in the SCHIB subchannel are: • I / O processing (field E) • Interrupt processing (Interrupt parameter and ISC field) • Path management (D, LPM, and POM fields) • Monitoring and verification of address limit (measurement block index, LM, and MM fields) • Measurement block format control (field F) • Extended measurement word mode enabled (field X) • Concurrent detection facility (field S) • Measurement block address (MBA)
[0607] [0607] Bits 0, 1, 6, and 7 of word 1, and bits 0-28 of word 6 of the SCHIB operand must be zeroes, and bits 9 and 10 of word 1 must not both be one. When the extended I / O measurement block installation is installed and a format-1 measurement block is specified, bits 2631 of word 11 must be specified as zeros. When the extended I / O measurement block installation is not installed, bit 29 of word 6 must be specified as zero; otherwise, an operand exception is recognized. When the extended I / O measurement word installation is not installed, or is installed but not allowed, bit 30 of word 6 must be specified as zero; otherwise, an operand exception is recognized. The remaining fields of the SCHIB are ignored and do not affect the processing of the SUB-CHANNEL OF MODIFICATION.
[0608] [0608] Condition code 0 is defined to indicate that the information from the SCHIB has been positioned in the program changeable fields in the subchannel, except that when the valid device number (V) bit in the designated subchannel is zero, then code of condition 0 is defined, and the information from the SCHIB is not positioned in the modifiable program fields.
[0609] [0609] Special Conditions
[0610] [0610] Condition code 1 is defined, and no further action is taken when the subchannel is in a pending state.
[0611] [0611] Condition code 2 is defined, and no further action is taken, when a release, stop or start function is in progress on the subchannel.
[0612] [0612] Condition code 3 is defined, and no further action is taken, when the subchannel is not operational for SUB-CHANNEL OF MODIFICATION. A subchannel is not operational for the SUB-CHANNEL OF MODIFICATION when the subchannel is not provided in the channel subsystem.
[0613] [0613] SUB-CHANNEL OF MODIFICATION can find the program exceptions described or listed below.
[0614] [0614] In word 1 of the SCHIB, bits 0, 1, 6, and 7 must be zeroes and, when the address limit check facility is installed, bits 9 and 10 must not be one. In word 6 of the SCHIB, bits 0-28 must be zeroes. Otherwise an operand exception is recognized.
[0615] [0615] When the extended I / O measurement block installation is installed and a format-1 measurement block is specified, bits 26-31 of word 11 must be specified as zeros; otherwise, an operand exception is recognized. When the extended I / O measurement block installation is not installed, bit 29 of word 6 must be specified as zero; otherwise, an operand exception is recognized. When the extended I / O measurement word installation is not installed, or is installed but not allowed, bit 30 of word 6 must be specified as zero; otherwise, an operand exception is recognized.
[0616] [0616] When the installation of multiple defined subchannels is not installed, bits 32-47 of general register 1 must contain 0001 hex; otherwise, an operand exception is recognized.
[0617] [0617] When the installation of multiple defined subchannels is installed, bits 32-44 of general register 1 must contain zeros, bits 45-46 must contain a valid value, and bit 47 must contain the value one; otherwise, an operand exception is recognized.
[0618] [0618] The second operand must be designated in a word limit; otherwise, a specification exception is recognized. The execution of the SUB-CHANNEL OF MODIFICATION is suppressed in all addressing and protection exceptions.
[0619] [0619] Resulting condition code:
[0620] [0620] 0 Function completed
[0621] [0621] 1 status pending
[0622] [0622] 2 Busy
[0623] [0623] 3 Not operational
[0624] • Acesso (busca, operando 2) • Operando • Operação privilegiada • Especificação [0624] Program exceptions: • Access (search, operating 2) • Operating • Privileged operation • Specification
[0625] 1. Se um dispositivo sinaliza alerta de erro de I/O enquanto o subcanal associado é desabilitado, o subsistema de canal emite o sinal de liberação para o dispositivo e descarta a indicação de alerta de erro de I/O sem gerar uma condição de interrupção de I/O. 2. Se um dispositivo apresenta estado não solicitado enquanto o subcanal associado é desabilitado, aquele estado é descartado pelo subsistema de canal sem gerar uma condição de interrupção de I/O. No entanto, se o estado apresentado contém verificação de unidade, o subsistema de canal emite o sinal de liberação para o subcanal associado e não gera uma condição de interrupção de I/O. Isto deve ser levado em conta quando o programa usa SUBCANAL DE MODIFICAÇÃO para habilitar um subcanal. Por exemplo, o meio no dispositivo associado que estava presente quando o subcanal se torna desabilitado pode ter sido substituído e, portanto, o programa deve verificar a integridade daquele meio. 3. É recomendado que o programa inspecione os conteúdos do subcanal emitindo subsequentemente o SUBCANAL DE ARMAZENAMENTO quando o SUBCANAL DE MODIFICAÇÃO define o código de condição 0. Use do Subcanal DE ARMAZENAMENTO é um método para determinar se o subcanal designado foi alterado ou não. Falha em inspecionar o subcanal seguindo o ajuste do código de condição 0 pelo SUBCANAL DE MODIFICAÇÃO pode resultar nas condições que o programa não espera ocorrer. [0625] Programming Notes: 1. If a device signals an I / O error alert while the associated subchannel is disabled, the channel subsystem issues the release signal to the device and discards the I / O error alert indication without generating an interrupt condition of I / O. 2. If a device has an unsolicited state while the associated subchannel is disabled, that state is discarded by the channel subsystem without generating an I / O interrupt condition. However, if the displayed state contains unit verification, the channel subsystem sends the release signal to the associated subchannel and does not generate an I / O interrupt condition. This must be taken into account when the program uses SUB-CHANNEL OF MODIFICATION to enable a sub-channel. For example, the medium on the associated device that was present when the subchannel becomes disabled may have been replaced and, therefore, the program must verify the integrity of that medium. 3. It is recommended that the program inspect the contents of the subchannel by subsequently issuing the SUB-CHANNEL OF STORAGE when the SUB-CHANNEL OF MODIFICATION defines condition code 0. Use of the STORAGE SUB-CHANNEL is a method for determining whether the designated sub-channel has been changed or not. Failure to inspect the subchannel following the setting of condition code 0 by the SUB-CHANNEL OF MODIFICATION can result in conditions that the program does not expect to occur.
[0626] [0626] SUBCANAL DEPARTURE
[0627] [0627] The channel subsystem is signaled to perform the start function for the associated device asynchronously, and the execution parameters that are contained in the designated ORB are positioned in the designated subchannel.
[0628] [0628] The General Register 1 contains the subsystem identification word that designates the subchannel to be started. The address of the second operand is the logical address of the ORB and must be designated in a word boundary; otherwise, a specification exception is recognized.
[0629] [0629] The execution parameters contained in the ORB are positioned in the subchannel.
[0630] [0630] When the SUBChannel START is executed, the subchannel is pending state with only secondary state, and the format extended status word bit (L) is zero, the pending state condition is discarded in the subchannel.
[0631] [0631] The subchannel is made pending start, and the start function is indicated on the subchannel. If the second operand designates a command mode ORB, the subchannel remains in command mode. If the second operand designates a transport mode ORB, the subchannel enters the transport mode. When the subchannel enters the transport mode, the LPUM is set to zero if no previous dedicated loyalty exists; otherwise the LPUM is not changed.
[0632] [0632] Logically before setting the condition code 0, non-operational path conditions in the subchannel, if any, are released.
[0633] [0633] The channel subsystem is signaled to perform the start function asynchronously. The start function is summarized below in the "Associated functions" section and is described in detail below.
[0634] [0634] Condition code 0 is defined to indicate that the actions described above have been taken.
[0635] [0635] Associated functions
[0636] [0636] Subsequent to the execution of the SUBCANAL DEPARTURE, the channel subsystem performs the start function asynchronously.
[0637] [0637] The contents of the ORB, other than the fields that must contain all zeros, are checked for validity. In some models, ORB fields that must contain zeros are checked asynchronously, instead during the execution of the instruction. When invalid fields are detected asynchronously, the subchannel becomes pending state with primary, secondary state, and alert state and with deferred condition code 1 and indicated program verification.
[0638] [0638] In this situation, the I / O operation or I / O Operations chain is not initiated on the device, and the condition is indicated by the pending start bit being stored as one when the SCSW is released by executing SUBCANAL DE TEST.
[0639] [0639] In some models, path availability is tested asynchronously, instead during instruction execution. When in the channel path it is available for selection, the subchannel becomes pending state with primary and secondary status and with deferred condition code 3 indicated. The I / O operation or chain of I / O operations is not initiated on the device, and this condition is indicated by the pending start bit being stored as one when the SCSW is released by executing the SUBCANAL TEST.
[0640] [0640] If conditions permit, a channel path is chosen, and the execution of the channel program that is designated in the ORB is started.
[0641] [0641] Special conditions
[0642] [0642] Condition code 1 is defined, and no further action is taken when the subchannel is in a pending state when the SUBCANAL DEPARTURE is executed. In some models, condition code 1 is not defined when the subchannel is in a pending state with only a secondary state; instead, the pending state condition is discarded.
[0643] [0643] Condition code 2 is defined, and no further action is taken, when a start, stop or release function is currently in progress at the subchannel.
[0644] [0644] Condition code 3 is defined, and no further action is taken, when the subchannel is not operational for SUBCANAL DEPARTURE. A subchannel is not operational for SUBCANAL DEPARTURE if the subchannel is not provided in the channel subsystem, has no valid device number associated with it, or is not allowed.
[0645] [0645] A subchannel is also not operational for the SUBCANAL DEPARTURE, on some models, when no channel path is available for selection. In these models, the lack of an available channel path is detected as part of the SUBCANAL DEPARTURE execution. In other models, channel path availability is only tested as part of the asynchronous start function.
[0646] [0646] SUBCANAL DEPARTURE You can find the program exceptions described or listed below.
[0647] [0647] In word 1 of the command mode ORB, bits 26-30 must be zeroes, and, in word 2 of the command mode ORB, bit 0 must be zero. Otherwise, on some models, an operand exception is recognized. In other models, an I / O interrupt condition is generated, indicating the program check, as part of the asynchronous start function.
[0648] [0648] SUBCANAL DEPARTURE You can also find the program exceptions listed below.
[0649] [0649] When the installation of multiple defined subchannels is not installed, bits 32-47 of general register 1 must contain 0001 hex; otherwise, an operand exception is recognized.
[0650] [0650] When the installation of multiple defined subchannels is installed, bits 32-44 of general register 1 must contain zeros, bits 45-46 must contain a valid value, and bit 47 must contain the value one; otherwise, an operand exception is recognized.
[0651] [0651] The second operand must be designated in a word limit; otherwise, a specification exception is recognized. The execution of the DEPARTURE SUBCANAL is suppressed in all addressing and protection exceptions.
[0652] [0652] Resulting condition code:
[0653] [0653] 0 Function started
[0654] [0654] 1 status pending
[0655] [0655] 2 Busy
[0656] [0656] 3 Not operational
[0657] • Acesso (busca, operando 2) • Operando • Operação privilegiada • Especificação [0657] Program exceptions: • Access (search, operating 2) • Operating • Privileged operation • Specification
[0658] [0658] Start function and summary function
[0659] [0659] The start and summary functions start I / O Operations as described below. The start function applies to subchannels that operate in both command mode and transport mode. The summary function applies only to subchannels operating in command mode.
[0660] [0660] Subsequent to the execution of the SUBCANAL DE START and SUBCANAL SUMMARY, the channel subsystem performs the start and summary functions, respectively, to initiate an I / O operation with the associated device. Performance of a start function or summary function consists of: (1) performing a path management operation, (2) performing an I / O operation or I / O Operations chain with the associated device, and (3 ) causing the subchannel to be made in a pending state, indicating the completion of the start function. The start function starts the execution of a channel program that is designated in the ORB, which in turn is designated as the SUBCANAL DEPARTURE operand, in contrast to the summary function that starts the execution of a suspended channel program, if any, starting at the CCW that caused the suspension; otherwise, the summary function is performed as if it were a start function.
[0661] [0661] Summary Function and Start Function Path Management
[0662] a. Se o dispositivo é especificado para estar operando no modo de múltiplos caminhos e a indicação de ocupado recebida é de dispositivo ocupado, então a função de partida ou de resumo permanece pendente até a indicação interna de ocupado ser reiniciada. b. Se o dispositivo é especificado para estar operando no modo de múltiplos caminhos e a indicação de ocupado recebida é a unidade de controle ocupada, ou se o dispositivo é especificado para estar operando no modo de caminho único , o subsistema de canal tenta a seleção do dispositivo escolhendo um caminho de canal alternado que está disponível para a seleção e continua a operação de gerenciamento de caminho até tanto a função de partida quanto a função de resumo é iniciada ou seleção do dispositivo ter sido tentada em todos os caminhos de canal que estão disponíveis para a seleção. Se a função de partida ou de resumo não foi iniciada pelo subsistema de canal após todos os caminhos de canal disponíveis para a seleção foram escolhidos, a função de partida ou de resumo permanece pendente até a indicação interna de ocupado ser reiniciada. c. Se o subcanal possui uma fidelidade dedicada, então a ação 2 na página 15-20 se aplica. 9. Quando, durante a tentativa de seleção para transferir o primeiro comando para um programa de canal de CCW, ou para transportar o TCCB para um programa de canal de TCW, o dispositivo parece não operacional e o correspondente caminho de canal é operacional para o subcanal, uma condição de caminho não operacional é reconhecida, e o estado do caminho de canal muda no subcanal de operacional para o subcanal para não operacional para o subcanal. As condições de caminho não operacional no subcanal, se existe alguma, são preservadas até o subcanal próximo se tornar de liberação pendente partida pendente, ou resumo pendente (se o subcanal foi suspenso), momento em que as condições de caminho não operacional são liberadas. Se, no entanto, o correspondente caminho de canal não é operacional para o subcanal, uma condição de caminho não operacional não é reconhecido. Quando o dispositivo parece não operacional durante a tentativa de seleção para transferir o primeiro comando ou TCCB em um caminho de canal que está disponível para a seleção, uma das seguintes ações ocorre: a. Se uma fidelidade dedicada existe para aquele caminho de canal, então é apenas o caminho de canal que está disponível para a seleção; portanto, adicionalmente tenta iniciar a função de partida ou de resumo são abandonados, e uma condição de interrupção é reconhecida. b. Se no fidelidade dedicada existe e existem caminhos de canal alternados disponíveis para a seleção que não foram tentados, um destes caminhos de canal é escolhido para tentar a seleção do dispositivo e a transferência do primeiro comando para um programa de canal de CCW, ou o TCCB para um programa de canal de TCW. c. Se nenhuma fidelidade dedicada existe, nenhum caminho de canal alternado está disponível para a seleção que não foi tentado, e o dispositivo parece operacional em pelo menos um do caminhos de canal que foram tentados, a função de partida ou de resumo permanece pendente no subcanal até um caminho de canal, uma unidade de controle, ou o dispositivo, como for apropriado, se tornar disponível. d. Se no fidelidade dedicada existe, nenhum caminho de canal alternado está disponível para a seleção que não foi tentada, e o dispositivo parece não operacional em todos os caminhos de canal que foram tentados, adicionalmente tenta iniciar a função de partida ou de resumo são abandonados, e uma condição de interrupção é reconhecida. 10. Quando o subcanal está ativo e uma operação de I/O deve ser iniciada com um dispositivo, todas as seleções de dispositivo ocorrem de acordo com a indicação de LPUM se o modo de múltiplos caminhos não está especificado no subcanal. Por exemplo, se encadeamento de comando é especificado para um programa de canal de CCW, o subsistema de canal transfere o primeiro comando e todos os subsequentes comandos que descrevem uma cadeia de Operações de I/O sobre o mesmo caminho de canal.[0662] A path management operation is performed by the channel subsystem during the performance of both the start function and the summary function to choose an available channel path that can be used for selecting the device to initiate an I operation. / O with that device. The actions taken are as follows: 1. If the subchannel is currently pending start and the device is active, the start function remains pending on the subchannel until the secondary state for the previous start function has been accepted from the associated device and the subchannel is pending start alone. When the state is accepted and does not describe an alert interrupt condition, the subchannel is not made in a pending state, and the performance of the pending start function is subsequently started. If the state describes an alert interrupt condition, the subchannel becomes a pending state with a secondary state and an alert state, the pending start function is not started, deferred condition code 1 is set, and the pending start bit remains a. If the subchannel is currently pending start alone, the performance of the start function is initiated as described below. 2. If a dedicated loyalty exists in the subchannel for a channel path, the channel subsystem chooses that path for device selection. If a busy condition is encountered while trying to select the device and a dedicated fidelity exists in the subchannel, the start function remains pending until the internal busy indication is reset for that channel path. When the internal busy indication is reset, the performance of the pending start function is initiated on that channel path. 3. If the channel path is available for selection and no dedicated fidelity exists in the subchannel for a channel path, a channel path is not chosen. 4. If all channel paths that are available for selection have been tried and one or more of them are being used to actively communicate with other devices, or alternatively, if the channel subsystem encounters both a busy unit of control or a device busy condition on one or more of these channel paths, or a combination of these conditions on one or more of these channel paths, the start function remains pending on the subchannel to a channel path, control unit, or device , as appropriate, becomes available. 5. If (1) the start function is to be started on a channel path with a device attached with a type 1 control unit and (2) no other device is attached with the same control unit that the subchannel has so much a dedicated fidelity for the same channel path or a working fidelity for the same channel path where the primary state has not been received for that subchannel, so that channel path is chosen if it is available for selection; otherwise, that channel path is not chosen. If, however, another channel path for the device is available for selection and no fidelity exists as described above, that channel path is chosen. If no other channel path is available for selection, the start or summary function, as appropriate, remains pending until a channel path becomes available. 6. If the device is attached with a type 3 control unit, and if at least one other device is attached with the same control unit where the subchannel has a dedicated fidelity for the same channel path, another channel path that is available for selection can be chosen, or the start function remains pending until the dedicated fidelity for the other device is released. 7. If a channel path has been chosen and a busy indication is received during device selection to start executing the first command of a pending CCW channel program or to transport the TCCB from a pending TCW channel program, the channel path over which the busy indication is received is not used again for that device or the control unit (depending on the busy device indication or busy control unit received) until the internal busy indication is reset. 8. If, during an attempt to select the device so as to initiate the execution of the first command specified for starting or implied for the summary function for a CCW channel program, or to initiate the transport of the TCCB for the function of starting for a TCW channel program, (as described in action 7 above), the channel subsystem receives a busy indication, performs one of the following actions: The. If the device is specified to be operating in multipath mode and the busy indication received is device busy, then the start or summary function remains pending until the internal busy indication is reset. B. If the device is specified to be operating in multipath mode and the busy indication received is the control unit occupied, or if the device is specified to be operating in single path mode, the channel subsystem attempts the device selection choosing an alternate channel path that is available for selection and continues the path management operation until either the start function or the summary function is initiated or device selection has been attempted on all channel paths that are available for the selection. If the start or summary function has not been started by the channel subsystem after all channel paths available for selection have been chosen, the start or summary function remains pending until the internal busy indication is restarted. ç. If the subchannel has dedicated fidelity, then action 2 on page 15-20 applies. 9. When, during the selection attempt to transfer the first command to a CCW channel program, or to transport the TCCB to a TCW channel program, the device appears non-operational and the corresponding channel path is operational for the subchannel, a non-operational path condition is recognized, and the state of the channel path changes in the subchannel from operational to the subchannel to non-operational for the subchannel. Non-operational path conditions at the subchannel, if any, are preserved until the next subchannel becomes pending release pending start, or pending summary (if the subchannel has been suspended), at which point the non-operational path conditions are released. If, however, the corresponding channel path is not operational for the subchannel, a non-operational path condition is not recognized. When the device appears non-operational during the selection attempt to transfer the first command or TCCB to a channel path that is available for selection, one of the following actions occurs: The. If a dedicated loyalty exists for that channel path, then it is only the channel path that is available for selection; therefore, additionally attempts to start the start or summary function are abandoned, and an interrupt condition is recognized. B. If dedicated fidelity exists and there are alternate channel paths available for selection that have not been attempted, one of these channel paths is chosen to attempt device selection and transfer the first command to a CCW channel program, or the TCCB for a TCW channel program. ç. If no dedicated fidelity exists, no alternate channel path is available for the selection that was not attempted, and the device appears operational on at least one of the channel paths that were attempted, the start or summary function remains pending on the subchannel until a channel path, a control unit, or the device, as appropriate, becomes available. d. If no dedicated fidelity exists, no alternate channel path is available for the selection that was not attempted, and the device appears to be non-operational on all the channel paths that were attempted, additionally attempts to start the start or summary function are abandoned, and an interrupt condition is recognized. 10. When the subchannel is active and an I / O operation must be initiated with a device, all device selections occur according to the LPUM indication if multipath mode is not specified in the subchannel. For example, if command chaining is specified for a CCW channel program, the channel subsystem transfers the first command and all subsequent commands that describe a chain of I / O Operations over the same channel path.
[0663] [0663] Execution of I / O Operations
[0664] [0664] After a channel path is chosen, the channel subsystem, if conditions permit, starts the execution of an I / O operation with the associated device. The execution of additional I / O Operations can follow the start and execution of the first I / O operation.
[0665] [0665] For subchannels operating in command mode, the channel subsystem can execute seven types of commands: write, read, read back, control, detection, detection ID, and transfer in the channel. Each command, except the transfer on the channel, initiates a corresponding I / O operation. Except for periods when channel program execution is suspended at the subchannel, the subchannel is active from the acceptance of the first command until the primary interrupt condition is recognized at the subchannel. If the primary interrupt condition is recognized before the first command is accepted, the subchannel does not become active. Usually, the primary interrupt condition is caused by the end of channel signal or, in the case of command chaining, the end of channel signal for the last CCW in the chain. The device is active until the secondary interrupt condition is recognized in the subchannel. Typically, the secondary interrupt condition is caused by the device end signal or, in the case of command chaining, the device end signal for the last CCW in the chain.
[0666] [0666] For subchannels operating in transport mode, the channel subsystem can carry six types of commands for execution: writing, reading, control, detection, detection ID, and interrogation. Each command initiates a corresponding operation of the device. When one or more commands are carried to the I / O device in a TCCB, the subchannel remains pending starting until the primary state is displayed.
[0667] [0667] Programming Notes:
[0668] [0668] In single path mode, all command, data, and status transfers for the I / O operation or I / O Operations chain occur on the channel path over which the first command was transferred to the device .
[0669] a. Um tipo de comando de modo de múltiplos caminhos de conjunto deve ser executado com sucesso pelo dispositivo em cada caminho de canal que deve ser um membro do grupo de múltiplos caminhos que é definido; de outra forma, o modo de múltiplos caminhos de operação pode fornecer resultados imprevisíveis no subcanal. [0669] When the device has dynamic reconnection functionality installed, an I / O operation or chain of I / O operations can be performed in multipath mode. To operate in multipath mode, SUB-CHANNEL OF MODIFICATION must be performed previously for the sub-channel with bit 13 of word 1 of the SCHIB specified as one. In addition, the device must be set to multipath mode by executing certain model-dependent commands appropriate for that type of device. The general procedures for handling multipath mode operations are as follows: 1. Configuration The. A set multipath mode command type must be successfully executed by the device on each channel path which must be a member of the multipath group that is defined; otherwise, the multipath mode of operation can provide unpredictable results at the subchannel.
[0670] [0670] If, for any reason, one or more channel paths physically available to the device are not included in the multipath group, these channel paths should not be available for selection while the subchannel is operating in multiple paths. A channel path can be made unavailable for selection by having the corresponding LPM bit set to zero both in the SCHIB prior to the execution of the MODIFICATION SUBChannel and in the ORB prior to the execution of the STARTING SUBCANAL.
[0671] [0671] b. When a type of set multipath command is transferred to a device, only a single channel path must be available in a logical manner in order to avoid selecting alternate channel path for the execution of that start function; otherwise, busy device conditions can be detected by the channel subsystem in more than one channel path, which can cause unpredictable results for subsequent multipath mode operations. This type of configuration procedure should be used whenever the member of a multipath group is changed.
[0672] [0672] 2. Leaving multipath mode
[0673] a. Um tipo de comando de modo de múltiplos caminhos de dissolução pode ser executado para qualquer caminho de canal do grupo de múltiplos caminhos. Este comando deve ser seguido tanto por (1) a execução do SUBCANAL DE MODIFICAÇÃO com bit 13 da palavra 1 do SCHIB especificado como zero, quanto por (2) a especificação de apenas um único caminho de canal como disponível de maneira lógica no LPM. Uma função de partida não deve ser realizada em um subcanal que opera no modo de múltiplos caminhos com múltiplos caminhos de canal disponíveis para a seleção enquanto o dispositivo está operando no modo de caminho único; de outra forma, resultados imprevisíveis podem ocorrer no subcanal para aquela função ou subsequentes funções de partida. b. Um tipo de comando de modo de múltiplos caminhos de renuncia é executado em cada caminho de canal do grupo de múltiplos caminhos (o inverso da configuração). Este comando deve ser seguido tanto por (1) a execução do SUBCANAL DE MODIFICAÇÃO com bit 13 da palavra 1 do SCHIB especificado como zero, quanto por (2) a especificação de apenas um único caminho de canal como disponível de maneira lógica no LPM. No função de partida pode ser realizada em um subcanal que opera no modo de múltiplos caminhos com múltiplos caminhos de canal disponíveis para a seleção enquanto o dispositivo está operando no modo de caminho único; de outra forma, resultados imprevisíveis podem ocorrer no subcanal para aquela ou subsequentes funções de partida. [0673] To leave multipath mode and continue processing in single path mode, both of the following two procedures can be used: The. A type of multipath dissolve mode command can be executed for any channel path in the multipath group. This command must be followed both by (1) the execution of the SUB-CHANGE CHANGE with bit 13 of word 1 of the SCHIB specified as zero, and by (2) the specification of only a single channel path as available logically in the LPM. A start function must not be performed on a subchannel that operates in multipath mode with multiple channel paths available for selection while the device is operating in single path mode; otherwise, unpredictable results can occur at the subchannel for that function or subsequent start functions. B. A type of multipath mode command waives is executed on each channel path of the multipath group (the reverse of the configuration). This command must be followed both by (1) the execution of the SUB-CHANGE CHANGE with bit 13 of word 1 of the SCHIB specified as zero, and by (2) the specification of only a single channel path as available logically in the LPM. The start function can be performed on a subchannel that operates in multipath mode with multiple channel paths available for selection while the device is operating in single path mode; otherwise, unpredictable results can occur at the subchannel for that or subsequent start functions.
[0674] [0674] Blocking of data
[0675] [0675] Data recorded by an I / O device is divided into blocks. The length of a block depends on the device; for example, a pad can be a card, a printing line, or the information recorded between two consecutive gaps in the magnetic tape.
[0676] [0676] The maximum amount of information that can be transferred in an I / O operation is a block. An I / O operation is terminated when the associated main storage area is exhausted or the end of the block is reached, whenever it occurs first. For some operations, such as writing to a magnetic tape drive or an inquiry station, blocks are not defined, and the amount of information transferred is controlled only by the program.
[0677] [0677] Operation order block
[0678] [0678] The operation request block (ORB) is the operand of the SUBCANAL DEPARTURE. The ORB specifies the parameters to be used to control that particular start function. These parameters include the Interrupt parameter, the Subchannel Key, the address of the first CCW or TCW, operation control bits, priority control numbers, and a specification of the logical availability of the channel paths for the designated device.
[0679] [0679] ORB contents are positioned on the designated subchannel during the execution of the SUBCANAL DEPARTURE, before setting the condition code 0. If the execution will result in a non-zero condition code, the ORB contents are not positioned on the designated subchannel.
[0680] [0680] The rightmost bits of the ORB address must be zeroes, placing the ORB on a word boundary; otherwise, a specification exception is recognized. When the installation of fiber channel extensions (FCX) is installed, the channel program type control (B) (word 1, bit 13) of the ORB specifies the type of channel program that is designated by the ORB. When B is zero, the ORB designates a CCW channel program. When B is one, the ORB designates a TCW channel program. Only I / O devices that support FCX recognize TCW channel programs.
[0681] [0681] If the contents of an ORB that designates a CCW channel program are positioned in the designated subchannel during the execution of the STARTING SUBChannel, the subchannel remains in command mode. Thus, such an ORB is also known as a command mode ORB. If the contents of an ORB that designates a TCW channel program are positioned on the designated subchannel during the execution of the STARTING SUBChannel, the subchannel enters the transport mode. Thus, such an ORB is also known as a transport mode ORB.
[0682] [0682] PENDING TEST INTERRUPTION
[0683] [0683] The I / O interrupt code for a pending I / O interruption in a subchannel is stored at the location designated by the address of the second operand, and the pending I / O interrupt request is released.
[0684] [0684] The address of the second operand, when different from zero, is the logical address of the location where the two-word I / O interrupt code, consisting of words 0 and 1, must be stored. The address of the second operand must be designated on a word boundary; otherwise, a specification exception is recognized.
[0685] [0685] If the address of the second operand is zero, the three-word I / O interrupt code, consisting of the words 0-2, is stored in real locations 184195. In this case, low address protection and controlled key protection do not apply.
[0686] [0686] In access register mode when the address of the second operand is zero, it is unpredictable if access register translation occurs for access register B2. If translation occurs, the resulting address space control element is not used; that is, the interrupt code is still stored in real locations 184-195.
[0687] [0687] Pending I / O interrupt requests are accepted only for those I / O interrupt subclasses allowed by the I / O interrupt subclass mask in the control register 6 of the CPU that executes the instruction. If no I / O interrupt request exists that is left by control register 6, the I / O interrupt code is not stored, the location of the second operand is not modified, and condition code 0 is set.
[0688] [0688] If a pending I / O interrupt request is accepted, the I / O interrupt code is stored, the pending I / O interrupt request is released, and condition code 1 is defined. The I / O interrupt code that is stored is the same that can be stored if an I / O interrupt occurs. However, PSWs are not exchanged as when an I / O interruption occurs, the execution of the instruction is defined as follows:
[0689] [0689] Subsystem identification word (SID):
[0690] [0690] Bits 32-63 of the SID are positioned in the word 0.
[0691] [0691] Interrupt Parameter: Word 1 contains a four-byte parameter that was specified by the program and passed to the subchannel in word 0 of the ORB or PMCW. When a device displays the alert state and the Interrupt parameter has not been previously passed to the subchannel by a SUBCANAL DEPARTURE or SUBCANAL CHANGE run, this field contains zeros.
[0692] [0692] Interrupt identification word: Word 2, when stored, contains the interruption identification word, which additionally identifies the source of the I / O interruption. Word 2 is stored only when the address of the second operand is zero.
[0693] [0693] The interruption identification word is defined as follows:
[0694] [0694] One bit (A): Bit 0 of the interrupt identification word specifies the type of pending I / O interrupt request that has been released. When bit 0 is zero, the I / O interrupt request is associated with a subchannel.
[0695] [0695] I / O Interrupt Subclass (ISC): bit positions 2-4 of the interrupt identification word contain an unassigned binary integer, in the range 0 to 7, that specifies the I / O Interrupt Subclass associated with the subchannel for which the pending I / O interrupt request was released. The remaining bit positions are reserved and stored as zeroes.
[0696] [0696] Special conditions
[0697] [0697] PENDING TEST INTERRUPTION You can find the program exceptions described or listed below.
[0698] [0698] The second operand must be designated in a word limit; otherwise, a specification exception is recognized.
[0699] [0699] The execution of the PENDING TEST INTERRUPTION is suppressed in all addressing and protection exceptions.
[0700] [0700] Resulting condition code:
[0701] [0701] 0 Interrupt code not stored
[0702] [0702] 1 Interruption code stored
[0703] [0703] 2-
[0704] [0704] 3-
[0705] • Acesso (armazenamento, operando 2, endereço de segundo operando diferente de zero apenas) • Operação privilegiada • Especificação [0705] Program exceptions: • Access (storage, operand 2, second address operand nonzero only) • Privileged operation • Specification
[0706] 1. INTERRUPÇÃO PENDENTE DE TESTE deve ser executada apenas com um endereço de segundo operando de zero quando Interrupções de I/O são mascaradas. De outra forma, um código de interrupção de I/O armazenado pela instrução pode ser perdido se uma interrupção de I/O ocorre. O código de interrupção de I/O que identifica a fonte de uma interrupção de I/O tomada subsequente à INTERRUPÇÃO PENDENTE DE TESTE também é armazenada em localizações reais 184-195, substituindo um código de interrupção de I/O que foi armazenado pela instrução. 2. No modo registrador de acesso quando o endereço do segundo operando é zero, uma exceção de acesso é reconhecida se tradução de registrador de acesso ocorre e o registrador de acesso está em erro. Esta exceção pode ser evitada mascarando o campo de zero B2 ou colocando 00000000 hex, 00000001 hex, ou qualquer outro conteúdo válido no registrador de acesso. [0706] Programming Notes: 1. PENDING TEST INTERRUPTION should only be performed with a second address operating from zero when I / O Interrupts are masked. Otherwise, an I / O interrupt code stored by the instruction can be lost if an I / O interruption occurs. The I / O interrupt code that identifies the source of an I / O interruption taken subsequent to PENDING TEST INTERRUPTION is also stored in actual locations 184-195, replacing an I / O interruption code that was stored by the instruction . 2. In access register mode when the address of the second operand is zero, an access exception is recognized if access register translation occurs and the access register is in error. This exception can be avoided by masking the B2 zero field or by placing 00000000 hex, 00000001 hex, or any other valid content in the access register.
[0707] [0707] SUBCANAL STORAGE
[0708] [0708] Status and control information for the designated subchannel is stored in the designated SCHIB.
[0709] [0709] General register 1 contains a subsystem identification word that designates the subchannel for which the information is to be stored. The address of the second operand is the logical address of the SCHIB and must be designated in a word boundary; otherwise, a specification exception is recognized.
[0710] [0710] When the extended I / O measurement block installation is not installed, the information that is stored in the SCHIB consists of a path management control word, SCSW, and three words of model-dependent information. When the extended I / O measurement block installation is installed, the information that is stored in the SCHIB consists of a path management control word, the SCSW, the measurement block address field, and an information word dependent on the model.
[0711] [0711] The execution of the STORAGE SUBCANAL does not change any information in the subchannel.
[0712] [0712] Condition code 0 is defined to indicate that status and control information for the designated subchannel has been stored in the SCHIB. When the execution of the STORAGE SUBChannel results in the definition of condition code 0, the information in the SCHIB indicates a consistent status of the subchannel.
[0713] [0713] Special conditions
[0714] [0714] Condition code 3 is defined, and no further action is taken, when the designated subchannel is not operational for the STORAGE SUBCANAL. A subchannel is not operational for STORAGE SUBChannel if the subchannel is not provided in the channel subsystem.
[0715] [0715] SUBCANAL STORAGE can find the program exceptions described or listed below.
[0716] [0716] When the installation of multiple defined subchannels is not installed, bits 32-47 of general register 1 must contain 0001 hex; otherwise, an operand exception is recognized.
[0717] [0717] When the installation of multiple defined subchannels is installed, bits 32-44 of general register 1 must contain zeros, bits 45-46 must contain a valid value, and bit 47 must contain the value one; otherwise, an operand exception is recognized.
[0718] [0718] The second operand must be designated in a word limit; otherwise, a specification exception is recognized.
[0719] [0719] Resulting condition code:
[0720] [0720] 0 SCHIB stored
[0721] [0721] 1-
[0722] [0722] 2-
[0723] [0723] 3 Not operational
[0724] • Acesso (armazenamento, operando 2) • Operando • Operação privilegiada • Especificação [0724] Program exceptions: • Access (storage, operating 2) • Operating • Privileged operation • Specification
[0725] 1. Estado de dispositivo que é armazenado na SCSW pode incluir dispositivo ocupado, ocupado de unidade de controle, ou indicações de fim da unidade de controle. 2. A informação que é armazenado no SCHIB é obtida a partir do subcanal. A Instrução de SUBCANAL DE ARMAZENAMENTO não faz com que o subsistema de canal interrogue o dispositivo endereçado. 3. SUBCANAL DE ARMAZENAMENTO pode ser executado em qualquer momento para tirar amostras de condições existentes no subcanal, sem fazer com que quaisquer condições de estado pendentes sejam liberadas. 4. Execução repetida do SUBCANAL DE ARMAZENAMENTO sem um atraso interveniente (por exemplo, para determinar quando um subcanal muda de estado) deve ser evitado já que acessos repetidos do subcanal pela CPU podem atrasar ou proibir o acesso do subcanal por um subsistema de canal para atualizar o subcanal. [0725] Programming Notes: 1. Device status that is stored in SCSW can include device busy, control unit busy, or control unit end indications. 2. The information that is stored in the SCHIB is obtained from the subchannel. The SUBCANAL STORAGE Instruction does not cause the channel subsystem to interrogate the addressed device. 3. SUBCANAL STORAGE can be performed at any time to take samples of existing conditions in the subchannel, without causing any pending state conditions to be released. 4. Repeated execution of the STORAGE SUBCANAL without an intervening delay (for example, to determine when a subchannel changes state) should be avoided since repeated accesses of the subchannel by the CPU can delay or prohibit the access of the subchannel by a channel subsystem to update the subchannel.
[0726] [0726] SUBCANAL TEST
[0727] [0727] Status and control information for the subchannel is stored in the designated IRB.
[0728] [0728] General register 1 contains a subsystem identification word that designates the subchannel for which the information is to be stored. The address of the second operand is the logical address of the IRB and must be designated in a word boundary; otherwise, a specification exception is recognized.
[0729] [0729] The information that is stored on the IRB consists of an SCSW, an extended status word, and an extended control word.
[0730] [0730] If the subchannel is pending state, the pending state bit of the state control field is stored as one. Whether the subchannel is in a pending state or does not have an effect on the functions that are performed when the TEST SUB-CHANNEL is executed.
[0731] [0731] When the subchannel is in a pending state and the TEST SUBCANAL is executed, information, as described above, is stored in the IRB, followed by the emptying of certain conditions and indications that exist in the subchannel. If the subchannel is in transport mode, emptying these conditions, specifically the start function, puts the subchannel in command mode. If an I / O interrupt request is pending for the subchannel, the requirement is released. Condition code 0 is defined to indicate that these actions have been taken.
[0732] [0732] When the subchannel is not in a pending state and the SUBCANAL TEST is executed, information is stored in the IRB, and no conditions or indications are released. Condition code 1 is defined to indicate that these actions have been taken.
[0733] [0733] Special conditions
[0734] [0734] Condition code 3 is defined, and no further action is taken, when the subchannel is not operational for TEST SUB-CHANNEL. A subchannel is not operational for SUBCANAL TEST if the subchannel is not provided, has no valid device number associated with it, or is not allowed.
[0735] [0735] The SUBCANAL TEST can find the program exceptions described or listed below.
[0736] [0736] When the installation of multiple defined subchannels is not installed, bits 32-47 of general register 1 must contain 0001 hex; otherwise, an operand exception is recognized.
[0737] [0737] When the installation of multiple defined subchannels is installed, bits 32-44 of general register 1 must contain zeros, bits 45-46 must contain a valid value, and bit 47 must contain the value one; otherwise, an operand exception is recognized.
[0738] [0738] The second operand must be designated in a word limit; otherwise, a specification exception is recognized.
[0739] [0739] When the execution of the TEST SUB-CHANNEL is terminated in addressing and protection exceptions, the status of the sub-channel is not changed.
[0740] [0740] Resulting condition code:
[0741] [0741] 0 IRB stored; pending state subchannel
[0742] [0742] 1 IRB stored; non-pending state subchannel
[0743] [0743] 2-
[0744] [0744] 3 Not operational
[0745] • Acesso (armazenamento, operando 2) • Operando • Operação privilegiada • Especificação [0745] Program exceptions: • Access (storage, operating 2) • Operating • Privileged operation • Specification
[0746] 1. Estado de dispositivo que é armazenado na SCSW pode incluir dispositivo ocupado, ocupado de unidade de controle, ou indicações de fim de unidade de controle. 2. A informação que é armazenado no IRB é obtida a partir do subcanal. [0746] Programming Notes: 1. Device status that is stored in SCSW may include device busy, control unit busy, or end of control unit indications. 2. The information that is stored on the IRB is obtained from the subchannel.
[0747] [0747] The SUBCANAL TEST statement does not cause the channel subsystem to interrogate the addressed device.
[0748] [0748] 3. When an I / O interruption occurs, it is the result of a state condition pending in the subchannel, and typically SUB-CHANNEL TEST is performed to release the state. The SUBCANAL TEST can also be performed at any other time to sample the conditions that exist in the subchannel.
[0749] [0749] 4. Repeated execution of the SUBCANAL TEST to determine when a start function has been completed should be avoided as there are conditions under which completion of the start function may or may not be indicated. For example, if the channel subsystem is retaining a suspended interface control check (IFCC) condition (for any subchannel) since another subchannel is already in a pending state, and if the start function that is tested by the SUBCANAL DE TEST has the only path available for selection the channel path with the IFCC condition, so the start function may not start until the pending status condition in the other subchannel is released, allowing the IFCC condition to be indicated in the subchannel to which it applies.
[0750] [0750] 5. Repeated execution of the SUBCANAL TEST without intervening delay, for example, to determine when a subchannel changes state, should be avoided because of repeated accesses of the subchannel by the CPU can delay or prohibit the access of the subchannel by channel subsystem. The execution of the TEST SUBCANAL by multiple CPUs for the same subchannel at approximately the same time can have the same effect and should also be avoided.
[0751] [0751] 6. The priority of dealing with the I / O interruption by the CPU can be modified by executing SUBCANAL TEST. When the TEST SUBCANAL is executed and the designated subchannel has a pending I / O interruption request, that I / O interruption request is released, and the SCSW is stored, with no relation to any previously established priority. The relative priority of the remaining I / O interruption requests is not changed.
[0752] [0752] As will be appreciated by one skilled in the art, aspects of the present invention can be incorporated as a computer program system, method or product.
[0753] [0753] Appropriately, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.) or an embodiment that combines software and hardware aspects which can all in general be referred to here as a "circuit," "module" or "system". In addition, aspects of the present invention may take the form of a computer program product incorporated in one or more computer-readable media having computer-readable program code incorporated therein.
[0754] [0754] Any combination of one or more computer-readable media can be used. The computer-readable medium may be a computer-readable storage medium. A computer-readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium include the following: an electrical connection having one or more wires, a portable floppy disk, a hard disk, a random access memory (RAM), a memory read-only (ROM), a programmable erasable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc (CD-ROM) read-only memory, an optical storage device, a magnetic storage device, or any suitable combination of the above. In the context of this document, a computer-readable storage medium can be any tangible medium that can contain or store a program for use by or in conjunction with a system, apparatus, or instruction execution device.
[0755] [0755] Referring now to Figure 10, in one example, a computer program product 1000 includes, for example, one or more non-transitory computer-readable storage media 1002 for storing computer-readable program code media or logic 1004 therein to provide and facilitate one or more aspects of the present invention.
[0756] [0756] Program code embedded in a computer-readable medium can be transmitted using an appropriate medium, including but not limited to a wireless, in-line, fiber optic cable, RF, etc., or any suitable combination of the above.
[0757] [0757] Computer program code to perform operations for aspects of the present invention can be written in any combination of one or more programming languages, including an objective oriented programming language, such as Java, Smalltalk, C ++ or the like, and conventional procedural programming languages, such as the "C" programming language, assembly programming languages or the like. The program code can run entirely on the user's computer, partially on the user's computer, as a remote software package, partially on the user's computer and partially on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including the local area network (LAN) or a wide area network (WAN), or the connection can be made with a computer external network (for example, over the Internet using an Internet Service Provider).
[0758] [0758] Aspects of the present invention are described here with reference to the flowchart illustrations and / or block diagrams of the methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of the blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided for a general purpose computer processor, special purpose computer, or other programmable data processing device to produce a machine, such as instructions, which run through the computer's processor or other programmable data processing apparatus, create means to implement the functions / acts specified in the flowchart and / or block diagram blocks or blocks.
[0759] [0759] These computer program instructions can also be stored in a computer-readable medium that can target a computer, another programmable data processing device, or other devices to function in a particular way, such as instructions stored in the middle computer-readable produce a manufacturing article including instructions that implement the function / act specified in the block or blocks of flowchart and / or block diagram.
[0760] [0760] Computer program instructions can also be loaded onto a computer, another programmable data processing device, or other devices to cause a series of operational steps to be performed on the computer, another programmable device, or other devices to produce a computer-implemented process such that instructions that are executed on the computer or other programmable device provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.
[0761] [0761] The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of computer program systems, methods and products in accordance with various embodiments of the present invention. In this sense, each block in the flowchart or block diagrams can represent a module, segment, or piece of code, which comprises one or more executable instructions to implement the specified logical functions. It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession can, in fact, be executed substantially concurrently, or the blocks can sometimes be executed in reverse order, depending on the functionality involved. It will also be noted that each block in the block diagram and / or flowchart illustration, and combinations of the blocks in the block diagrams and / or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the functions or acts specified, or combinations of special-purpose computer and hardware instructions.
[0762] [0762] In addition to the above, one or more aspects of the present invention can be provided, offered, delayed, managed, served, etc. by a service provider that offers management of consumer environments. For example, the service provider can create, maintain, support, etc. computer code and / or a computer infrastructure that performs one or more aspects of the present invention for one or more consumers. In return, the service provider may receive payment from the consumer under subscription and / or fee agreement, as examples. In addition or alternatively, the service provider may receive payment from a SALE of advertising content to one or more third parties.
[0763] [0763] In one aspect of the present invention, an application can be distributed to carry out one or more aspects of the present invention. As an example, the distribution of an application comprises providing computer infrastructure operable to realize one or more aspects of the present invention.
[0764] [0764] As yet another aspect of the present invention, a computing infrastructure can be deployed comprising integrating computer-readable code into a computing system, where the code in combination with the computing system is capable of carrying out one or more aspects of present invention.
[0765] [0765] As a further aspect of the present invention, a process for integrating computing infrastructure comprising integrating computer-readable code into a computer system can be provided. The computer system comprises a computer-readable medium, wherein the computer medium comprises one or more aspects of the present invention. The code in combination with the computer system is capable of realizing one or more aspects of the present invention.
[0766] [0766] Although several embodiments are described above, these are only examples.
[0767] [0767] For example, computing environments of other architectures can incorporate and use one or more aspects of the present invention. As examples, servers other than zl96 servers may include, use and / or benefit from one or more aspects of the present invention. In addition, other instructions and / or commands can be used; and the instructions / commands may include additional information, in less quantity and / or different than that described here. Many variations are possible.
[0768] [0768] Additionally, other types of computing environments can benefit from one or more aspects of the present invention. As an example, a data processing system suitable for storing and / or executing program code is useful that includes at least two processors coupled directly or indirectly to memory elements via a system bus. Memory elements include, for example, local memory used during actual program execution code, volume storage, and cache memory that provide temporary storage for at least some program code in order to reduce the number of times the code must be retrieved from volume storage during execution.
[0769] [0769] Input / Output or I / O devices (including, but not limited to, keyboards, displays, pointing devices, DASD, tape, CDs, DVDs, finger drives and other memory media, etc.) can be coupled with the system either directly or through intervening I / O controllers. Network adapters can also be coupled with the system to allow the data processing system to be coupled with other data processing systems or remote printers or storage devices over intervening public or private networks. Modems, cable modems, and Ethernet cards are just a few of the available types of network adapters.
[0770] [0770] Referring to figure 11, representative components of a host computer system 5000 for implementing one or more aspects of the present invention are depicted. Representative host computer 5000 comprises one or more CPUs 5001 in communication with computer memory (i.e., central storage) 5002, as well as I / O interfaces for storing 5011 media devices and 5010 networks for communicating with other computers or SANs and the like. The 5001 CPU conforms to an architecture having a defined architecture instruction and architectured functionality. The 5001 CPU can have dynamic address translation (DAT) 5003 to transform program addresses (virtual addresses) into real memory addresses. The DAT typically includes a side translation buffer (TLB) 5007 for translation caching so that subsequent accesses to computer memory block 5002 do not require the address translation delay. Typically, cache 5009 is used between computer memory 5002 and processor 5001. Cache 5009 can be hierarchical with a large cache available for more than one CPU and smaller, faster (lower level) caches between the large cache and each CPU. In some implementations, lower-level caches are broken down to provide separate low-level caches for instruction search and data access. In one embodiment, an instruction is fetched from memory 5002 by an instruction search unit 5004 through cache 5009. The instruction is decoded into an instruction decoding unit 5006 and dispatched (with other instructions in some embodiments) to the instruction execution unit or units 5008. Typically several execution units 5008 are employed, for example, an arithmetic execution unit, a floating point execution unit and a branch instruction execution unit. The instruction is executed by the execution unit, accessing operands from specified registers or instruction memory as necessary. If an operand is to be accessed (loaded or stored) from memory 5002, a load / storage unit 5005 typically handles access under control of the instruction being executed. Instructions can be executed on hardware circuits or on internal microcode (firmware) or by a combination of both.
[0771] [0771] As noted, a computer system includes information in local (or main) storage, as well as addressing, protection, and reference and recording of changes. Some aspects of addressing include the format of addresses, the concept of address space, the various types of addresses, and the way in which one type of address is translated into another type of address. Part of the main storage includes permanently designated storage locations. The main storage provides the system with directly addressable, fast-access data storage. Both data and programs must be loaded into main storage (from the input devices) before they can be processed.
[0772] [0772] The main storage can include one or more smaller, faster-access buffer storage, sometimes called caches. The cache is typically physically associated with the CPU or an I / O processor. The effects, except on performance, of physical construction and the use of different storage media are generally not observable by the program.
[0773] [0773] Separate caches can be maintained for instructions and data operands.
[0774] [0774] Information within a cache is maintained in contiguous bytes in an integral limit called a cache block or cache line (or line, to summarize). A model can provide an EXTRACT CACHE ATTRIBUTE statement that returns the size of a cache line in bytes. A template can also provide LONG RELATIVE PRE-SEARCH DATA and PRE-SEARCH DATA instructions that pre-fetch storage in the data or instruction cache or flush data from the cache.
[0775] [0775] The storage is observed as a long horizontal column of bits. For most operations, accesses to store proceed in a sequence from left to right. The column of bits is subdivided into units of eight bits. A unit of eight bits is called a byte, which is the basic building block of all information formats. Each byte location in the store is identified by a unique non-negative integer, which is the address of that byte location or, simply, the byte address. Adjacent byte locations have consecutive addresses, starting with 0 on the left and proceeding in a sequence from left to right. Addresses are unassigned binary integers and are 24, 31, or 64 bits.
[0776] [0776] The information is transmitted between the storage and the CPU or a channel subsystem one byte, or a group of bytes, at once. Unless otherwise specified, for example, in z / Architecture®, a group of bytes in storage is addressed by the leftmost byte of the group. The number of bytes in the group is either implied or explicitly specified by the operation to be performed. When used in a CPU operation, a group of bytes is called a field. Within each group of bytes, for example, in z / Architecture®, bits are numbered in a sequence from left to right. In z / Architecture®, the leftmost bits are sometimes referred to as the "highest order" bits and the rightmost bits as the "lowest order" bits. Bit numbers are not storage addresses, however. Only bytes can be addressed. To operate individual bits of a byte in storage, the entire byte is accessed. The bits in a byte are numbered 0 to 7, from left to right (for example, in z / Architecture®). The bits in an address can be numbered 8-31 or 40-63 for 24-bit addresses, or 1-31 or 33-63 for 31-bit addresses; they are numbered 0-63 for 64-bit addresses. Within any other fixed-length multi-byte format, the bits that make up the format are numbered consecutively starting from 0. For the purposes of error detection, and preferably for correction, one or more check bits can be transmitted with each byte or with a group of bytes. Such check bits are automatically generated by the machine and cannot be controlled directly by the program. Storage capacities are expressed in number of bytes. When the length of a storage operand field is implied by an instruction's operation code, the field is said to have a fixed length, which can be one, two, four, eight, or sixteen bytes. Larger fields may be implied for some instructions. When the length of a storage operand field is not implied but is stated explicitly, the field is said to have a variable length. Operands of variable length can vary in length by increments of one byte (or with some instructions, in multiples of two bytes or other multiples). When information is placed in storage, the contents of only these byte locations are replaced, which are included in the designated field, even though the width of the physical path to storage may be greater than the length of the field that is stored.
[0777] [0777] Certain information units must be in full storage limit. A limit is called an integral for an information unit when its storage address is a multiple of the unit's length in bytes. Special names are given for the fields of 2, 4, 8, and 16 bytes in an integral limit. A word half is a group of two consecutive bytes in a two-byte boundary and is the basic building block of instructions. A word is a group of four consecutive bytes with a limit of four bytes. A double word is a group of eight consecutive bytes with a limit of eight bytes. A quadruple word is a group of 16 consecutive bytes with a limit of 16 bytes. When storage addresses designate word halves, words, double words, and quadruple words, the binary representation of the address contains one, two, three, or four bits of the right-most zero, respectively. Instructions must be in full two-byte limits. The storage operands of most instructions do not have limit alignment requirements.
[0778] [0778] On devices that implement separate caches for instructions and data operands, a significant delay can be passed if the program stores in a cache line from which instructions are subsequently fetched, regardless of whether the storage changes instructions that are sought after.
[0779] [0779] In one embodiment, the invention can be practiced by software (sometimes referred to as licensed internal code, firmware, micro-code, milli-code, pico-code and the like, any of which may be consistent with the present invention ). Referring to Figure 11, software program code incorporating the present invention is typically accessed by the 5001 processor of the host system 5000 from the 5011 long-term storage media devices, such as a CD-ROM drive, drive tape or hard drive. The software program code can be incorporated into any of a variety of known media for use with a data processing system, such as a floppy disk, hard drive, or CD-ROM. The code can be distributed in such media, or it can be distributed to users from computer memory 5002 or storage from one computer system over a 5010 network to other computer systems for use by users of such other systems.
[0780] [0780] The software program code includes an operating system that controls the function and interaction of the various computer components and one or more application programs. Program code is typically paged from the storage medium device 5011 to the relatively higher speed computer storage 5002 where it is available for processing by the 5001 processor. The techniques and methods for incorporating the software program code into memory , in physical media, and / or distributing software code over networks are well known and will not be discussed further here. Program code, when created and stored in a tangible medium (including but not limited to electronic memory modules (RAM), flash memory, Compact Discs (CDs), DVDs, Magnetic Tape and the like, are generally referred to as a "product of computer program ". The computer program product medium is typically readable by a processing circuit preferably on a computer system for execution by the processing circuit.
[0781] [0781] Figure 12 illustrates a representative workstation or server hardware system on which the present invention can be practiced. The 5020 system of Figure 12 comprises a representative base computer system 5021, such as a personal computer, a workstation or a server, including optional peripheral devices. The 5021 base computer system includes one or more 5026 processors and a bus employed to connect and enable communication between the 5026 processors and the other components of the 5021 system according to known techniques. The bus connects the 5026 processor with the 5025 memory and 5027 long-term storage which can include a hard drive (including any magnetic media, CD, DVD and flash memory, for example) or a tape drive for example. The 5021 system must also include a user interface adapter, which connects the 5026 microprocessor over the bus with one or more interface devices, such as a 5024 keyboard, a 5023 mouse, a 5030 printer / scanner and / or other interface, which can be any user interface device, such as a touch screen, digitized input block, etc. The bus also connects a 5022 display device, such as an LCD screen or monitor, to the 5026 microprocessor via a display adapter.
[0782] [0782] The 5021 system can communicate with other computers or computer networks through a network adapter capable of communicating 5028 with a 5029 network. Examples of network adapters are communication channels, called a token, Ethernet or modems . Alternatively, the 5021 system can communicate using a wireless interface, such as a CDPD card (cellular digital packet data). The 5021 system can be associated with such other computers and a local area network (LAN) or a wide area network (WAN), or the 5021 system can be a client in a client / server arrangement with another computer, etc. All of these configurations, as well as the appropriate hardware and software communications, are well known in the art.
[0783] [0783] Figure 13 illustrates a 5040 data processing network in which the present invention can be practiced. The data processing network 5040 can include a plurality of individual networks, such as a wireless network and a wired network, each of which can include a plurality of individual workstations 5041, 5042, 5043, 5044. Additionally, as one skilled in the art will appreciate, one or more LANs may be included, where a LAN may comprise a plurality of intelligent workstations coupled with a host processor.
[0784] [0784] Still referring to figure 13, the work networks can also include computers or servers of main structure, such as a portal computer (client server 5046) or application server (remote server 5048 that can access data repositories and also can be accessed directly from a 5045 workstation). A 5046 portal computer serves as an entry point into each individual network. A portal is necessary when connecting one network protocol with the other. The 5046 portal can preferably be coupled with another network (the Internet 5047, for example) via a communications link. The 5046 portal can also be coupled directly to one or more workstations 5041, 5042, 5043, 5044 using a communications link. The portal computer can be deployed using an IBM eServer ™ System z® server server available from International Business Máquinas Corporation.
[0785] [0785] Referring concurrently to figure 12 and figure 13, software programming code that can incorporate the present invention can be accessed by the 5026 processor of the 5020 system from 5027 long-term storage media, such as a CD-ROM drive or hard disk. The software programming code can be incorporated into any of a variety of known media for use with a data processing system, such as a floppy disk, hard drive, or CD-ROM. The code can be distributed in such media, or it can be distributed to 5050, 5051 users from the memory or storage of one computer system over a network to other computer systems for use by users of such other systems.
[0786] [0786] Alternatively, the programming code can be incorporated into the 5025 memory, and evaluated by the 5026 processor using the processor bus. Such programming code includes an operating system that controls the function and interaction of various computer components and one or more 5032 application programs. The program code is usually paged from the 5027 storage media to high-speed memory. 5025 where it is available for processing by the 5026 processor. The techniques and methods for incorporating software programming code into memory, in physical media, and / or distributing software code over networks are well known and will not be discussed additionally here. Program code, when created and stored on a tangible medium (including but not limited to electronic memory modules (RAM), flash memory, Compact Discs (CDs), DVDs, Magnetic Tape and the like is generally referred to as a "product computer program product ". The computer program product medium is typically readable by a processing circuit preferably on a computer system for execution by the processing circuit.
[0787] [0787] The cache that is most readily available to the processor (usually faster and smaller than other processor caches) is the smallest cache (L1 or level one) and the main storage (main memory) is the level cache highest (L3 if there are 3 levels). The lower level cache is usually divided into an instruction cache (I-Cache) that holds machine instructions to be executed and a data cache (D-Cache) that holds data operands.
[0788] [0788] Referring to figure 14, an example processor embodiment is represented for processor 5026. Typically one or more levels of cache 5053 are employed for blocks of buffer memory in order to improve the performance of the processor. The 5053 cache is a high-speed buffer that holds the cache lines of memory data that are likely to be used. Typical cache lines are 64, 128 or 256 bytes of memory data. Separate caches are generally used for caching instructions rather than caching data. Cache coherence (synchronization of copies of lines in memory and caches) is generally provided by several "snoop" algorithms well known in the art. 5025 main memory storage for a processor system is generally referred to as a cache. In a processor system having 4 levels of cache 5053, main storage 5025 is sometimes referred to as level 5 (L5) cache as it is typically faster and only retains a portion of non-volatile storage (DASD, tape, etc. .) which is available for a computer system. Main storage cache data pages 5025 paged in and out of main storage 5025 by the operating system.
[0789] [0789] A program counter (instruction counter) 5061 keeps track of the address of the current instruction to be executed. A program counter on a z / Architecture® processor is 64-bit and can be truncated to 31 or 24 bits to support previous addressing limits. A program counter is typically incorporated into a computer's PSW (program status word) such that it persists during context switching. Thus, a program in progress, having a program counter value, can be interrupted, for example, by the operating system (context switching from the program environment to the operating system environment). The program's PSW maintains the program counter value while the program is not active, and the program counter (on the PSW) of the operating system is used while the operating system is running. Typically, the program counter is incremented by an amount equal to the number of bytes in the current instruction. RISC (Reduced Instruction Set Computing) instructions are typically fixed in length while CISC (Complex Instruction Set Computing) instructions are typically of variable length. IBM z / Architecture® instructions are CISC instructions having a length of 2, 4 or 6 bytes. The program counter 5061 is modified both by a context switching operation and by a branch removal operation of a branch instruction for example. In a context switching operation, the current program counter value is saved in the program status word along with other status information about the program being executed (such as condition codes), and a new program counter value. The program is loaded by pointing to an instruction for a new program module to be executed. A branch making operation is performed in order to allow the program to make decisions or run within the program by loading the result of the branch instruction to the program counter 5061.
[0790] [0790] Typically a 5055 instruction fetch unit is employed to fetch instructions on behalf of the 5026 processor. The fetch unit either searches for "next sequential instructions", target instructions for instructions taken from branch, or first instructions of a program following a context switch. Modern instruction search units generally employ prefetching techniques to speculatively prefetch prefetch instructions based on the propensity that prefetch instructions should be used. For example, a search unit can fetch 16 instruction bytes that include the next sequential instruction and additional bytes of additional sequential instructions.
[0791] [0791] The searched instructions are then executed by the 5026 processor. In one embodiment, the searched instructions are passed to a dispatch unit 5056 of the search unit. The dispatch unit decodes the instructions and directs information about the decoded instructions to the appropriate 5057, 5058, 5060 units. A 5057 execution unit will typically receive information about decoded arithmetic instructions from the 5055 instruction search unit and will perform operations arithmetic in the operands according to the instruction's operation code. The operands are provided for the execution unit 5057 preferably both from memory 5025, from 5059 archived registers and from an immediate field of the instruction that is executed. Execution results, when stored, are stored both in 5025 memory, 5059 registers and other machine hardware (such as control registers, PSW registers and the like).
[0792] [0792] A 5026 processor typically has one or more 5057, 5058, 5060 units to perform the instruction function. Referring to Figure 15A, an execution unit 5057 can communicate with general architects registered 5059, a decoding / dispatch unit 5056, a load storage unit 5060, and another 5065 processor units via 5071 interface logic. An execution unit 5057 may employ several register circuits 5067, 5068, 5069 to retain information on which the 5066 arithmetic logic unit (ALU) will operate. ALU performs arithmetic operations such as addition, subtraction, multiplication and division as well as a logical function such as e, or and exclusive or (XOR), rotate and move. Preferably ALU supports specialized operations that are dependent on the project. Other circuits can provide other 5072 architecture installations including condition codes and recovery support logic for example. Typically the result of an ALU operation is maintained on a 5070 output recorder circuit that can direct the result to a variety of other processing functions. These are many arrangements of processor units, the present description is only intended to provide a representative understanding of an embodiment.
[0793] [0793] An ADD instruction, for example, can be executed in a 5057 execution unit having arithmetic and logical functionality while a floating point instruction, for example, can be executed in a floating point execution having point capacity of specialized flotation. Preferably, an execution unit operates on operands identified by an instruction performing a function defined by operation code on the operands. For example, an ADD instruction can be executed by a 5057 execution unit on the operands found in two 5059 registers identified by the instruction register fields.
[0794] [0794] The execution unit 5057 performs the arithmetic addition in two operands and stores the result in a third operand where the third operand can be a third register or one of the two source registers. The execution unit preferably uses a 5066 Arithmetic Logic Unit (ALU) which is capable of performing a variety of logic functions such as Shift, Rotate, AND, or and OR as well as a variety of algebraic functions including any of addition, subtraction , multiplication, division. Some 5066 ALUs are designed for scalar operations and some for floating point. Data can be Big Endian (where the least significant byte is in the largest byte address) or Little Endian (where the least significant byte is in the lowest byte address) depending on the architecture. IBM's z / Architecture is Big Endian. Signaled fields can be sign and magnitude, complement of 1 or complement of 2 depending on the architecture. A complement number of 2 is advantageous in that the ALU does not need to design a subtraction capability since any negative value or positive value in complement 2 needs only an addition within the ALU. Numbers are commonly described briefly, where a 12-bit field defines an address in a 4,096-byte block and is commonly described as a 4-Kbyte (Kilobytes) block, for example.
[0795] [0795] Referring to figure 15B, branch instruction information to execute a branch instruction is typically sent to a 5058 branch unit that generally employs a branch prediction algorithm such as a 5082 branch history table to predict the result of branching before other conditional operations are complete. The target of the current branching instruction will be sought and executed in a speculative manner before the conditional operations are complete. When the conditional operations are completed, the branch instructions executed in a speculative manner are both completed and discarded based on the conditions of the conditional operation and the speculated result. A typical branching statement can test condition and branching codes for a target address if the condition codes satisfy the branching requirement of the branching statement, a target address can be calculated based on various numbers including those found in the register fields or a immediate field of instruction, for example. The 5058 branch unit can employ an ALU 5074 having a plurality of 5075, 5076, 5077 input register circuits and an 5080 output register circuit. The 5058 branch unit can communicate with the 5059 general register, decoding dispatch unit. 5056 or other 5073 circuits, for example.
[0796] [0796] The execution of a group of instructions can be interrupted for a variety of reasons including a context switch initiated by an operating system, a program exception or error causing a context switch, an I / O interrupt signal causing a context switching or multiple segmentation activity from a plurality of programs (in a multiple segmentation environment), for example. Preferably, a context switching action saves status information about a program currently running and then loads status information about another program being invoked. The status information can be saved in hardware registers or in memory, for example. The status information preferably comprises a program counter value that points to the next instruction to be executed, condition codes, memory translation information and archived register content. A context switching activity can be performed by hardware circuits, application programs, operating system programs or firmware code (microcode, pico-code or licensed internal code (LIC)) alone or in combination.
[0797] [0797] A processor accesses the operands according to methods defined by the instruction. The instruction can provide an immediate operand using the value of a portion of the instruction, it can provide one or more register fields that explicitly point to both general purpose registers and special purpose registers (eg, floating point registers) ). The instruction can use implicit registers identified by an opcode field as operands. The instruction can use memory locations for the operands. An operand's memory location can be provided by a register, an immediate field, or a combination of registers and immediate field as exemplified by the z / Architecture® long shift installation where the instruction defines a base register, a register index and an immediate field (displacement field) that are added together to provide the address of the operand in memory, for example. The location here typically implies a location in main memory (main storage) unless otherwise noted.
[0798] [0798] With reference to figure 16C, a processor accesses storage using a 5060 load / storage unit. The 5060 load / storage unit can perform a load operation by obtaining the address of the target operand in memory 5053 and loading the operand in a 5059 register or other 5053 memory location, or it can perform a storage operation by obtaining the address of the target operand in memory 5053 and storing data obtained from a 5059 register or another 5053 memory location in the location of target operand in memory 5053 The 5060 load / storage unit can be speculative and can access memory in a sequence that is out of order with respect to the instruction sequence, however the 5060 load / storage unit is to maintain the appearance for the programs that instructions were executed in order. A 5060 load / storage unit can communicate with general register 5059, decode / dispatch unit 5056, cache / memory interface 5053 or other 5083 elements and comprises several register circuits, ALUs 5085 and 5090 control logic to calculate the storage addresses and to provide link sequencing to keep operations in order. Some operations may be out of order but the load / storage unit provides functionality to make operations out of order appear to the program as having been performed in order, as is well known in the art.
[0799] [0799] Preferably addresses that an application program "sees" are generally referred to as virtual addresses. Virtual addresses are sometimes referred to as "logical addresses" and "effective addresses". These virtual addresses are virtual in that they are redirected to physical memory locations by one of a variety of dynamic address translation (DAT) technologies including, but not limited to, simply pre-fixed virtual addresses with a value of displacement, translation of the virtual address through one or more translation tables, the translation tables preferably comprising at least one segment table and one page table alone or in combination, preferably the segment table having an entry pointing to the page table. In z / Architecture®, a translation hierarchy is provided including a first region table, a second region table, a third region table, a segment table and an optional page table. The performance of address translation is generally improved by using a side translation buffer (TLB) that comprises entries that map a virtual address to an associated physical memory location. Entries are created when the DAT translates a virtual address using the translation tables. Subsequent use of the virtual address can then use the fast TLB entry instead of the slow sequential translation table accesses. TLB content can be managed by a variety of replacement algorithms including LRU (Last used).
[0800] [0800] In the case where the processor is a processor of a system of multiple processors, each processor has the responsibility of maintaining divided resources, such as I / O, caches, TLBs and memory, interlocked for consistency. Typically, "snoop" technologies will be used to maintain cache coherence. In a snoop environment, each cache line can be marked as being in either a split state, a unique state, an altered state, an invalid state, and the like in order to facilitate division.
[0801] [0801] 5054 I / O units (figure 14) provide the processor with means for attaching to peripheral devices including tape, disk, printers, displays, and networks, for example. I / O units are usually presented to the computer program by the software drivers. In main structures, such as the z® system from IBM®, channel adapters and open system adapters are I / O units of the main frame that provide communications between the operating system and peripheral devices.
[0802] [0802] Additionally, other types of computing environments can benefit from one or more aspects of the present invention. As an example, an environment can include an emulator (for example, software or another emulation mechanism), in which a particular architecture (including, for example, instruction execution, architected functions, such as address translation, and architected registers) or a subset of them is emulated (for example, on a native computer system having a processor and memory). In such an environment, one or more emulation functions of the emulator can implement one or more aspects of the present invention, even though a computer running the emulator may have a different architecture than the capabilities that are emulated. As an example, in emulation mode, the specific instruction or operation that is emulated is decoded, and an appropriate emulation function is built to implement the individual instruction or operation.
[0803] [0803] In an emulation environment, a host computer includes, for example, memory to store instructions and data; an instruction search unit to search for instructions from memory and to optionally provide local buffering for the searched instruction; an instruction decoding unit to receive the instructions sought and to determine the type of instructions that were sought; and an instruction execution unit for executing instructions. Execution may include loading data into a register from memory; storing data back into memory from a register; or performing some kind of arithmetic or logical operation, as determined by the decoding unit. In one example, each unit is implemented in software. For example, operations that are performed by the units are implemented as one or more subroutines within emulator software.
[0804] [0804] More particularly, in a main structure, engineered machine instructions are used by programmers, commonly "C" programmers today, usually through a compiler application. These instructions stored on the storage medium can be executed natively on an IBM® z / Architecture® server, or alternatively on machines running other architectures. They can be emulated on existing and future IBM® backbone servers and on other IBM® machines (for example, Power Systems servers and x® system servers). they can run on machines that run on Linux on a wide variety of machines using hardware manufactured by IBM®, Intel®, AMD ™, and others. In addition to running on that hardware under z / Architecture®, Linux can be used as well as machines that use Hercules, UMX, or FSI (Fundamental Software, Inc) emulation, where in general the execution is in an emulation mode. In emulation mode, emulation software is run by a native processor to emulate the architecture of an emulated processor.
[0805] [0805] The native processor typically runs emulation software comprising both firmware and a native operating system to perform the emulation of the emulated processor. The emulation software is responsible for fetching and executing instructions from the emulated processor architecture. The emulation software maintains an emulated program counter to keep track of instruction limits. The emulation software can fetch one or more emulated machine instructions at once and convert the one or more emulated machine instructions to a corresponding group of native machine instructions for execution by the native processor. These converted instructions can be cached such that faster conversion can be achieved. Nevertheless, the emulation software must maintain the architectural rules of the architecture of the emulated processor in order to ensure that the operating systems and applications written for the emulated processor operate correctly. Additionally, the emulation software is to provide features identified by the emulated processor architecture including, but not limited to, control registers, general purpose registers, floating point registers, dynamic address translation function including segment tables and tables for example, interrupt mechanisms, context switching mechanisms, Time of Day (TOD) clocks and interfaces designed for I / O subsystems such as an operating system or application program designed to run on the emulated processor , can be run on the native processor using the emulation software.
[0806] [0806] A specific instruction that is emulated is decoded, and a subroutine is called to perform the function of the individual instruction. An emulation software function that emulates a function of an emulated processor is implemented, for example, in a "C" subroutine or driver, or some other method to provide a driver for specific hardware as will be within the skill of the person skilled in the art after understanding the description of the preferred embodiment. Several software and hardware emulation patents including, but not limited to, US Charter Patent No. 5,551,013, entitled "Multiprocessor for Hardware Emulation", by Beausoleil et al; and US Charter Patents No. 6,009,261, entitled "Preprocessing of Stored Target Routines for Emulating Incompatible Instructions on a Target Processor", by Scalzi et al; and U.S. Patent Charters No. 5,574,873, entitled "Decoding Guest Instruction to Directly Access Emulation Routines that Emulate the Guest Instructions", by Davidian et al; and U.S. Patent Charters No. 6,308,255, entitled "Symmetrical Multiprocessing Bus and Chipset Used for Coprocessor Support Allowing Non-Native Code to Run in a System", by Gorishek et al; and U.S. Patent Charges No. 6,463,582, entitled "Dynamic Optimizing Object Code Translator for Architecture Emulation and Dynamic Optimizing Object Code Translation Method", by Lethin et al; and U.S. Patent Charts No. 5,790,825, entitled "Method for Emulating Guest Instructions on a Host Computer Through Dynamic Recompilation of Host Instructions" by Eric Traut, each of which is incorporated herein by reference in its entirety; and many others, illustrate a variety of known ways to achieve the emulation of an instruction format designed for a different machine for a target machine available to the person skilled in the art.
[0807] [0807] In figure 16, an example of an emulated host computer system 5092 is provided that emulates a host computer system 5000 'of a host architecture. In the 5092 emulated host computer system, the 5091 host processor (CPU) is an emulated host processor (or virtual host processor) and comprises a 5093 emulation processor having a different defined native instruction architecture than that of the processor 5091 of the host computer 5000 '. The emulated host computer system 5092 has memory 5094 accessible to the emulation processor 5093. In the example of the embodiment, memory 5094 is partitioned into a portion of host computer memory 5096 and a portion of emulation routines 5097. A 5096 host computer memory is available for the 5092 emulated host computer programs according to the host computer architecture. The 5093 emulation processor executes native instructions from a defined architecture instruction of a different architecture than that of the 5091 emulated processor, the native instructions obtained from the memory of 5097 emulation routines, and can access a host instruction for execution from a program in host computer memory 5096 incorporating one or more instructions obtained in an access / decoding sequence and routine that can decode accessed host instructions to determine a native instruction execution routine to emulate the instruction function host accessed. Other facilities that are defined for the host computer system architecture 5000 'can be emulated by the routines of architected facilities, including such facilities as general purpose registers, control registers, dynamic address translation and I / O subsystem support. and processor cache, for example. Emulation routines can also take advantage of functions available on the 5093 emulation processor (such as general registers and dynamic translation of virtual addresses) to improve the performance of emulation routines. Special hardware and discharge motors can also be provided to assist the 5093 processor in emulating the function of the host computer 5000 '.
[0808] [0808] The terminology used here is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used here, the singular forms "one", "one", "a" and "o" are also intended to include the plural forms, unless the context clearly indicates otherwise. Additionally, it will be understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of declared functionalities, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other functionalities, integers, steps, operations, elements, components and / or groups thereof.
[0809] [0809] The corresponding structures, materials, acts, and equivalents of all means or elements of function plus step in the claims below, if any, are intended to include any structure, material, or act to perform the function in combination with others claimed elements as specifically claimed. The description of the present invention has been presented for the purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the disclosed form. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the invention. The embodiment has been chosen and described in order to better explain the principles of the invention and the practical application, and to allow other experts in the art to understand the invention for various embodiments with various modifications that are suitable for the particular intended use.

权利要求:
Claims (10)
[0001]
Method of executing a subchannel start instruction in a computing environment that comprises main storage memory and storage class memory comprising the steps of: in response to the determination that a subchannel identified by the start subchannel instruction is an asynchronous data movement (ADM) subchannel that performs: obtaining an operation request block (200) from the main storage, the operation request block (200) comprising an address (206) of an operating block (220), characterized by the fact that based on the address of the operation block, obtain the main storage operation block (220), the operation block (220) consisting of a request block (22), a response block (224), and a list of one or more of the first motion specification blocks (MSB) (226), the list identifying a defined member of MSBs, wherein the order block (222) comprises an MSB count field (234) having a value indicating the count of MSBs that make up an order associated with the operation order block, where the response block (224) is configured to maintain exception conditions, where each first motion specification block (226) is configured to include a first field of the operation code (262), a first block count field (268), a first main storage address field (270), a first storage class memory address field (272), a first block size field (266) and a first d field and flags (264); obtaining a first movement specification block from one or more of the first movement specification blocks, wherein the first flag field (264) of the first movement specification block (226) comprises an extension indicator for the next MSB, from here hereinafter referred to as the BNM indicator, and where more than a defined number of MSBs can be specified to designate a large number of MSBs in the order block's MSB count field and to use the extension indicator for next MSB in the first field flags to branch a continuation of the list of MSBs, which need not be contiguous; in response to the BNM indicator having a first BNM value, perform an operation based on a first operation code (262) in the first obtained motion specification block (226), the operation being performed on a series of memory blocks of storage class of a size determined by the first block size field (266), where the number of blocks is determined by the first block count field (268), and in response to the BNM indicator having a second BNM value: branch a second MSB located at an address specified by the first main storage address field (270) of the first MSB (226), wherein the second MSB comprises a second block size field (266), a second block count field (268) and a second operation code (262); and perform an operation based on the second operation code (262) on the second MSB (226) obtained, the operation being performed on a series of storage class memory blocks of a size determined by the second block size field (266), wherein the number of blocks is determined from the second block count field (268).
[0002]
Method, according to claim 1, characterized by the fact that in response to the first operation code or the second operation code to be adjusted to a first value, the performance comprises performing an operation in which the data blocks are moved from the storage class memory (130, 140, 180) for main storage (104).
[0003]
Method, according to claim 1, characterized by the fact that in response to the first operation code or the second operation code to be adjusted to a second value, the performance comprises performing an operation in which the data blocks are moved from the main storage (104) for storage class memory (130, 140, 180).
[0004]
Method according to claim 1, characterized by the fact that in response to the first operation code or the second operation code to be adjusted to a third value, the performance comprises performing a cleaning operation.
[0005]
Method according to claim 1, characterized by the fact that in response to the first operation code or the second operation code to be adjusted to a fourth value, the performance comprises performing a launch operation.
[0006]
Method according to claim 1, characterized in that the size designated in the first block size field (266) or in the second block size field (266) is 4K or 1M.
[0007]
Method, according to claim 1, characterized by the fact that it also comprises generating (338) one or more status conditions, in response to the conclusion (336) of the operation, to one or more of the status conditions accessible to an issuer of the subchannel start instruction.
[0008]
Method according to claim 1, characterized by the fact that the response block (224) is configured to indicate one or more errors and is filled in response to an error condition detected during the execution of the operation.
[0009]
Method, according to claim 1, characterized by the fact that in response to the BNM indicator with the second BNM value, the first operation code field (262), the first block size field (266), the the first block count field (268) and the first storage class memory address field (272) are meaningless.
[0010]
Computer system characterized by the fact that it comprises means adapted to carry out all stages of the method, as defined in any one of claims 1 to 9.

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法律状态:
2018-12-11| B06F| Objections, documents and/or translations needed after an examination request according art. 34 industrial property law|

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2019-10-29| B06U| Preliminary requirement: requests with searches performed by other patent offices: suspension of the patent application procedure|

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2021-02-09| B09A| Decision: intention to grant|

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2021-03-23| B16A| Patent or certificate of addition of invention granted|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 10/05/2012, OBSERVADAS AS CONDICOES LEGAIS. |

优先权:

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