巴西专利BR112013029295B1 INK LEVEL SENSOR

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专利摘要:
ink level sensor. in one configuration, a method for detecting an ink level includes applying a vp preload voltage to a detection capacitor to charge the detection capacitor with a q1 charge, sharing q1 between the detection capacitor and a reference capacitor, causing a reference voltage vg at the port of an evaluation transistor, and determining a resistance from the drain to the source of the evaluation transistor that results from vg.
公开号:BR112013029295B1
申请号:R112013029295-4
申请日:2011-06-27
公开日:2020-10-06
发明作者:Ning Ge；Judy Benjamin；Teck Khim Neo；Joseph M. Torgerson；Neel Banerjee；George H. Corrigan
申请人:Hewlett-Packard Development Company, L.P；
IPC主号:

专利说明:

Background
Accurate ink level detection in supply reservoirs for all types of inkjet printers is desirable for a number of reasons. For example, detecting the correct ink level and providing a corresponding indication of the amount of ink remaining in an ink cartridge allows printer users to prepare to replace exhausted ink cartridges. Accurate ink level indications also help to avoid wasting ink, as inaccurate ink level indications often result in premature replacement of ink cartridges that still contain ink. In addition, printing systems can use ink level detection to trigger certain actions that help prevent low-quality prints that could result from inadequate supply levels.
Although a number of techniques are available to determine the level of ink in a reservoir, or fluidic chamber, several challenges remain related to its accuracy and cost. Brief description of the drawings
The present configurations will now be described, by way of example, with reference to the attached drawings, in which:
Figure 1 shows a fluid ejection device configured as an inkjet printing system suitable for incorporating an ink level sensor, according to a configuration;
Figure 2 shows a bottom view of an end of a TIJ printhead having a single slit of fluid formed on a silicon matrix substrate, according to one configuration;
Figure 3 shows a cross-sectional view of an exemplary fluid drop generator, according to a configuration;
Figure 4 shows a cross-sectional view of an exemplary detection structure, according to a configuration;
Figure 5 shows a time diagram of non-overlapping time signals used to drive a printhead, according to a configuration;
Figure 6 shows an exemplary ink level sensor circuit, according to a configuration;
Figure 7 shows a cross-sectional view of a detection structure with both a detection capacitor and an intrinsic parasitic capacitance, according to a configuration;
Figure 8 shows a cross-sectional view of an exemplary detection structure that includes a parasitic elimination element, according to a configuration;
Figure 9 shows an exemplary ink level sensor circuit with a parasitic elimination circuit, according to a configuration; and
Figure 10 shows a flow diagram of an exemplary method for detecting an ink level, according to a configuration. Detailed Description
Overview of the problem and solution
As noted above, there are a number of techniques available for determining the level of ink in a reservoir such as a fluidic chamber. For example, prisms were used to reflect or refract beams of light in ink cartridges to generate electrical and / or user-visible ink level indications. Back pressure indicators are another way to determine ink levels in a reservoir. Some printing systems count the number of ink drops ejected from the print cartridges as a way to determine ink levels. Still other techniques use the electrical conductivity of the ink as an ink level indicator in printing systems. Challenges remain, however, with regards to improving the accuracy and cost of ink level detection systems and techniques.
The configurations of the present disclosure provide an ink level sensor and related methods that improve over previous ink level detection techniques. The sensor and methods disclosed employ a capacitive, load-sharing detection circuit on board the thermal inkjet printhead (TIJ). The detection circuit implements a sampling and retention technique that captures the state of the ink level through a capacitive sensor. The capacitance of the capacitive sensor changes with the ink level. A load placed on the capacitive sensor is shared between the capacitive sensor and a reference capacitor, causing a reference voltage at the port of an evaluation transistor. A current source in an application-specific integrated circuit (ASIC) printer supplies current to the transistor drain. The ASIC measures the resulting voltage at the current source and calculates the corresponding drain resistance for the source of the evaluation transistor. The ASIC then determines the status of the ink level based on the resistance determined from the evaluation transistor.
In one configuration, an ink level sensor includes a detection capacitor whose capacitance changes with the level of ink in a chamber. The sensor includes a switch T2 for applying a voltage Vp to the detection capacitor, which places a charge on the detection capacitor. Another switch T3 shares the load between the detection capacitor and a reference capacitor, resulting in a reference voltage Vg. An evaluation transistor is configured to provide resistance from drain to source in proportion to the reference voltage.
In another configuration, an ink level sensor includes a detection capacitor between an Ml node and the ground.
A switch T2 connects a voltage Vp to Ml to charge the detection capacitor, and a switch T3 connects Ml to M2 to share the load between the detection capacitor and a reference capacitor, causing a voltage Vg in M2. The sensor includes a transistor T4 having a drain, a port coupled to M2, a source coupled to ground. A current source injects a current into the drain, and an executable module calculates a resistance between the drain and the source of the transistor based on a Vid voltage measured at the drain.
In one configuration, a method for detecting an ink level includes applying a preload voltage Vp to a detection capacitor to charge the detection capacitor with a charge Ql. The charge Q1 is then shared between the detection capacitor and a reference capacitor, causing a reference voltage Vg at the port of an evaluation transistor. The method then determines a resistance from the drain to the source of the transistor that results from Vg at the transistor port.
In another configuration, a method for detecting an ink level includes placing a charge on a detection capacitor in an Ml memory node. The M1 node is then coupled to a secondary memory node M2 to share the load between the detection capacitor and a reference capacitor. The shared load causes a reference voltage Vg in Ml, M2, and in a transistor port. A resistance through the drain to the source of the transistor is then determined, and the resistance is compared with a reference value to determine an ink level. Illustrative configurations
Figure 1 illustrates a fluid ejection device configured as an inkjet printing system 100 suitable for incorporating an ink level sensor as disclosed here, according to a disclosure configuration. In this configuration, a fluid ejection assembly is disclosed as a fluid drop blasting printhead 114. The inkjet printing system 100 includes an inkjet printhead assembly 102, a supply set of ink 104, an upstream assembly 106, a media transport assembly 108, an electronic printer controller 110, and at least one power supply 112 that supplies power to the various electrical components of the inkjet printing system 100. The inkjet printhead assembly 102 includes at least one fluid ejection assembly 114 (printhead 114) that ejects ink droplets through a plurality of nozzles or nozzles 116 against a print media 118 in order to printing on print media 118. Print media 118 can be any type of sheet or roll material suitable, such as paper, cardboard, transparencies, polyester, plywood, foam board a, fabric, canvas, and the like. Nozzles 116 are typically arranged in one or more columns or arrangements such that the correctly sequenced ejection of ink from nozzles 116 causes characters, symbols, and / or other graphics or images to be printed on print media 118 as the inkjet printhead assembly 102 and print media 118 are moved together.
The ink supply set 104 provides fluid ink for the printhead assembly 102 and includes a reservoir 120 for storing ink. Ink flows from reservoir 120 to inkjet printhead assembly 102. Ink supply assembly 104 and inkjet printhead assembly 102 can form a one-way ink delivery system or a recirculating ink supply system. In a one-way ink supply system, substantially all of the ink supplied to the inkjet printhead assembly 102 is consumed during printing. In a recirculating ink supply system, however, only a portion of the ink supplied to the printhead assembly 102 is consumed during printing. The ink not consumed during printing is returned to the ink supply set 104.
In one configuration, the ink supply set 104 delivers ink under positive pressure through an ink conditioner set 105 to the inkjet printhead set 102 via an interface connection, such as a supply tube. The ink supply set 104 includes, for example, a reservoir, pumps and pressure regulators. Conditioning in the ink conditioner set 105 may include filtering, preheating, pressure surge absorption, and degassing. The ink is extracted under negative pressure from the printhead set 102 to the ink supply set 104. The pressure difference between the inlet and outlet for the printhead set 102 is selected to achieve the correct back pressure in nozzles 116, and is usually a negative pressure between 1 "negative and 10" negative H20. The reservoir 120 of the ink supply set 104 can be removed, replaced, and / or refilled.
The riser assembly 106 positions the inkjet printhead assembly 102 with respect to the media transport assembly 108, and the media transport assembly 108 positions the print media 118 with respect to the jet printhead assembly Thus, a printing zone 122 is defined adjacent to the nozzles 116 in an area between the inkjet printhead assembly 102 and the print media 118. In one configuration, the printhead assembly a inkjet 102 is a scan-type printhead assembly. As such, the upstream assembly 106 includes a cart for moving the inkjet printhead assembly 102 relative to the media transport assembly 108 for scanning the print media 118. In another configuration, the print head assembly inkjet print 102 is a non-scan printhead set. As such, the upstream assembly 106 secures the inkjet printhead assembly 102 in a prescribed position with respect to the media transport set 108. Thus, the media transport set 108 positions the print media 118 relative to to the 102 inkjet printhead assembly.
The electronic printer controller 110 typically includes a processor, firmware [resident startup program], software, one or more memory components including volatile and non-volatile memory components, and other printer electronics to communicate with and control the set of inkjet printhead 102, upright set 106, and media transport set 108. The electronic controller 110 receives data 124 from a host system, such as a computer, and temporarily stores data 124 in a memory. Typically, data 124 is sent to the inkjet printing system 100 along an electronic, infrared, optical, or other information transfer path. Data 124 represents, for example, a document and / or file to be printed. As such, data 124 forms a print job for inkjet printing system 100 and includes one or more print job command parameters and / or parameters.
In one configuration, the electronic printer controller 110 controls the inkjet printhead assembly 102 for ejecting ink droplets from nozzles 116. Thus, electronic controller 110 defines a pattern of ejected ink droplets that they form characters, symbols, and / or other graphics or images on the print media 118. The pattern of the ejected ink droplets is determined by the print job command commands and / or parameters from data 124. In one configuration, the electronic controller 110 includes an application-specific integrated circuit (ASIC) 126 and a resistance detection firmware module 128 executable on ASIC 126 or controller 110. Printer ASIC 126 includes a current source 13 0 and an analog converter to digital (ADC) 132. The ASIC 126 can convert the voltage present in the current source 130 to determine a resistance, and then determine a corresponding value of digital resistance to through ADC 132. A programmable algorithm implemented by resistance detection module 128 allows the determination of resistance and the subsequent digital conversion by ADC 132.
In the described configurations, the inkjet printing system 100 is an on-demand thermal drop inkjet printing system with a thermal inkjet printhead (TIJ) 114 suitable for implementing an ink level sensor as disclosed here. In one implementation, the inkjet printhead assembly 102 includes a single TIJ 114 printhead. In another implementation, the inkjet printhead assembly 102 includes a wide array of TIJ 114 printheads. Although the manufacturing processes associated with TIJ printheads are well suited for integrating the ink level sensor, other types of printheads such as a piezoelectric printhead can also implement such an ink level sensor. Therefore, the disclosed ink level sensor is not limited to implementation on a TIJ 114 printhead.
Figure 2 shows a bottom view of an end of a TIJ 114 printhead having a single slit of fluid 200 formed on a silicon matrix substrate 202, according to a configuration of the disclosure. Although the printhead 114 is shown with a single slit of fluid 200, the principles discussed here are not limited in its application to a printhead with only one slit 200. On the contrary, other printhead configurations are also possible, such as printheads with two or more ink slits. In the TIJ 114 printhead, substrate 202 is beneath a chamber layer having fluid chambers 204 and a nozzle layer having nozzles 116 formed therein, as discussed below with reference to figure 3. However, for the purpose of illustration , the chamber layer and the nozzle layer in figure 2 are assumed to be transparent to show the substrate below 202. Therefore, the chambers 204 in figure 2 are illustrated using dashed lines. Fluid slit 200 is an elongated slit formed in substrate 022 which has fluid drop generators 300 (figure 3) arranged along both sides of the slit. The fluid slot 200 is in fluid communication with a fluid supply (not shown), such as a fluid reservoir 120.
Figure 3 shows a cross-sectional view of an exemplary fluid drop generator 300, according to a configuration of the disclosure. Each drop generator 300 includes a nozzle 116, a fluid chamber 204 and a firing element 302 disposed in the fluid chamber 204. Nozzles 116 are formed in the nozzle layer 310 and are generally arranged to form nozzle columns along the nozzles. sides of the fluid slot 200. The firing element 302 is a thermal resistor formed of a metal plate (eg, tantalum-aluminum, TaAl) on an insulating layer 304 (eg, polysilyl glass, PSG ) on an upper surface of the silicon substrate 202. A passivation layer 306 on the trigger element 302 protects the ink trigger element in chamber 204 and acts as a protective cavitation barrier or mechanical passivation barrier to absorb shock of steam bubbles exploding. A chamber layer 308 has walls and chambers 204 that separate substrate 202 from nozzle layer 310.
During operation, a drop of fluid is ejected from a chamber 204 through a corresponding nozzle 116 and the chamber 204 is then replenished with fluid circulating from the fluid slot 200. More specifically, an electric current is passed through a resistor firing element 302 resulting in rapid heating of the element. A thin layer of fluid adjacent to the passivation layer 306 on the firing element 302 is overheated and vaporizes, creating a vapor bubble in the corresponding firing chamber 204. The rapidly expanding vapor bubble forces a drop of fluid out of the corresponding nozzle 116. When the heating element cools, the vapor bubble quickly explodes, extracting more fluid from the fluid slot 200 into the firing chamber 204 in preparation to eject another drop from the nozzle 116.
Referring again to figure 2, in addition to the drop generators 300, the TIJ 114 printhead includes one or more ink level sensors integrated into the printhead 206. An ink level sensor 206 generally includes a detection 208 and an ink level sensor circuit 210 integrated in the printhead 114. Meanwhile, an ink level sensor 206 additionally incorporates a current source 130 and an analog to digital converter (ADC) 132 from an ASIC printer 126 that is not integrated in the printhead 114. On the contrary, the printer ASIC 126 is located, for example, in the printer cart or electronic controller of the printer system 100. The ink level sensor circuit 210 incorporates a detection capacitor (Detection) 212 from inside the detection structure 208. A detection structure 208 and an ink level sensor circuit 210 can be located on the head substrate Note the print along the ink slot 200 in any position where a typical drop generator 300 is located. The detection structure 208 and ink level sensor circuit 210 are discussed in more detail below with respect to figs. 4 and 5.
Figure 4 shows a cross-sectional view of an exemplary detection structure 208, according to a configuration of the disclosure. The detection structure 208 is generally configured in the same way as the typical drop generator 300, but it can include additional features such as a compensating resistor 214 (shown in figure 2) used to purge ink residue from the structure chamber detection element 208. Therefore, as a typical drop generator 300, the detection structure 208 includes a nozzle 116, a fluid chamber 204, a conductive element such as a metal plate firing element 302 disposed in the fluid chamber 204 , a passivation layer 306 on the firing element 302, and an insulating layer 304 (e.g., polysilicon glass, PSG) on an upper surface of the silicon substrate 202.
Within the detection structure 212, a detection capacitor (Detection) 212 is formed by the metal plate element 302, the passivation layer 306 and the substance or contents of the chamber 204. The value of the detection capacitor 212 changes as the substance inside chamber 204 changes. The substance in chamber 204 can be all paint, paint and air, or just air. Therefore, the value of detection capacitor 212 changes with the ink level in chamber 204. When ink is present in chamber 204, detection capacitor 212 has good ground conductance so the capacitance value is higher (that is, 100%). However, when there is no ink in chamber 204 (i.e., only air) the capacitance of detection capacitor 212 drops to a very small value, which is ideally close to zero. When the chamber contains ink and air, the capacitance value of the detection capacitor 212 is somewhere between zero and 100%. Using the changed value of detection capacitor 212, the ink level sensor circuit 210 is able to determine the ink level. In general, the ink level in chamber 204 is indicative of the ink level in reservoir 120 of the printing system 100. In some configurations, before measuring the ink level with sensor circuit 210, a compensation resistor 214 (shown in figure 2) is used to purge ink residue from the detection frame chamber 208. Thereafter, to the extent that ink is present in reservoir 120, it flows back into the chamber to allow an accurate measurement of the level of ink.
Figure 5 shows an example of a part-time diagram 500 having non-overlapping time signals (SI - S3) with synchronized data and trigger signals that can be used to drive a printhead 114, according to a disclosure configuration. . The time signals in the time diagram 500 are also used to trigger the operation of the ink level sensor circuit 210 as discussed below with reference to figure 6.
Figure 6 shows an exemplary ink level sensor circuit 210, according to a disclosure configuration. In general, the sensor circuit 210 employs a load sharing mechanism to determine different levels of ink in a chamber. The sensor circuit 210 includes two first transistors, TI (Tia, Tlb), configured as switches. Referring to figs. 5 and 6, during the operation of the sensor circuit 210, in a first step a time pulse SI is used to close the transistor switches Tia and Tlb, coupling the memory nodes M1 and M2 to the ground and discharging the detection capacitor 212 and the reference capacitor 600. The reference capacitor 600 is the capacitance between node M2 and ground. In this configuration, the reference capacitor 600 is implemented as the inherent gate capacitance of the evaluation transistor T4, and is therefore illustrated using dashed lines. The reference capacitor 600 additionally includes associated parasitic capacitance such as overlapping capacitance of the source port, but the port capacitance of T4 is the dominant capacitance in the reference capacitor 600. Using the port capacitance of transistor T4 as a reference capacitor 600 reduces the number of components in the sensor circuit 210 by avoiding a specific reference capacitor manufactured between node M2 and ground. However, in other configurations, it may be beneficial to adjust the value of reference capacitor 600 by including a specific capacitor made from M2 to ground (ie, in addition to the inherent port capacitance of T4).
In a second step, the SI time pulse ends, opening the Tia and Tlb switches. Directly after the TI switches open, a time pulse S2 is used to close the transistor switch T2. Closing T2 couples the Ml node to a pre-charge voltage, Vp (eg, on the order of +15 volts), and a charge Q1 is placed through the detection capacitor 212 according to the equation, Q1 (Cdetection ) (Vp). At this moment, node M2 remains at zero voltage potential since time pulse S3 is off. In a third step, the time pulse S2 ends, opening the transistor switch T2. Directly after switch T2 opens, time pulse S3 closes switch transistor T3, coupling nodes M1 and M2 to each other and sharing the load Q1 between detection capacitor 212 and reference capacitor 600. The shared load Q1 between capacitor sensor 212 and reference capacitor 600 results in a reference voltage, Vg, at node M2 which is also on the gate of the evaluation transistor T4, according to the following equation:
Vg remains in M2 until another cycle begins with a SI time pulse grounding memory nodes M1 and M2. Vg in M2 connects the evaluation transistor T4, which allows measurement in ID (the drain of the transistor T4). In this configuration it is assumed that the transistor T4 is forced in the linear mode of operation, where T4 acts as a resistor whose value is proportional to the voltage of the gate Vg (that is, the reference voltage). The T4 resistance from the drain to the source (coupled to earth) is determined by forcing a small current in ID (that is, a current of the order of 1 milliamp). The ID is coupled to a current source, such as the current source 130 in printer ASIC 126. When applying the current source in ID, the voltage is measured in ID (VID). Firmware, such as the Rdetection 128 module running on controller 110 or ASIC 126 can convert VID to a drain resistor Rds for the source of transistor T4 using current and VID. The ADC 132 in the printer ASIC 126 subsequently determines a corresponding digital value for the resistance Rds. The resistance Rds allows an inference as to the value of Vg based on the characteristics of the transistor T4. Based on a value for Vg, a Cdetection value can be found from the equation for Vg shown above. An ink level can then be determined based on the Detection value.
Once the Rds resistance is determined, there are several ways in which the ink level can be found. For example, the measured Rds value can be compared to a Rds reference value, or a table of Rds values determined experimentally to be associated with specific ink levels. Without ink (ie, a "dry" signal), or a very low ink level, the value of detection capacitor 212 is very low. This results in a very low Vg (on the order of 1.7 volts), and the evaluation transistor T4 is switched off or almost switched off (ie, T4 is in the region of cut or sub-limit operation). Therefore, the Rds resistance of Id to ground through T4 would be very high (eg, with an ID current of 1.2 mA, Rds is typically above 12 kohm). Conversely, with a high ink level (ie, a "wet" signal), the value of detection capacitor 212 is close to 100% of its value, resulting in a high value for Vg (on the order of 3.5 volts ). Therefore, the Rds resistance is low. For example, with a high ink level Rds is below 1 kohm, and is typically a few hundred ohms.
Figure 7 shows a cross-sectional view of an exemplary detection structure 208 that illustrates both the detection capacitor 212 and an intrinsic parasitic capacitance Cpl (700) below the metal plate 302 that forms part of the detection capacitor 212, of according to a disclosure configuration. The intrinsic parasitic capacitance Cpl 700 is formed by metal plate 302, insulation layer 304, and substrate 202. As described above, an ink level sensor 206 determines an ink level based on the capacitance value of the detection capacitor 212 However, when a voltage (ie, Vp) is applied to the metal plate 302, carrying the detection capacitor 212, the capacitor Cpl 700 also charges. Because of this, the parasitic capacitance Cpl 700 can contribute on the order of 20% of the capacitance determined for the detection capacitor 212. This percentage will vary depending on the thickness of the insulation layer 304 and the dielectric constant of the insulation material. However, the remaining charge at the Cpl 700 parasitic capacitance in a "dry" state (ie, where no ink is present) is sufficient to connect the T4 evaluation transistor. The parasitic Cpl 700, therefore dilutes the dry / wet signal.
Figure 8 shows a cross-sectional view of an exemplary detection structure 208 that includes a parasitic elimination element 800, according to a configuration of the disclosure. The parasitic elimination element is a conductive layer 800 such as a poly silicon layer designed to eliminate the impact of the parasitic capacitance Cpl 700. In this design, when a voltage (i.e., Vp) is applied to the metal plate 302, it also is applied to the conductive layer 800. This prevents a charge from developing on the Cpl 700 such that the Cpl is effectively removed / isolated from the determination of the capacitance of the detection capacitor 212. Cp2, element 802, is the intrinsic capacitance from the element of detection. parasitic elimination 800 (poly conductive layer 800). Cp2 802 reduces the charge speed of the parasitic elimination element 800, but has no impact on the removal / isolation of Cpl 700 because there is sufficient charge time provided for element 800.
Figure 9 shows an exemplary ink level sensor circuit 210 with a parasitic elimination circuit 900, according to a disclosure configuration. In figure 9, the parasitic capacitance Cpl 700 is shown coupled between the metal plate 302 (node Ml) and the conductive layer 800 (node Mp). Referring to figs. 8 and 9, the ink level sensor circuit 210 with the parasitic elimination circuit 900 are triggered by non-overlapping time signals such as those shown in time diagram 500 in figure 5. In a first step, a SI time pulse is used to close the Tia, Tib and Tpl transistor switches. Closing the Tia, Tlb and Tpl switches connects memory nodes Ml, M2 and Mp to ground, discharging the detection capacitor (Cdetection) 212, the reference capacitor (Cref) 600 and the parasitic capacitor (Cpl) 700. In one In the second stage, the SI time pulse ends, opening the Tia, Tlb and Tpl switches. Directly after the Tia, Tlb and Tpl switches open, a S2 time pulse is used to close the T2 and Tp2 transistor switches. Closing T2 and Tp2 couples nodes Ml and Mp, respectively, to a preload voltage, Vp. This places a charge Q1 through the detection capacitor (Cdetection) 212. However, with nodes Ml and Mp at the same voltage potential, Vp, no charge develops through the parasitic capacitor (Cpl) 700.
The ink level sensor circuit 210 then continues to function as described above with respect to figure 6. Thus, in a third step, the time pulse S2 ends, opening the transistor switches T2 and Tp2. Directly after switches T2 and Tp2 open, the time pulse S3 closes transistor switches T3 and Tp3. Closing switch T3 couples the M1 and M2 nodes together and shares the Q1 load between the detection capacitor 212 and the reference capacitor 600. The shared load Q1 between the detection capacitor 212 and the reference capacitor 600 results in a voltage reference number, Vg, at node M2 which is also at the gate of the evaluation transistor T4. Closing the Tp3 switch couples the parasitic capacitor (Cpl) 700 to the ground. During the time pulse S3, the parasitic charge in Cpl 700 is discharged, leaving only the detection capacitor 212 to be evaluated with the evaluation transistor T4. Once the effect of the parasitic capacitor (Cpl) 700 is removed, for a dry signal there is a very small parasitic contribution to turning on T4.
Figure 10 shows a flow diagram of an exemplary method 1000 for detecting an ink level, according to a disclosure configuration. Method 1000 is associated with the configurations discussed above with respect to figs. 1-9. Method 1000 starts at block 1002 by applying a preload voltage Vp to a detection capacitor to charge the detection capacitor with a charge Q. Applying Vp to the detection capacitor includes coupling Vp to a first memory node Ml closing a T2 switch. In another configuration, applying Vp additionally includes applying Vp to an Mp node to prevent a parasitic capacitor between Ml and Mp from charging.
In step 1004 of method 1000, a charge Q1 is shared between the detection capacitor and a reference capacitor, causing a reference voltage Vg at the port of an evaluation transistor. Sharing load Q1 includes opening T2 to disconnect Vp from the detection capacitor, and closing a switch T3 to couple the detection capacitor to the reference capacitor. The share couples M1 to a second memory node M2 to share the load between the detection capacitor and a reference capacitor, and the shared load causes the reference voltage Vg in M1, M2, and at the transistor port.
Method 1000 continues in step 1006 with the determination of a resistance from the drain to the source of the evaluation transistor that results from Vg. The resistance is determined by forcing a current in the transistor drain, measuring a voltage, Vid, in the transistor drain, running an algorithm to calculate the resistance from the current and Vid, and converting the resistance to a digital value.
In step 1008 of method 1000, an ink level is determined by comparing the resistance with a group of resistors that have predetermined associated ink levels. In step 1010 of method 1000, before applying the preload voltage Vp, the detection capacitor and the reference capacitor are discharged.

权利要求:
Claims (9)
[0001]
1. Ink level sensor characterized by the fact that it comprises: - a detection capacitor (212) whose capacitance changes with an ink level in a chamber (204); - a first switch (T2) to apply a voltage Vp to the detection capacitor (212), placing a load on the detection capacitor (212); - a second switch (T3) to share the load between the detection capacitor (212) and a reference capacitor (600), resulting in a reference voltage Vg; and - an evaluation transistor (T4) configured to provide resistance from the drain to the source in proportion to the reference voltage Vg.
[0002]
2. Ink level sensor according to claim 1, characterized in that the detection capacitor (212) comprises: - a metal plate (302); - a passivation layer (306) on the metal plate (302); and - substance in a chamber (204) above the passivation layer (306).
[0003]
3. Ink level sensor, according to claim 2, characterized in that the substance is selected from the group consisting of ink, ink and air, and air.
[0004]
4. Ink level sensor, according to claim 1, characterized by the fact that the reference capacitor (600) comprises a capacitance of the evaluation transistor port (T4).
[0005]
5. Ink level sensor according to claim 1, characterized by the fact that it also comprises a detection structure that includes the detection capacitor (212), the chamber (204), a nozzle (116), a metal plate a firing element (302) disposed within the fluid chamber (204), a passivation layer (306) on the firing element, and an insulating layer (304) on a silicon substrate (202).
[0006]
6. Ink level sensor according to claim 1, characterized by the fact that it also comprises a compensation resistor (214) for purging ink residue from the chamber (204).
[0007]
7. Ink level sensor according to claim 2, characterized in that the metal plate (302) comprises a trigger element resistor.
[0008]
8. Ink level sensor according to claim 2, characterized by the fact that it further comprises a parasitic elimination element (800) to eliminate a parasitic capacitance formed below the metal plate (302).
[0009]
Ink level sensor according to claim 8, characterized in that the parasitic elimination element (800) comprises a conductive poly silicon layer.

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同族专利:

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法律状态:
2018-12-26| B06F| Objections, documents and/or translations needed after an examination request according art. 34 industrial property law|

2019-04-30| B06T| Formal requirements before examination|

2020-05-12| B09A| Decision: intention to grant|

2020-10-06| B16A| Patent or certificate of addition of invention granted|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 27/06/2011, OBSERVADAS AS CONDICOES LEGAIS. |

优先权:

申请号 | 申请日 | 专利标题

PCT/US2011/042043|WO2013002762A1|2011-06-27|2011-06-27|Ink level sensor and related methods|

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