BIT INTERCALATION METHOD, BIT DECREASER METHOD, BIT INTERCATER, BIT DECREASER AND DECODER

专利摘要:
parallel bit interleaving. The present invention relates to a bit interleaving method which involves applying a bit permutation process to a qc-ldpc codeword composed of cyclic n blocks each including q bits, and dividing the codeword after the process of permutation into a plurality of constellation words each including m bits, the codeword being divided into f×n/m folding sections, each of the constellation words being associated with one of the f×n folding sections /m, and the bit permutation process being applied such that each of the constellation words includes f bits from each of the different cyclic blocks m/f in a given folding section associated with a given constellation word.
公开号:BR112013029037B1
申请号:R112013029037-4
申请日:2012-05-18
公开日:2021-06-29
发明作者:Mihail Petrov
申请人:Panasonic Corporation；
IPC主号:

专利说明:

Technical Field
[001] The present disclosure relates to the field of digital communications, and more specifically to a bit interleaver for a bit-interleaved modulation and encoding system with quasi-cyclic low-density parity check codes. Background Technique
[002] In recent years, bit-interleaved coding and modulation systems (hereinafter, BICM) have been used in the field of digital communications (see, for example, Non-Patent Literature 1).
[003] BICM systems generally incorporate the following three steps. (1) Encoding of data blocks into codewords using, for example, quasi-cyclic low-density parity check code (hereinafter, QC LDPC), or similar. (2) Carrying out bit interleaving in bits of each codeword. (3) Dividing each bit-interleaved codeword into constellation words having a number of constellation bits, and mapping the constellation words into constellations. Citation List Patent Literature Patent Literature 1 ETSI EN 302 755 V1.2.1 (DVB-T2 Standard) Invention Summary Technical problem
[004] Typically, efficiency is desirable in the interleaving applied to quasi-cyclic low-density parity check codewords.
[005] The present disclosure aims to provide an interleaving method that enables efficient interleaving to be applied to quasi-cyclic low-density parity-check codewords. Solution to Problem
[006] In order to achieve the above-cited objective, a bit interleaving method for a communication system using quasi-cyclic low-density parity check codes comprises: a step of receiving and receiving a codeword of the codes of quasi-cyclic low-density parity checking composed of N-cyclic blocks each including Q bits; a bit swapping step of applying a bit swapping process to the codeword so as to swap the bits in the codeword; and a dividing step of dividing the codeword, after the bit permutation process, into a plurality of constellation words, each of the constellation words being composed of M bits, and indicating one of the 2M constellation points in a predetermined constellation, in which before the bit permutation process, the codeword is divided into folding sections FxN/M, F being an integer greater than one, each of the folding sections including M/F of the cyclic blocks, and each of the constellation words being associated with one of the FxN/M folding sections, and in the bit permutation step, the bit permutation process is applied such that the M bits in each of the constellation words include F bits of each of the different M/F cyclic blocks in a given folding section associated with a given constellation word, and such that all bits in the given folding section are mapped to only Q/F of the constellation words associated with the given if folding action. Advantageous Effects of the Invention
[007] The bit interleaving method of the present invention enables effective interleaving to be applied to the codewords of the quasi-cyclic low-density parity check codes. Brief Description of Drawings
[008] Fig. 1 is a block diagram showing the configuration of a transmitter that includes a typical BICM encoder.
[009] Fig. 2 illustrates an example of a parity check matrix for quasi-cyclic low-density parity check codes having an encoding rate of 1/2.
[0010] Fig. 3 illustrates an example of a parity check matrix for repeating accumulated quasi-cyclic low-density parity check codes having a coding rate of 2/3.
[0011] Fig. 4 illustrates a parity check matrix for the accumulated nearly cyclic low density parity check codes of Fig. 3 after a row permutation.
[0012] Fig. 5 illustrates a parity check matrix for repeating accumulated quasi-cyclic low density parity check codes of Fig. 3 after a row permutation and a parity permutation.
[0013] Fig. 6 describes different robustness levels of bits encoded in eight PAM symbols.
[0014] Fig. 7 is a block diagram showing the configuration of a typical bit interleaver where the cyclic factor Q is 8, the number of cyclic blocks per low density parity check codeword N is 12, and the number bits per constellation Me 4.
[0015] Fig. 8A is a block diagram showing the configuration of a DVB-T2 modulator used in the DVB-T2 standard, and Fig. 8B is a block diagram showing the configuration of a BICM decoder for the modulator of DVB-T2 of Fig. 8A.
[0016] Fig. 9A illustrates a writing process for the bits of a 16K codeword (i.e., an LDPC code where the LDPC codeword length is 16200 bits) as performed by a column-row interleaver having twelve columns, and Fig. 9B illustrates a reading process for the bits of the codeword written in the manner indicated by Fig. 9A as performed by the column-row interleaver.
[0017] Fig. 10A illustrates a writing process for the bits of a 16K codeword as performed by a column-row interleaver having eight columns, and Fig. 10B illustrates a reading process for the bits of the codeword. code written in the manner indicated by Fig. 10A as performed by the column-row interleaver.
[0018] Fig. 11 is a block diagram showing the configuration of a bit-to-cell demultiplier used for 16-QAM 16K codes in the DVB-T2 standard.
[0019] Fig. 12 is a block diagram showing the configuration of a bit-to-cell demultiplier used for 16K and 64-QAM codes in the DVB-T2 standard.
[0020] Fig. 13 is a block diagram showing the configuration of a bit-to-cell demultiplier used for 256-QAM 16K codes in the DVB-T2 standard.
[0021] Fig. 14 illustrates a problem that occurs for 16K codes with an eight-column DVB-T2 bit interleaver.
[0022] Fig. 15 illustrates a problem that occurs for 16K codes with a twelve column DVB-T2 bit interleaver.
[0023] Fig. 16 illustrates a problem that occurs for 16K codes with an eight column DVB-T2 bit interleaver when column twisting is applied.
[0024] Fig. 17 illustrates a problem that occurs for 16K codes with a twelve column DVB-T2 bit interleaver when column twisting is applied.
[0025] Figs. 18A and 18B respectively illustrate a first and second condition discovered by the inventors enabling an extremely effective interleaver to be provided.
[0026] Fig. 19 illustrates a mapping function by an interleaver belonging to an Embodiment.
[0027] Fig. 20 is a block diagram showing the configuration of an interleaver belonging to an Embodiment.
[0028] Fig. 21A is a block diagram showing the configuration of a section changer that performs the section permutation illustrated in Fig. 20, and Fig. 21B illustrates a mapping function of the section changer shown in Fig. 21A.
[0029] Fig. 22A is a block diagram showing an alternate configuration of a section exchanger that performs the section permutation illustrated in Fig. 20, and Fig. 22B illustrates a mapping function of the section exchanger shown in Fig. 22A.
[0030] Fig. 23 is a block diagram showing the configuration of an interleaver belonging to another Embodiment.
[0031] Fig. 24 is a block diagram showing the configuration of the bit interleaver shown in Fig. 23.
[0032] Fig. 25 is a block diagram showing the configuration of a transmitter belonging to another Embodiment.
[0033] Fig. 26 is a block diagram showing the configuration of a BICM encoder belonging to another Embodiment.
[0034] Fig. 27 is a block diagram showing the configuration of a receiver including a non-interactive BICM decoder belonging to another Embodiment.
[0035] Fig. 28 is a block diagram showing the configuration of a receiver including an interactive BICM decoder belonging to another Embodiment.
[0036] Fig. 29 is a block diagram showing the configuration of an interactive BICM decoder belonging to another Embodiment.
[0037] Fig. 30 illustrates an example of cyclic blocks included in and excluded from a parallel interleaver process.
Figs. 31A and 31B respectively illustrate a first and second condition discovered by the inventors that enable an extremely effective interleaver to be provided.
[0039] Fig. 32 is a block diagram showing the configuration of an interleaver belonging to another Embodiment.
[0040] Fig. 33A illustrates a mapping function for a non-folding situation (F = 1), and fig. 33B illustrates a mapping function for a situation with folding (F = 2).
[0041] Fig. 34A is a block diagram showing the configuration of a (folding) section exchanger for the situation without bending (F = 1), and Fig. 34B is a block diagram showing the configuration of a exchanger of bending section for the situation with bending (F = 2).
[0042] Fig. 35 is a block diagram showing the configuration of an interleaver belonging to another Embodiment.
[0043] Fig. 36 is a block diagram showing the configuration of the bit interleaver shown in Fig. 35.
[0044] Fig. 37 is a block diagram showing the configuration of a transmitter belonging to another Embodiment.
[0045] Fig. 38 is a block diagram of a receiver including a non-interactive BICM decoder belonging to another Embodiment.
[0046] Fig. 39 is a block diagram of a receiver including an interactive BICM decoder belonging to another Embodiment.
[0047] Fig. 40 illustrates LLR memory locations for folding with F = 2, and bit positions for the first constellation word.
[0048] Fig. 41 schematically represents the mapping of constellation blocks belonging to hybrid QPSK+16QAM codes.
[0049] Fig. 42 is a block diagram showing the configuration of an interleaver belonging to another Embodiment.
[0050] Fig. 43 is a block diagram showing the configuration of an interleaver belonging to another Embodiment. Description of Achievements Background Information
[0051] Fig. 1 is a block diagram showing the configuration of a transmitter 100 that includes a modulation encoder and typical bit-interleaved encoding (hereinafter, BICM). As shown, transmitter 100 includes an input processor 110, a BICM encoder (in turn including a low-density parity check encoder (hereinafter, LDPC) 120, a bit interleaver 130, and a bit mapper. constellation 140), and a modulator 150.
[0052] The input processor 110 converts an input bit stream into blocks of a predetermined length. LDPC encoder 120 encodes the blocks into codewords using LDPC codes, and then transmits the codewords to bit interleaver 130. Bit interleaver 130 applies an interleaving process to each LDPC codeword , then splits each interleaved codeword into a sequence of cell words (that is, constellation words). Constellation mapper 140 maps each cell word (i.e., constellation word) to a sequence of constellations (eg, using QAM). The generic modulator 150 at the output includes all processing blocks from the output of the BICM encoder to a radio frequency power amplifier (hereinafter, RF).
[0053] An LDPC code is a linear error correction code that is fully defined by a parity check matrix (hereafter, PCM). A PCM is a sparse binary array that represents the connection of codeword bits (hereafter also called variable nodes) to parity checks (hereafter also called check nodes). The columns and lines of the PCM respectively correspond to the variable nodes and the verification nodes. In PCM, a connection between a variable node and a verification node is represented by a one-element.
[0054] Quasi-cyclic low-density parity check codes (hereinafter, QC LDPC) are a variety of LDPC codes. LDPC QC codes have a structure that is particularly suitable for hardware implementation. In fact, many standards in use today employ LDPC QC codes. The PCM of an LDPC QC code having a special configuration composed of a plurality of circulating matrices. A circulating matrix is a square matrix where each row is a cyclical change of elements in the previous row, and has one, two, or more bend diagonals. Each circulating matrix has a size of Q x Q. Here, Q represents the cyclic factor to QC LDPC. The quasi-cyclic configuration described above allows Q verification nodes to be processed in parallel, which is clearly beneficial for efficient hardware implementation.
[0055] Fig. 2 shows the PCM of an LDPC QC code having a Q cyclic factor of eight, as an example. In Fig.2 as well as in Figs. 3 and 5 described later, the smaller squares each represent an element of the PCM, where the black squares are one-elements and all other squares are zero-elements. The PCM shown has circulating dies with one or two each folded diagonals. This LDPC QC code encodes a block of 8x6 = 48 bits into a codeword of 8x12 = 96 bits. Consequently, the encoding rate of LDPC QC is 48/96 = 1/2. The codeword bits are divided into a plurality of blocks of Q bits each. Q bit blocks are hereinafter called cyclic blocks (or cyclic groups) for this relation to the other cyclic factor of Q.
[0056] A special variety of LDPC QC codes are repeating accumulated quasi-cyclic low density parity check codes (hereinafter, RA QC LDPC). LDPC QC RA codes are well known to be easy to encode, and are therefore used in a wide variety of standards (for example, in second generation DVB standards, including DVB-S2, DVB-T2, and DVB- C2). The right side of the PCM corresponds to the parity bits. The one-elements in these are arranged in a ladder structure. Fig. 3 shows an example of a PCM for an RA QC LDPC having an encoding rate of 2/3.
[0057] Above and completely, DVB-T is an abbreviation of Digital Video Broadcasting - Terrestrial, DVB-S2 is an abbreviation of Digital Video Broadcasting - Second Generation Satellite, DVB-T2 is an abbreviation of Digital Video Broadcasting - Second Generation Terrestrial, and DVB-C2 is an abbreviation for Digital Video Broadcasting - Second Generation Cable.
[0058] By applying a simple row permutation to the PCM shown in Fig. 3, the quasi-cyclic structure of the RA QC LDPC codes is revealed, with the exception of the parity portion shown in Fig. 4. The row permutation it is a simple graphical representation change having no influence on the code definition.
[0059] The quasi-cyclic structure of the PCM parity portion is impaired by applying a line permutation suitable for only the PCM parity bits shown in Fig. 4. This technique is widely known in the field and is used in such standards as DVB-T2, under the name of parity interleaving or parity permutation. Fig. 5 shows the PCM obtained as a result of applying such a parity permutation to the PCM shown in Fig. 4.
[0060] Typically, bits of an LDPC codeword vary in importance, and bits of a constellation vary in level of robustness. Mapping the bits of an LDPC codeword to a constellation directly, ie without interleaving, leads to suboptimal performance. Thus, the bits of the LDPC codeword require interleaving before mapping into the constellations.
[0061] For this proposal, the bit interleaver 130 is provided between the LDPC encoder 120 and the constellation mapper 140, as shown in Fig. 1. By carefully designating the bit interleaver 130, the association between the bits of the word of LDPC code and constellation encoded bits is improved, leading to improved receiver performance. Performance is typically measured using a bit error rate (hereafter, BER) as a function of the signal-to-noise ratio (hereafter, SNR).
[0062] The LDPC codeword bits differ in importance primarily because not all bits are necessarily involved in the same number of parity checks. The more parity checks (check nodes) a given codeword bit (variable node) is involved, the more important the given codeword bit is in an iterative LDPC decoding process. An additional reason is that the variable nodes each have different connectivity to the cycles of a Tanner graph representing the LDPC codes. Therefore, the codeword bits are likely to differ in importance despite being involved in the same number of parity checks. These ideas are well understood in the field. As a rule, the importance of variable nodes increases as the number of verification nodes connected to them increases.
[0063] In the particular case of QC LPDC codes, all bits included in a cyclic block of Q bits have the same number of parity checks applied in it, and have the same connectivity to the cycles of the Tanner graph. In this way, all bits are of equal importance.
[0064] Similarly, the encoded bits of a constellation are widely known to have different levels of robustness. For example, a quadrature amplitude modulation constellation (hereafter QAM) is composed of two independent pulse amplitude modulation symbols (hereafter PAM), one symbol corresponding to the real part and the other symbol corresponding to the imaginary part. The two PAM symbols each encode M bits. Fig. 6 shows 8-PAM symbols using Gray encoding. As shown, the bits encoded by each PAM symbol vary in terms of robustness level. The difference in robustness is a result of the distance between two subsets defined by each bit (eg 0 or 1) being different for each of the bits. The greater the distance, the more robust and secure the bit. Fig. 6 indicates that bit b3 has the highest robustness level, while bit b1 has the lowest robustness level.
[0065] Thus, a 16-QAM constellation encodes four bits, and has two levels of robustness. Also, a 64-QAM constellation encodes six bits, and has three robustness levels. Likewise, a 256-QAM constellation encodes eight bits, and has four robustness levels.
[0066] The following parameters are hereinafter used throughout the present description. Cyclic factor: Q = 8 Number of cyclic blocks per LDPC codeword: N = 12 Number of bits per constellation: M = 4 (ie 16-QAM)
[0067] Given the above parameters, the number of constellations to which each LDPC codeword is mapped is equal to Q x N/M = 24. Typically, the Q and N parameters are selected such that QxN is equal to a multiple from M for all constellations supported by the system.
[0068] Fig. 7 is a block diagram showing the configuration of a typical interleaver when the above parameters are applied. In Fig. 7, the 12 cyclic blocks are labeled QB1, ..., QB 12, and the 24 constellations are labeled C1, ..., C24. A bit interleaver 710 interleaves the 96 bits of the LDPC codeword.
[0069] A conventional bit interleaver is known from the DVB-T2 standard (see ETSI EN 302 755). The DVB-T2 standard is a television standard featuring improvements over the DVB-T standard, and describes a second generation baseline transmission system for digital television broadcasting. The DVB-T2 standard gives the details of a channel coding and modulation system for television broadcast and generic data services.
[0070] Fig. 8A is a block diagram showing the structure of a modulator used in the DVB-T2 standard (ie, a DVB-T2 modulator). The DVB-T2 modulator 800 includes an input processor 810, a BICM encoder 820, a frame builder 830, and an OFDM generator 840.
[0071] The input processor 810 converts an input bit stream into blocks of a predetermined length. The BICM encoder 820 applies BICM processing to the input. Structure builder 830 uses input from BICM encoder 820 and the like to generate a distribution structure in DVB-T2 format. OFDM generator 840 performs pilot addition, fast Fourier transform application, protection interval insertion, and the like, in the distribution structure, then outputs a broadcast signal in DVB-T2 format.
[0072] The BICM used in the DVB-T2 standard is described in chapter 6 of the ETSI EN 302 755 standard. The aforementioned standard is incorporated herein by reference and explained below.
[0073] Fig. 8B is a block diagram showing the structure of BICM encoder 820 in DVB-T2 modulator 800 illustrated in Fig. 8A. Fig. 8B omits BCH outer coding, constellation rotation, cell interleaver, time interleaver, and the like.
[0074] The BICM encoder 820 includes an LDPC encoder 821, a bit interleaver (in turn including a parity interleaver 822 and a column-row interleaver 823), a bit-to-cell demultiplier 824, and an 825 QAM mapper.
[0075] The LDPC encoder 821 encodes the blocks into codewords using LDPC codes. Bit interleaver (which includes parity interleaver 822 and column-row interleaver 823) performs interleaving on the codeword bits. Bit-to-cell demultiplexer 824 demultiplexes the interleaved bits of the codewords into cell words (constellation words). The 825 QAM mapper maps cell word (constellation words) to complex QAM symbols. Complex QAM symbols are also called cells. In fact, bit-to-cell demultiplier 824 can also be considered a part of the bit interleaver. In such situations, the BICM encoder that conforms to the DVB-T2 standard can be considered to have the basic structure shown in Fig. 1.
[0076] The LDPC codes used in the DVB-T2 standard are RA QC LDPC codes having a cyclic factor of Q = 360. Two codeword lengths are defined for the DVB-T2 standard, one being 16200 bits and the other being 64800 bits. In the present document, LDPC codes using a codeword length of 16200 bits are referred to as 16K codes (or as 16K LDPC Codes), and LDPC codes having a codeword length of 64800 bits are referred to as 64K codes (or as 64K LDPC Codes). The number of cyclic blocks per codeword is 45 for 16K codes and 180 for 64K codes. The available codes corresponding to each block length (code word length) are given in Tables A1 to A6 of ETSI EN 302 755 for the DVB-T2 standard.
[0077] The bit interleaver is only used for constellations larger than quadrature phase shift switching constellations (hereinafter, QPSK), and includes parity interleaver 822, column-row interleaver 823, and the bit-to-cell demultiplier 824. According to the DVB-T2 standard, the bit interleaver does not include the bit-to-cell demultiplier 824. However, this document pertains to the interleaver as applied to LDPC codes before the constellation mapping. As such, bit-to-cell demultiplier 824 is treated as a part of the bit interleaver.
[0078] The parity interleaver 822 performs parity permutation on the parity bits of each codeword in order to clarify the quasi-cyclic structure thereof, as described above (see Figs. 4 and 5).
[0079] Conceptually, column-row interleaver 823 operates by writing the bits of each LDPC codeword similar to the column in an interleaver matrix, then reading the bits per row. The first bit of the LDPC codeword is written first, and read first. After writing and before reading the LDPC codeword bits, column-row interleaver 823 cyclically shifts the bit columns by a predetermined number of positions. This is called column twisting in the DVB-T2 standard. The number of columns Nc and the number of rows Nr in the interleaver matrix are given in Table 1 for various constellation sizes in accordance with the two aforementioned LDPC codeword lengths. Table 1

[0080] The number of columns Nc is twice the number of bits per constellation, with the exception of 16K codes with a constellation of 256-QAM. This exception occurs because the LDPC Codeword Constellation of 16200 is not a multiple of 16, that is, it is not twice the number of bits per constellation of 256-QAM.
[0081] The codeword bit writing process and bit reading process for 16K codes performed by column-row interleaver 823 is illustrated in Figs. 9A and 9B for twelve columns, and in Figs. 10A and 10B for eight columns. Each of the small squares corresponds to one bit of the LDPC codeword. The blackened square represents the first bit of the LDPC codeword. Arrows indicate the order in which bits are written and read from the interleaver matrix. For example, when the interleaver matrix has twelve columns, the codeword bits of the 16K code are written in the order given in Fig. 9A, namely, (Row 1, Column 1), (Row 2, Column 1), ..., (Row 1350, Column 1), (Row 1, Column 2), ..., (Row 1350, Column 12), then read in the order given in Fig. 9B, namely, (Row 1 , Column 1), (Row 1, Column 2), ..., (Row 1, Column 12), (Row 2, Column 1), ..., (Row 1350, Column 12). Figs. 9A, 9B, 10A, and 10B do not illustrate the column twisting process.
[0082] Before QAM mapping, bit-to-cell demultiplexer 824 demultiplexes the LDPC codewords to obtain a plurality of parallel bit streams. The number of streams is twice the number of M coded bits per QAM constellation, ie 2*M, with the exception of 16K LDPC codes with a 256-QAM constellation. For 16K LDPC codes with a constellation of 256-QAM, the number of streams equals the number of M coded bits per QAM constellation. The constellation encoded M bits are referred to as a cell word (constellation word). For LDPC 16K codes, the number of cell words per codeword is 16200/M as given below. 8100 cells for QPSK, 4050 cells for 16-QAM, 2700 cells for 64-QAM, and 2025 cells for 256-QAM.
[0083] According to Table 1, given above, the number of parallel streams is equal to the number of columns in the column-row interleaver for constellations larger than QPSK. The bit-to-cell demultiplier corresponding to 16 QAM constellations, 64 QAM constellations, and 256 QAM constellations for 16K LDPC codes are respectively shown in Figs. 11, 12, and 13. The bit notation used is that of the DVB-T2 standard.
[0084] As shown in Fig. 11 (and Figs. 12 and 13), bit-to-cell demultiplexer 824 includes a single demultiplexer 1110 (also 1210, 1310) and a demux exchanger 1120 (also 1220, 1320).
[0085] In addition to having the single demultiplexer 1110 (1210, 1310), it simply demultiplexes the LDPC codewords, to which the interleaving has been applied, the bit-to-cell demultiplexer 824 also has the demux exchanger 1120 ( 1220, 1320) which performs a permutation on the demultiplexed parallel bitstreams.
[0086] However, when column-row interleaver is used (ie, for 16 QAM constellations or greater), the permutation applied to the bit streams is identical to a permutation applied to the columns of the column-row interleaver due to number of parallel bit streams being equal to the number of columns. Therefore, the permutation performed by the bit-to-cell demultiplier 824 is related as a part of the bit interleaver.
[0087] The bit interleaver used in the DVB-T2 standard essentially has two problems.
[0088] The first problem is that parallelism is impaired when the number of cyclic blocks in the LDPC codeword is not a multiple of the number of columns in the bit interleaving matrix. Reduced parallelism leads to increased latency. This is especially problematic when interactive BICM decoding is used by the receiver. This situation occurs for various combinations of LDPC codeword constellation and constellation size in DVB-T2 standard.
[0089] Figs. 14 and 15 illustrate the aforementioned situation for 16K LDPC code cases where the interleaver matrix has eight and twelve columns, respectively. Eight columns are used in the interleaver matrix for 16 QAM constellations and 256 QAM constellations. Twelve columns are used in the collator matrix for 64 QAM constellations. In Figs. 14 and 15, the grid represents an LDPC codeword, the small squares each represent a bit of the LDPC codeword, the rows correspond to cyclic blocks, and the columns correspond to bits of the same bit index within a cyclic block. The blackened squares represent the eighth and twelfth bits of the first row in the interleaver matrix. For ease of understanding, the number of bits per cyclic block has been reduced from 360 to 72. However, this does not affect comprehension.
[0090] The second problem is that, in the DVB-T2 standard, the number of possible bit interleaving configurations is limited by the number of columns in the bit interleaving matrix.
[0091] An additional problem of the DVB-T2 bit interleaver is that the regularity and parallelism of the permutation are impaired by the column twisting process. Figs. 16 and 17 respectively illustrate the same situations as Figs. 14 and 15, with the addition of the column twisting process. When the interleaver matrix has eight columns for the 16K LDPC codes, the column twist values for the DVB-T2 bit interleaver columns are (0, 0, 0, 1, 7, 20, 20, 21). Similarly, when the interleaver matrix has twelve columns for the 16K LDPC codes, the column twist values for the DVB-T2 bit interleaver columns are (0, 0, 0, 2, 2, 2, 3, 3 , 3, 6, 7, 7).
[0092] Consequently, a bit interleaver that reduces latency while improving parallelism is desired. These properties are particularly important in interactive BICM decoding. Experimental Discoveries
[0093] The inventor has discovered, as the fruit of prolonged experimentation, that an intercalator that satisfies the following two conditions is extremely efficient. Condition 1
[0094] The M bits of each constellation are each mapped to one of the M different cyclic blocks of the LDPC codeword. This is equivalent to mapping a bit of M different cyclic blocks from the LDPC codeword to a constellation word. This is schematically illustrated in Fig. 18A. Condition 2
[0095] All constellation words mapped to the M cyclic blocks are mapped only to that particular cyclic block. This is equivalent to mapping all the MxQ bits of the different M cyclic blocks each composed of Q bits to exactly Q constellations. This is schematically illustrated in Fig. 18B.
[0096] The above conditions imply that exactly Q constellations are mapped to each set of M cyclic blocks. Achievement 1
[0097] The following describes the details of a bit interleaver (ie a parallel bit interleaver) that satisfies conditions 1 and 2 given above. In the following description, the processing and the units for carrying out such processing are labeled with the same reference numbers where applicable.
[0098] In this document, each group of M cyclic blocks and each group of Q words of the constellation is referred to as a section (or as an interleaver section).
[0099] Figs. 19 and 20 are block diagrams respectively illustrating the mapping function of a bit interleaver that satisfies Conditions 1 and 2, and corresponding to the aforementioned parameters (i.e., Q = 8, M = 4, N = 12), and a sample setting for such bit interleaving.
[00100] In Figs. 19 and 20, the LDPC QC codewords are composed of N = 12 cyclic blocks, each in turn composed of Q = 8 bits. Each of the 24 words of the constellation is made up of M = 4 bits. Each constellation word indicates one of 2M = 16 constellation points. The bit interleaver is divided into N/M = 3 sections. The 24 words of the constellation are each associated with one of the three sections.
[00101] A bit interleaver 2000 includes a bit changer 2010, which in turn includes N/M (= 3) section changers 2021, 2022, and 2023, each operating independently. However, rather than providing three section exchangers, a single section exchanger may, for example, be provided in order to carry out the section permutation processes described below, changing between them with time.
[00102] The section exchangers (2021, 2022, and 2023) each independently perform a section permutation on the 32 bits that make up each of the 4 cyclic blocks, such that one bit from all four cyclic blocks (ie, QB1 to QB4, QB5 through QB8, and QB9 through QB12) is mapped to each group of eight words in the constellation (ie, C1 through C8, C9 through C16, and C17 through C24).
[00103] Conditions 1 and 2, described above, ensure that the bit interleaver is divisible into N/M parallel sections. Section permutations applied to parallel sections may all apply the same permutation rules, they may each apply different permutation rules, or they may involve a subset of the sections that apply identical application rules while others differ.
[00104] For example, section exchangers can map the Q bits of a cyclic block (which each have the same importance in LDPC decoding) to bits having the same bit index (ie, having the same robustness level) in the words of the Q constellation. For each cyclic block, the Q bits can be in sequential order or in permuted order. The latter case is described with reference to Figs. 21A and 21B, while the first case is described with reference to Figs. 22A and 22B.
[00105] Fig. 21A structurally illustrates the section exchanger of Fig. 20.
[00106] Section exchanger 2101 includes intracyclic block exchangers 2111 to 2114, and a column-row exchanger 2131. Preferably than providing four intracyclic block exchangers, for example, a single intracyclic block exchanger may be provided, and performs four intracyclic block permutation processes, described later, interleaving between them over time.
[00107] The intracyclic block exchangers (2111-2114) each perform an intracyclic block permutation in the Q-bit (8-bit) cyclic blocks (QB1-QB4). The intracyclic block permutations applied to the cyclic blocks in each section may all apply the same permutation rules, they may each apply different permutation rules, or they may involve a subset of the sections that apply identical permutation rules while others differ.
[00108] The column-row exchanger 2131 performs a column-row permutation on each group of MxQ (= 32) bits. Specifically, column-row exchanger 2131 writes the MxQ bits per row into an MxQ (8x4) matrix, then reads the MxQ bits per column from it, thereby applying column-row permutation. The column-row permutation applied by the column-row exchanger 2131 resembles the permutation applied to the 12x1350 matrix shown in Figs. 9A and 9B, where Q columns and M rows are used, the writing process is similar to the column, and the reading process is similar to the row.
[00109] Fig. 21B is a structural representation of the section exchanger shown in Fig. 21A. In Fig. 21B, the constellation words of M = 4 bits are each denoted b1 through b4.
[00110] However, a variation in which the intracyclic block permutation process is not part of the section permutation process is also plausible.
[00111] For example, a section permutation implemented without performing the intracyclic block permutation and a mapping structure by the section changer are shown in Figs. 22A and 22B. The 2201 section exchanger includes a 2131 column-row exchanger, and performs a single column-row permutation. In Fig. 22B, the constellation words of M = 4 bits are each denoted b1 through b4.
[00112] The section permutation described in Figs. 21A, 21B, 22A and 22B, can be applied to cyclic blocks QB5-QB8 and QB9-QB12.
[00113] Advantageously, an additional cyclic block permutation can be applied to cyclic N blocks before the bit interleaver performs the section permutation. Fig. 23 is a structural diagram of the additional cyclic block permutation applied by the bit interleaver. In this context, cyclic block permutation plays a role similar to that permutation performed by the bit-to-cell demultiplier in the DVB-T2 standard.
[00114] The bit interleaver 2300 shown in Fig. 23 includes a cyclic block changer 2310 and a bit changer 2010 (which, in turn, includes section exchangers 2021-2023).
[00115] Cyclic block exchanger 2310 performs cyclic block permutations 2311-2318 in cyclic blocks QB1-QB12. Here, the permutations of cyclic blocks 2311-2318 all follow the same permutation rules.
[00116] Cyclic block permutation performed on Ncyclic blocks is particularly advantageous in enabling optimized mapping of LDPC codeword bits into constellation bits, resulting in optimized performance.
[00117] Fig. 24 is a schematic block diagram of the bit interleaver 2300 shown in Fig. 23. The bit interleaver 2400 shown in Fig. 24 includes three stages, A, B, and C. Stage A: (inter ) cyclic block permutation Stage B: intracyclic block permutation Stage C: column-row permutation
[00118] Cyclic block (inter) permutation is applied to Ncyclic blocks that make up the codeword, intracyclic block permutation is applied to Q bits of the given cyclic block, and column-row permutation is applied to M sections x Q.
[00119] The bit interleaver 2400 shown in Fig. 24 includes the cyclic block changer 2310 and the bit changer 2010 (which in turn include the section exchangers 2101-2103). The 2101 section exchanger (2102, 2013) includes the 2111-2114 intracyclic block exchangers (2115-2118, 2119-2122) and the 2131 column-to-row exchanger (2132, 2133).
[00120] In bit interleaver 2400, (inter)cyclic block permutation is performed by cyclic block exchanger 2310 (stage A), intracyclic block permutation is performed by intracyclic block exchangers 2111-2122 (stage B), and column-row permutation is performed by column-row exchangers 2131-2133 (stage C).
[00121] Intracyclic block exchangers 2111-2122 can be removed from the bit interleaver 2400 shown in Fig. 24 such that the bit interleaver is configured not to perform intracyclic block permutation. Also, bit interleaver 2400 may perform (inter)cyclic block permutation before intracyclic block permutation preferably than after intracyclic block permutation, or may perform (inter)cyclic block permutation before and after intracyclic block permutation intracyclic block.
[00122] Intracyclic block exchangers can have similar structures. This is advantageous in that intracyclic block exchangers are thus implementable using identical resources (eg hardware blocks). Alternatively, intracyclic block permutations can consist of cyclic changes, which allow efficient hardware implementation using barrel changers. An implementation using barrel changers in the LDPC decoder is also possible.
[00123] The following describes a transmitter that includes the bit interleaver that performs a bit interleaving process that satisfies Conditions 1 and 2, with reference to Fig. 25.
[00124] Fig. 25 is a block diagram of a transmitter belonging to another Embodiment of the present disclosure. As shown in Fig. 25, a transmitter 2500 includes a BICM encoder (which, in turn, includes an LDPC encoder 2510, a bit interleaving 2520, and a constellation mapper 2530), and a modulator 2540.
[00125] LDPC encoder 2510 encodes block input into codewords using LDPC QC codes, and then transmits the codewords to bit interleaver 2520.
[00126] The bit interleaver 2520 receives the codeword in QC-LDPC code from the LDPC encoder 2510. The codeword is composed of N = 12 cyclic blocks, each cyclic block including Q = 8 bits. Bit interleaver 2520 performs interleaving on the codeword bits so as to swap bits of each codeword. Bit interleaver 2520 divides the interleaved codeword into a plurality of constellation words, each composed of M = 4 bits, and indicating one of 2M = 16 constellation points, then outputs the constellation words to the constellation mapper. constellation 2530. A bit interleaver 2520 can apply the bit interleaving process discussed with reference to Figs. 19 to 22A and 22B, or may apply a variant bit permutation process. Also, bit interleaver 2520 can apply an additional cyclic block permutation process, such as the process discussed with reference to Figs. 23 and 24, or a variation thereof.
[00127] The constellation mapper 2530 receives the constellation words from the bit interleaver 2520, and performs constellation mapping on the constellation words thus received.
[00128] The 2740 modulator generates a transmission signal using orthogonal frequency division multiplexing (hereinafter, OFDM), or similar.
[00129] The following describes a BICM encoder that includes the bit interleaver that performs a bit interleaving process that satisfies Conditions 1 and 2, with reference to Fig. 26.
[00130] Fig. 26 is a block diagram of an example of BICM encoder belonging to another Embodiment of the disclosure. In Fig. 26, the BICM encoder 2600 corresponds to the parameters given above (ie Q = 8, N = 12, M = 4).
[00131] The BICM encoder 2600 shown in Fig. 26 includes a main memory 2601, an LDPC controller 2611, a rotator 2612, a group verification node processor 2613, a derotator 2614, a counter of QB 2631, table A 2632, B interleaver 2633, a register group 2634, C interleaver 2635, and a mapper group 2651.
[00132] In Fig. 26, given that Q = 8, main memory 2601 reads eight bits at a time, verification node processor group 2613 includes eight verification node processors, and mapper group 2651 includes eight mappers . Also, given that M = 4, register group 2634 includes four registers.
[00133] Main memory 2601 receives a bit stream for transmission from, for example, the (not diagramed) input processor, and stores the received bit stream.
The LDPC controller 2611 sends a read address to main memory 2601. Main memory 2601 consequently sends the bit sequence, eight bits at a time start with the drive bit, to rotator 2612. Rotator 2612 is controlled by the LDPC controller 2611 to perform a predetermined number of cyclical changes in the eight bits supplied to it by main memory 2601, and then output the cyclically changed eight bits to the verifying node processors of the verifying node processor group 2613, one bit at a time, the bits and check node processors being in a one-to-one correspondence. Each check node processor of the check node processor group 2613 is controlled by the LDPC controller 2611 to perform check node processing on each bit input thereof, then output the results to the de-rotator 2614. The derotator 2614 is controlled by LDPC controller 2611 to perform a predetermined number of cyclic changes in the eight bits received from the verification node processor group 2613 so as to cancel the cyclic change applied by rotator 2612, and then outputs the eight bits changed to main memory 2601. LDPC controller 2611 issues a write address to main memory 2601. Main memory 2601 consequently stores the eight bits supplied therefrom by de-rotator 2614. LDPC controller 2611, rotator 2612, the verification node processor group 2613, and the de-rotator 2614 make up the BICM encoder in the LDPC encoder 2510 shown in Fig. 25.
[00135] The counter of QB 2631 counts from 0 to 11, and outputs the counter value to table A 2632. The counting operation of the counter of QB 2631 is defined in consideration of N = 12.
[00136] Table A 2632 is a simple linearization table in which cyclic block permutation rules are stored. That is, table A 2632 stores N = 12 pieces of cyclic block read order information (information associating a different cyclic block with each of the 12 counter values from the counter of QB 2631). Table A 2632 issues a read address to main memory 2601 such that bits of a cyclic block (i.e., Q = 8 bits) corresponding to the counter value supplied by the counter of QB 2631 are supplied from main memory 2601 to interleaver B 2633. Thereby, main memory 2601 outputs the bits of a cyclic block corresponding to the counter value of counter of QB 2631 to interleaver B 2633. Processing using table A 2632 is performed as cyclic block permutation process (stage A).
[00137] Interleaver B 2633 performs a predetermined number of cyclic changes in the bits of the cyclic block supplied by main memory 2601, and outputs the results to a first level register of group register 2634. Processing by interleaver B 2633 is performed as the intracyclic block permutation process (stage B). Each register in register group 2634 stores a cyclic block of bits with matching regulation of reception of a control pulse, and outputs the cyclic block of bits before receiving the next control pulse.
[00138] When the counter of QB 2631 performs the aforementioned process for counter values 0 to 3, the bits of four cyclic blocks (ie 32 bits) are sent to the 2635 C interleaver. At this time, the 2635 C interleaver interleaves the bits of the four cyclic block inputs thereof, and the mappers of mapper group 2651 output a bit constellation word (ie, M = 4 bits). Through the interleaving process, four bits, that is, one from each of the four registers in register group 2634, is supplied to each mapper. This processing by the 2635 C collator is performed like the column row permutation process (stage C).
[00139] QB counter 2631, table A 2632, interleaver B 2633, group register 2634, and interleaver C 2635, make up bit interleaver 2520 of the BICM encoder shown in Fig. 25.
[00140] The mapper group 2651 mappers each map four supplied bits of these from the 2635 C interleaver to a constellation, then output the results. The mapper group 2651 makes up the constellation mapper 2530 of the BICM encoder shown in Fig. 25.
[00141] For each codeword, the above-described set of processes is applied three times, once each for counter values 0-3, 4-7, and 8-11 of the counter of QB 2631.
[00142] The Embodiment depicted in Fig. 26 includes Q mappers that operate in parallel. However, the mappers are also feasible as a BICM encoder in order to decrease or increase the parallelism. For example, the number of parallel interleaver sections in the bit interleaver, i.e. the N/M quotient, can obviously be increased in order to easily enhance parallelism. Such methods enable parallelism to be optimized by parallelization of QxN/M mappers. Implementing such parallelism without problems in the bit interleaver is beneficial.
[00143] The following describes a receiver that receives signals from a transmitter that includes the bit interleaver that performs a bit interleaving process that satisfies Conditions 1 and 2, with reference to Fig. 27.
[00144] Fig. 27 is a block diagram of an example receiver including a non-interactive BICM decoder belonging to another Embodiment of the disclosure. The receiver performs transmitter operations in reverse.
[00145] The receiver 2700 shown in Fig. 27 includes a demodulator 2710 and a non-interactive BICM decoder (which, in turn, includes a constellation demapper 2720, a bit deinterleaver 2730, and an LDPC decoder 2740).
[00146] The demodulator 2710 performs a demodulation process through OFDM, for example, and outputs the demodulated results.
The constellation mapper 2720 of the non-interactive BICM decoder generates a smooth bit sequence by applying a demapping process to the input from the demodulator 2710, and outputs the thus generated smooth bit sequence to the constellation mapper 2730 Smooth bits are a measure of the probability that a given bit is either a zero-bit or a one-bit. Typically, smooth bits are represented as log probability ratios (hereafter LLRs), defined as follows. LLR(b) = ln [(b = 0)/p(b = 1)] where p(b = 0) indicates the probability of the given bit b being a zero-bit, and p(b = 1) represents the probability of the given bit b being a one-bit. Of course, p(b = 0) + p(b = 1) = 1.
[00148] The bit deinterleaver 2730 performs an interleaving process (i.e., a bit deinterleaving process) on the smooth bit sequence emitted from the constellation demapper 2720 so as to cancel the bit interleaving process applied to the sequence bit by bit interleaver 2730 in the transmitter illustrated in Fig. 25.
[00149] The LDPC decoder 2740 receives the smooth bit sequence deinterleaved by the bit deinterleaver 2730, and performs an LDPC decoding process using the thus received smooth bit sequence.
[00150] An improved technique that offers significant performance gains is interactive BICM decoding. Fig. 28 illustrates an interactive BICM decoder.
[00151] Fig. 28 is a block diagram of an example receiver including an interactive BICM decoder belonging to another Embodiment of the disclosure. The receiver performs transmitter operations in reverse.
[00152] As shown in Fig. 28, a receiver 2800 includes demodulator 2710 and an interactive BICM decoder (which in turn includes constellation decoder 2720, bit deinterleaver 2730, LDPC decoder 2740, a subtractor 2760, and a bit interleaver 2750).
[00153] The receiver 2800 of Fig. 28 has the constellation demapper 2720 which performs a constellation demapping process, the bit deinterleaver 2730 which performs a bit deinterleaving process, and the LDPC decoder 2740 which performs a process of LDPC decoding.
[00154] After one or more iterations of LDPC decoding, extrinsic information, obtained by subtractor 2760 which subtracts input to LDPC decoder 2740 from output of LDPC decoder 2740, is output to bit interleaver 2750. bit 2750 performs an interleaving process on the extrinsic information using the same interleaving rules as those applied to the bit sequence by the transmitter bit interleaver depicted in Fig. 25. Bit interleaver 2750 then feeds back an interleaved extrinsic information to the demapper Constellation Mapper 2720. Constellation Demapper 2720 uses the extrinsic information thus fed back as a-priori information to compute safer LLR values. Bit deinterleaver 2730 then performs an interleaving process on the newly computed LLR values (i.e., a bit deinterleaving process) in order to cancel the bit interleaving process applied to the bit stream by the bit interleaver. bit in the transmitter depicted in Fig. 25 and restores the original order of the bit sequence. The LDPC decoder 2740 uses the LLR values in de-interleaved mode in the LDPC decoding process.
[00155] As shown in Fig. 28, an interactive decoding loop is composed of four elements, namely, constellation demapper 2720, bit deinterleaver 2730, LDPC decoder 2740, and bit interleaver 2750. Bit deinterleaver 2730 and bit interleaver 2750 have beneficially very low latency, ideally zero, and low complexity. This results in a more efficient receiver implementation. Bit deinterleaver 2730 and bit interleaver 2750 described above satisfy both of these conditions.
[00156] Fig. 29 illustrates an interactive BICM decoder that performs a very efficient parallel implementation.
[00157] Fig. 29 is a block diagram of an example BICM decoder belonging to another Embodiment of the disclosure. In Fig. 29, the BICM decoder 2900 corresponds to the parameters given above (ie Q = 8, N = 12, M = 4).
[00158] As shown, the BICM decoder 2900 includes a main LLR memory 2901, a buffer LLR memory 2902, an LDPC controller 2911, a rotator 2912, a verification node processor group 2913, a de- rotator 2914, a counter of QB 2931, table A 2932, a subtractor group 2933, interleaver B 2934, register group 2935, C interleaver 2936, a mapper group 2937, C deinterleaver 2938, register group 2939, deinterleaver B 2940, and a retarder 2941.
[00159] In Fig. 29, given that Q = 8, main LLR memory 2901 and buffer LLR memory 2902 each read eight LLR values at a time, verification node processor group 2913 includes eight processors of verification node, and the demapper group 2951 includes eight demappers. Also, given that M = 4, register groups 2935 and 2972 each include four registers.
[00160] The demappers in the demapper group 2937 each perform a demapping process on the output of a demodulator (not diagramed), then output the LLR values thus obtained to the deinterleaver C 2938. The demapper group 2937 makes up the constellation demapper 2720 of the interactive BICM decoder shown in Fig. 28.
[00161] The C deinterleaver 2938 applies a deinterleaving process to the LLR values (that is, a new interleaving process that cancels the interleaving process applied by the transmitter during stage C), then outputs the deinterleaved LLR values to the register group register 2939. Each register stores a cyclic block of LLR values (ie, eight LLR values). In register group 2939, the cyclic block of LLR values stored by each register is sequentially outputted at a later level, such that the contents of each register are sequentially updated. Deinterleaver B 2940 applies a deinterleaving process to the cyclic block of (eight) LLR values (ie, a new interleaving process that cancels the interleaving process applied by the transmitter during stage B), then writes the results to main LLR memory 2901 and buffer LLR memory 2902 according to table A 2932 (discussed later). An interleaving process that cancels the interleaving process applied by the transmitter during stage A is achieved by this writing to main LLR memory 2901 and buffer LLR memory 2902 according to the contents of Table A 2932.
Thus, the main LLR memory 2901 stores the post-deinterleaving LLR values, and is also used by the LDPC decoder (i.e., LDPC controller 2911, rotator 2912, node processor group checkpoint 2913, and the derotator 2914). The LDPC decoding process is an iterative process involving one or more interactions. At each LDPC decoding iteration, the LLR values in LLR main memory 2901 are updated. In order to compute the extrinsic information needed for interactive BICM decoding, old LLR values are saved in LLR memory of buffer 2902.
[00163] The following describes the operations of the LDPC decoder.
[00164] The LDPC controller 2911 issues the read address to the main LLR memory 2901 according to the parity check matrix of the LDPC codes. Thereby, LLR main memory 2901 sequentially outputs a cyclic block of LLR values to rotator 2912. Rotator 2912 is controlled by LDPC controller 2911 to perform a predetermined number of cyclical changes in the cyclic block of LLR values sequentially supplied by main LLR memory 2901 then outputs the thus changed LLR values to verifying node processors of verifying node processor group 2913 at a time. The verifying node processors of the verifying node processor group 2913 are controlled by the LDPC controller 2911 to perform a verification node process on the sequence of LLR values sequentially issued therefrom. Thereafter, the verifying node processors of the verifying node processor group 2913 are controlled by the LDPC controller 2911 to sequentially output the resulting LLR values from the verifying node process. The de-rotator 2914 is controlled by the LDPC controller 2911 to perform a predetermined number of cyclic changes that cancel the cyclic change applied to the cyclic block sequentially received from the verifying node processor group 2913 by rotator 2912, then sequentially sends the changed results to main LLR memory 2901. The LDPC controller 2911 sends the write address to main LLR memory 2901 according to the parity check matrix of the LDPC codes. Thereby, the main LLR memory 2901 stores the cyclic block of the results sequentially supplied therefrom by the de-rotator 2914. The LDPC controller 2911 repeatedly performs the above-described processing according to the parity check matrix of the LDPC codes.
[00165] After a predetermined number of LDPC interactions, a BICM interaction is performed. LDPC and BICM interactions are also respectively referred to as internal and external iterations. These two types of interactives may also overlap in some implementations. This enables the convergence speed to be increased. The BICM and LDPC decoding process are well known in the field, and the details of these are thereby omitted.
[00166] The counter of QB 2931 counts from 0 to 11 and outputs the counter value to table A 2932. The counting operation of the counter of QB 2931 is defined in consideration of N = 12.
[00167] Table A 2932 is a simple lookup table in which cyclic block permutation rules are stored. That is, table A 2932 stores N = 12 pieces of cyclic block read (and write) order information (i.e., with information associating a different cyclic block with each of the 12 counter values from the counter of QB 2631). Table A 2932 outputs the read address to main LLR memory 2901 and buffer LLR memory 2902 such that a cyclic block of LLR values corresponding to the counter value supplied by the counter of QB 2931 is supplied to the subtractor group 2933 by LLR main memory 2901 and LLR buffer memory 2902. Thereby, LLR main memory 2901 and LLR buffer memory 2902 each output a cyclic block of LLR values corresponding to the counter value of the counter QB 2931 to subtractor 2933. Delay 2941 produces a delay setting such that the position of reading the LLR value from the main LLR memory 2901 and the LLR buffer memory 2902 matches the writing position of the same values from LLR to main LLR memory 2901 and buffer LLR memory 2902. Processing using table A 2932 is performed as cyclic block permutation process (stage A).
The subtractor 2933 in the subtractor group subtracts the output of buffer LLR memory 2902 from the output of main LLR memory 2901, then outputs the extrinsic information for a cyclic block thus obtained (i.e. , eight pieces of extrinsic information) for interleaver B 2934.
[00169] Interleaver B 2634 performs a predetermined number of cyclic changes in the pieces of extrinsic information for one of the cyclic blocks supplied by subtractor 2933, and outputs the results to a first level register of group register 2935. Processing performed by interleaver B 2934 corresponds to intracyclic block permutation (stage B). Each register in register group 2935 stores eight bits with regulation match of reception of a control pulse, and outputs the eight bits before receiving the next control pulse.
[00170] When the counter of QB 2631 performs the aforementioned process for counter values 0 to 3, the extrinsic information for four cyclic blocks (ie 32 pieces of extrinsic information) is admitted to the 2936 C interleaver. C interleaver 2936 performs the interleaving process on the extrinsic information input from this to four cyclic blocks, then admits an extrinsic information constellation word (ie, M = 4 extrinsic information pieces) to each demapper of the demapper group 2937. Through the interleaving process, the four pieces of extrinsic information are supplied to the mapper group 2951 from the four registers in the register group 2935, one at a time. This processing by the 2936 C collator is performed like the column row permutation process (stage C).
[00171] QB counter 2931, table A 2932, interleaver B 2934, group register 2935, and interleaver C 2936 make up bit interleaver 2750 of the BICM decoder shown in Fig. 28.
[00172] The demapper group 2937 uses the four pieces of extrinsic information supplied by the C interleaver 2936 as a-priori information to perform a demapping process, then admits the resulting LLR values to the C deinterleaver 2938.
[00173] The C deinterleaver 2938 applies a deinterleaving process to the LLR values (i.e., a new interleaving process that cancels the interleaving process applied by the transmitter during stage C), then outputs the deinterleaved LLR values to the register group register 2939. Each register stores a cyclic block of LLR values (ie, eight LLR values). In register group 2939, the cyclic block of LLR values stored by each register is sequentially admitted to a later level such that the contents of each register are sequentially updated. Deinterleaver B 2940 applies a deinterleaving process to the cyclic block of (eight) LLR values (ie, a new interleaving process that cancels the interleaving process applied by the transmitter during stage B), then writes the results to LLR main memory 2901 and LLR buffer memory 2902. LLR main memory 2901 and LLR buffer memory 2902 receive table A write address 2932, via delay 2941, then store a cyclic block of LLR values (i.e., eight LLR values) received from deinterleaver 2940 according to the received write address. An interleaving process that cancels the interleaving process applied by the transmitter during stage A (ie, a de-interleaving process) is achieved by this writing in accordance with the contents of table A 2932.
[00174] For each codeword, the above-described set of processes is applied three times, once each for counter values 0-3, 4-7, and 8-11 of the counter of QB 2931.
[00175] The QB counter 2931, table A 2932, deinterleaver B 26938, group register 2939, and interleaver C 2940 make up bit interleaver 2730 of the BICM decoder shown in Fig. 28.
[00176] Interleaver B 2934 and deinterleaver B 2940 are reconfigurable. This requires a certain hardware cost, but this cost is minimized by careful design. C-interleaver 2936 and de-interleaver 2938 implement column-row permutation. This permutation is uniform for a predetermined constellation size. Thereby, the cost of implementation is reduced.
[00177] The Embodiment depicted in Fig. 29 includes Q demappers that operate in parallel. However, mappers are also feasible as an interactive BICM decoder by decreasing or increasing parallelism. For example, the number of parallel interleaver sections in the bit interleaver, i.e. the N/M quotient, can obviously be increased in order to easily enhance parallelism. Such methods enable the parallelism to be optimized by the parallelization of QxN/M mappers. The above described bit interleaver has the merit of being implementable with such parallelism without problem. Additional Experimental Discoveries
[00178] Interleavers satisfying Conditions 1 and 2 given above (ie, parallel interleavers) assume that the number of bits per constellation word M is a divisor of the number of cyclic blocks N. However, M is typically not a divisor of N. For example, the 16K LDPC codes used in the DVB-T2 standard have N = 45 cyclic blocks per 16K LDPC codeword. When M is not a divisor of N, mapping square constellations, such as QAM constellations where M is constant, is not evident.
[00179] Thus, a particular solution is proposed that involves deleting one or more of the cyclic N blocks and implementing the interleaver discussed in Embodiment 1 (ie, the parallel interleaver), above, only for the remaining cyclic blocks.
[00180] In other words, N‘ cyclic blocks are selected from among the N cyclic blocks such that N‘ is a multiple of the number of bits per words of the constellation M in the bit interleaver. The bit interleaver divides the selected N ‘ cyclic blocks into N7 M sections such that each section includes M cyclic blocks, then performs a section permutation on each section. Bits of the excluded (ie, not selected) cyclic block may or may not be interleaved.
[00181] For example, the excluded cyclic blocks can be the cyclic blocks having a variable node of lower weight. For the example RA QC LDPC codes (see Fig. 5), the excluded cyclic blocks are the cyclic block of the parity section (having a variable node weight of two), and are beneficially the last or more cyclic blocks of the word of code.
[00182] Fig. 30 illustrates a cyclic block subject to and a cyclic block excluded from (i.e., an excluded block) of the interleaving process described above (i.e., Embodiment 1). In Fig. 30, the code is 16K LDPC code that conforms to the DVB-T2 standard, and the constellation is 16 constellations of QAM. As shown, 44 of the cyclic blocks are interleaved (ie, blocks 1 to 44), and cyclic block 45, in the last row, is the one cyclic block not subject to interleaving (ie, the excluded block). The four blackened squares represent the four bits of the first constellation.
[00183] In general, the number of interleaver sections (each composed of M cyclic blocks) is given by base (N/M), and the number of cyclic blocks excluded is given by rem (N, M). Here, base (N/M) is a function that returns the largest integer less than or equal to N/M, and rem (N, M) is a function that returns the remainder of the division N by M.
[00184] Table 2 indicates the number of sections and the number of cyclic blocks excluded for various constellation sizes (ie number of bits per constellation M), for DVB-T2 standard 16K LDPC codes (where N = 45 cyclic blocks are used). Table 2

[00185] According to the interleaving method that satisfies Conditions 1 and 2 as described above, each constellation word is mapped into M cyclic blocks. However, for large constellations (ie, constellations having many constellation points), an merge method that satisfies Conditions 1 and 2 requires an extremely large amount of delay registers (see the implementation described with reference to Figs. 26 to 29 ). Using an extremely large amount of loggers leads to an increase in circuit area and electrical power consumption. In addition, reducing the number of cyclic blocks to which each constellation word is mapped is beneficial in increasing the overlap between external interactions (BICM) and internal interactions (LDPC), in turn reducing BICM decoding latency total.
[00186] By mapping two or more bits of each constellation word into the same cyclic block, the number of cyclic blocks into which each constellation word is mapped is reduced. The number of constellation word bits mapped to the same cyclic block is called the doubling factor, and is denoted F. For example, when F = 2 for 16 QAM constellations, each constellation word is mapped to the four cyclic blocks preferably from what two. The only restriction is that the folding factor F (which is an integer greater than one) must be a divisor of both M and Q. When F = 1, no doubling is involved, ie the situation corresponds to Embodiment 1, described above.
[00187] A complex QAM constellation symbol is decomposed into two identical real PAM symbols. In this way, the M bits of the QAM constellation are split into two identical real PAM symbols, which are sets of M/2 bits. The bits of each constellation word are then mapped to the same M/2 number of cyclic blocks. A doubling factor of F = 2 is advantageous for QAM constellation.
[00188] For complex constellations that cannot be decomposed into real numbers, such as 8-PSK (Phase Shift Keying), 16-APSK (Amplitude Phase Shift Keying), 32-APSK, and so on, in DVB-S2 standard, the folding method is not easily applicable. However, the folding method is usable when F is a divisor of M. Unfortunately, this precludes any guarantee that each cyclic block has only bits of the same robustness level from the constellations mapped to these.
[00189] Beneficially, the folding method is, for example, applied, such that only bits of the same robustness level in the constellations are mapped to cyclic blocks.
[00190] Folding is also beneficial in reducing the number of cyclic blocks excluded, or even eliminating the need to exclude any cyclic blocks. As described above, a certain number of cyclic blocks that make up the codeword must be excluded when the interleaver described in Embodiment 1 (i.e., a parallel interleaver) is used.
[00191] Without folding (ie when F = 1), the number of groups of M cyclic blocks (ie the number of sections) is base N/M), and the number of excluded cyclic blocks is rem (N , M). With doubling, the number of groups of M/F cyclic blocks is base (N/(M/F)), and the number of cyclic blocks excluded is rem (N, M/F). Specific examples of these numbers are given in Table 3, for the LDPC codes used in the DVB-T2 standard. Table 3


[00192] The inventor has found that in order to perform folding (where F is an integer equal to or greater than two), Conditions 1 and 2 must be modified in Conditions 1A and 2A as given below. Condition 1A
[00193] The M bits of each constellation word are each mapped to one of M/F cyclic blocks different from the LDPC codeword. This is equivalent to mapping a bit of M/F cyclic blocks other than the LDPC codeword to a constellation word. This is schematically illustrated in Fig. 31A. Condition 2A
[00194] All constellation words mapped to M/F cyclic blocks are only mapped to that particular cyclic block. This is equivalent to mapping all the MxQ/Fbits of the different M/F cyclic blocks each composed of Q bits to exactly Q/F constellations. This is schematically illustrated in Fig. 31B. When F = 1, no folding is involved, and thus Conditions 1A and 2A are equivalent to Conditions 1 and 2. Achievement 2
[00195] The following describes the details of a bit interleaver (ie, a parallel bit interleaver) that satisfies conditions 1A and 2A, given above. In the following description, the processing and the units that perform such processing are labeled with the same reference numbers where applicable.
[00196] In this document, each group of M/F cyclic blocks or Q/F constellation words is referred to as a folding section (or as a folding interleaver section). When F = 1 (ie, no folding), the folding interleaver sections match the interleaver sections, and the bit interleaver is set identically to the bit interleaver of Embodiment 1.
[00197] Doubling occurs when Faith is an integer greater than one. Embodiment 2 describes an example of folding where F = 2.
[00198] Fig. 32 is a block diagram illustrating the configuration of a bit interleaver that satisfies Conditions 1A and 2A, when Q = 8, M = 4, N = 12, and F = 2, as another Embodiment of revelation.
[00199] In Fig. 32, the LDPC QC codewords are composed of N = 12 cyclic blocks QB1 to QB12, each, in turn, composed of Q = 8 bits. Each of the 24 words of the constellation is made up of M = 4 bits. Each constellation word indicates one of 2M = 16 constellation points. The bit interleaver is divided into F x N/M = 6 folding sections, and 24 constellation words are each associated with one of the FxN/M = 6 folding sections.
[00200] Bit interleaver 2000A includes a bit changer 2010A. The 2010A bit exchanger includes FxN/M = 6 2021A-2026A bending section exchangers, each operating independently. Rather than providing six bending section exchangers, a single bending section exchanger can be provided in order to carry out six (later described) bending section permutation processes, these changing with time.
[00201] The bending section exchangers (2021A, 2022A, 2023A, 2024A, 2025A, 2026A) are independent, and each applies a bending section permutation process to the 16 bits of two cyclic blocks such that F = 2 bits each of M/F = 2 cyclic blocks (QB1-QB2, QB3-QB4, QB5-QB6, QB7-QB8, QB9-QB10, QB11-QB12) are mapped to a given set of four constellation words (C1-C4 , C5-C8, C9-C12, C13-C16, C17-C20, C21-C24).
[00202] Conditions 1A and 2A, described above, simply ensure that the bit interleaver is divisible into FxN/M parallel folding sections. The bending section permutations applied to parallel bending sections may all apply the same permutation rules, may each apply different permutation rules, or may involve a subset of the sections that apply identical permutation rules while others differ.
[00203] For example, folding section exchangers can map Q bits of each cyclic block to bits of Q/F constellation words having the same robustness level. This is illustrated in Figs. 33A, 33B, 34A, and 34B for a situation where Q = 8 and M = 4.
[00204] Fig. 34A is a block diagram of a (folding) section exchanger when F = 1 (ie, no folding), and is similar to Fig. 22A.
[00205] Fig. 34B is a block diagram of the two bending section exchangers of Fig. 32 where F = 2 (ie with bending).
[00206] However, in the example of Fig. 34B, the constellations are 16 QAM constellations. Thus, the constellation bits have two levels of robustness. Bits b1 and b3 have the same robustness level, and bits b2 and b4 have the same robustness levels, the first robustness level being different from the last robustness level.
[00207] The 2201A (and 2202A) bending section exchangers each include a 2131A (or 2132A) column-row exchanger.
[00208] The column-row exchangers 2131A (and 2132A) each perform a row-to-column permutation process on QxM/F = 16 cyclic blocks QB1 and QB2 (or QB3 and QB4). To be exact, the column-row exchangers 2131A (and 2132A) write QxM/F = 16 bits per row into a matrix QxM/F (8x2), then read the 16 bits so written similar to the column to perform the process of row-to-column permutation. The column-row permutation applied by the column-row exchangers 2131A and 2132A resembles the permutation applied to the 12x1350 matrix shown in Figs. 9A and 9B, where Q columns and M/F rows are used, the writing process occurs similar to the row, and the reading process occurs similar to the column.
[00209] The folding with a folding factor of F reduces the number of cyclic blocks mapped into a single constellation word. In this way, the matrix used in column-row permutation is reduced in size from M rows to M/F rows.
[00210] Fig. 33A illustrates the mapping function performed by the (folding) section exchanger of Fig. 34A. Fig. 33B illustrates the mapping function performed by the two bending section exchangers of Fig. 34B. In Figs. 33A and 33B, each constellation word of M = 4 bits is denoted b1 to b4. The portions sketched in thicker lines represent the portions mapped to the C1 constellation.
[00211] As shown in Figs. 33A and 34A, the eight bits of a cyclic block (being of equal importance) are each mapped to bits of eight constellation words having the same bit index (i.e., having the same robustness level). Also, in Figs. 33B and 34B, the eight bits of a cyclic block (being of equal importance) are mapped to the bits of four constellation words having the same level of robustness.
[00212] The permutation of the folding section described in Fig. 34B can be applied to cyclic blocks QB5-QB6, QB7-QB8, QB9-QB10, and QB11-QB12.
[00213] The bending section exchangers of Figs. 34A and 34B may also include a subunit that performs intracyclic block permutation on cyclic block bits QB1 -QB4 prior to column-row permutation.
[00214] Advantageously, an additional cyclic block permutation can be applied to the N-cyclic blocks before the bit interleaver performs the folding section permutation. Fig. 35 is a structural diagram of the additional cyclic block permutation applied by the bit interleaver.
[00215] The bit interleaver 2300A shown in Fig. 35 includes the cyclic block exchanger 2310 and a bit exchanger 2010A (which, in turn, includes bending section exchangers 2021A-2026A).
[00216] Fig. 36 is a schematic block diagram of the bit interleaver 3500 shown in Fig. 23.
[00217] The 2400A bit interleaver shown in Fig. 36 includes the 2310 cyclic block exchanger and a 2200A bit exchanger (which, in turn, includes 2201A-2206A folding section exchangers).
[00218] The 2201A-2206A bending section exchangers each include a 2131A-2136A column-row exchanger. The 2133A-2136A bending section exchangers each perform substantially identical permutations with the 2131A-2132A column-to-row exchangers.
[00219] The bit interleaver shown in Figs. 35 and 36 may each include an additional subunit that performs an intracyclic block permutation on cyclic block bits QB1-QB12 before or after the cyclic block permutation.
[00220] The following describes a transmitter that includes the bit interleaver that performs a bit interleaving process that satisfies Conditions 1A and 2A, with reference to Fig. 37.
[00221] Fig. 37 is a block diagram of a transmitter belonging to another Embodiment of the present disclosure. The 2500A transmitter shown in Fig. 37 is configured similarly to the 2500 transmitter of Fig. 25, differing in that the 2520 bit interleaver is replaced with a 2520A bit interleaver.
Bit interleaver 2520A receives the codeword in the QC-LDPC code from the LDPC encoder 2510. The codeword is composed of N = 12 cyclic blocks, each cyclic block including Q = 8 bits. Bit interleaver 2520A performs interleaving on the codeword bits. Bit interleaver 2520A divides the interleaved codeword into a plurality of constellation words, each composed of M = 4 bits, and indicating one of 2M = 16 constellation points, then outputs the constellation words to the constellation mapper 2530. Bit interleaver 2520A can apply the bit interleaving process discussed with reference to Figs. 32 to 34, or can apply a variant bit permutation process (excluding cases where F = 1). Also, bit interleaver 2520A can apply an additional cyclic block permutation process (excluding cases where F = 1), such as the process discussed with reference to Figs. 35 and 36, or a variation thereof.
[00223] The following describes a receiver that receives signals from a transmitter that includes the bit interleaver that performs a bit interleaving process that satisfies Conditions 1A and 2A.
[00224] Fig. 38 is a block diagram of an example receiver including a non-interactive BICM decoder belonging to another Embodiment of the disclosure. The receiver performs transmitter operations in reverse. The receiver 2700A shown in Fig. 38 is configured similarly to the receiver 2700 of Fig. 27, differing in that the bit deinterleaver 2730 is replaced by a bit deinterleaver 2730A.
Bit deinterleaver 2730A performs an interleaving process on the smooth bit sequence outputted from the constellation demapper 2720 so as to cancel the bit interleaving process applied to the bit sequence by bit interleaver 2520A at transmitter 2500A.
[00226] Fig. 39 is a block diagram of an example receiver including a non-interactive BICM decoder belonging to another Embodiment of the disclosure. The receiver performs transmitter operations in reverse. The receiver 2800A shown in Fig. 39 is configured similarly to the receiver 2800 of Fig. 28, differing in that the bit deinterleaver 2730 and the bit interleaver 2750 are replaced by a bit deinterleaver 2730A and a bit deinterleaver 2750A.
[00227] The 2750A bit interleaver performs an interleaving process on the extrinsic information using the same interleaving rules as the interleaving process applied to the bit sequence by the 2520A bit interleaver at the 2500A transmitter.
[00228] From a hardware implementation perspective, folding is desirable where, for example, the bits of a constellation are thus located in a few LLR memory locations. Typically, the LLR memory in the decoder includes GxN addressable memory locations, each location being capable of storing Q/G LLR values. Here, G is an implementation parameter that is a divisor of Q and is hereafter referred to as memory granularity. The LLR memory locations in the decoder and the LLR values of the first constellation are shown in Fig. 40, where M = 4, F = 2, Q = 12, and G = 1-12.
[00229] The number of LLR values per memory location, i.e. the Q/G value, is necessarily a multiple of F. The LLR values of each constellation are thus stored in the same position in all memory locations. This ensures that the LLR values of any constellation word are stored in M/Fmemory locations. An example counter is given in Fig. 40 where G = 4, and 12/4 = 3 LLR values are stored in each memory location. The LLR values of the second and fifth words of the constellation are each stored in four memory locations rather than two memory locations.
[00230] In addition to single QAM constellations where folding with F = 2 is applicable, folding is even more useful when two or more constellation symbols are unitarily decoded. Joint decoding is necessary, for example, for maximum probability decoding of block codes (eg, spacetime codes, spacefrequency codes, and the like), and for constellation rotated in two or more dimensions.
[00231] In general, a block code encodes two or more input symbols (eg x1, ..., xK) into two or more output symbols (eg y1, ..., yL). Here, L is at least equal to K. Block codes are modeled on a generator matrix LxK. Here, the output signal vector Y is obtained as a result of multiplying the input signal vector X by the generator matrix G (ie Y = GX).
[00232] The elements of the input signal vector X and the output signal vector Y, as well as the elements of the generator matrix G, can be real or complex. Depending on the code type, the output signal vector Y can be transmitted in different time slots, or in different frequency slots, it can be transmitted over different antennas, or it can be transmitted using a variety of different time slots, slots frequency, and antennas.
[00233] At the receiver, maximum probability decoding is required in order to decode all elements of the input X signal vector. Examples of block codes for multiple input and multiple output systems (hereinafter, MIMO) include Alamouti codes , Golden codes, and spatial multiplexing.
[00234] When K symbols are encoded in the same block, a doubling factor of up to K is obviously usable. Additionally, provided the symbols are QAM symbols (including two divisible PAM symbols), then the doubling factor can be increased to 2K.
[00235] According to a further aspect of the present disclosure, when constellations of different sizes, i.e. hybrid constellations, are unicoded together, the two constellations have different robustness levels. Thus, for example, the cyclic block to which the bits of one constellation word are mapped is distinct from the cyclic block to which the bits of the other constellation word are mapped.
[00236] The following describes an example of a coded spatial multiplexing MIMO system using two transmit antennas. The complex signal before encoding is X = [x1 x2]. Here, x1 is a signal to which QPSK has been applied, and x2 is a signal to which 16-QAM has been applied. The complex signal after decoding is Y = [y1 y2]. Here, y1 and y2 are signals respectively transmitted by a first antenna and a second antenna. Y is obtained by multiplying X with a 2x2 generator matrix G (where the elements of G can be either real or complex) (ie Y = GX).
[00237] Fig. 41 illustrates an example of mapping with a doubling factor of F = 2 when multiplexing QPSK symbols with 16 QAM symbols into a single block code. Fig. 41 indicates only the first seven bits of the cyclic blocks. The two complex symbols x1 and x2 are configured as follows. x1 is a QPSK symbol having a real part b1 and an imaginary part b2. x2 is a 16-QAM symbol having real parts b3 and b4 and having imaginary parts b5 and b6.
[00238] The two symbols are unitly decoded by the receiver and thereby form a constellation block or generated block.
[00239] The total 6-bit constellation block has three robustness levels. Level 1: 1: QPSK bits b1 and b2 are mapped to QB1 Level 2: 16-QAM bits b3 and b5 are mapped to QB2 Level 3: 16-QAM bits b4 and b6 are mapped to QB3
[00240] When one of the constellations has M1 bits and the other constellation has M2 bits, the N cyclic groups are divided into one or more groups of M1 cyclic block and one or more groups of M2 cyclic blocks in order to carry out the interleaving process of bit. Achievement 3
[00241] The following describes an example of an interleaver that performs folding in a situation where N is not a multiple of M.
[00242] Fig. 42 illustrates a cyclic block subject to, and a cyclic block excluded from (i.e., an excluded block) the interleaving process where F = 2, described above. In Fig. 42, the code is 16K LDPC code that conforms to the DVB-T2 standard, and the constellation is 16 constellations of QAM. As shown, 44 of the cyclic blocks are interleaved (ie, blocks 1 to 44), and cyclic block 45, in the last row, is the one cyclic block not subject to interleaving (ie, the excluded block). The four blackened squares represent the four bits of the first constellation.
[00243] Fig. 43 is a schematic block diagram of a bit interleaver that performs doubling when N is not a multiple of M. For simplicity, the following values hold: N = 13, Q = 8, M = 4, and F = 2.
[00244] The number of folding sections is base (N/(M/F)) = 6, and the number of cyclic blocks excluded is rem (N, M/F) = 1.
[00245] Bit interleaver 2000B selects 13-1 = 12 cyclic blocks from among cyclic blocks QB1-QB13, such that the selected cyclic blocks QB1-QB12 satisfy conditions A1 and A2, and are subject to interleaving. Bit changer 2010A in bit interleaver 2000B performs the permutation process described with reference to Fig. 32 on the twelve selected cyclic blocks. Although cyclic block bits QB13 are here mapped to a constellation word without interleaving, interleaving can also be applied prior to mapping to the constellation word.
[00246] As an example of an interleaver not performing doubling when N is not a multiple of M, the bit changer 2010A shown in Fig. 43 can be replaced by the exchanger 2010 shown in Fig. 20. Supplement 1
[00247] The present disclosure is not limited to the Embodiments described above. Provided that the objects of the invention and accompanying objects are achieved, other variations are also possible, such as the following. (1) Embodiment 1 is described above using parameters N = 12, Q = 8, and M = 4. However, no limitations to parameters N, M, and Q are intended. Here, N can be any multiple of M. When N is two or more times M, the bit-interleaver processing is divisible into a plurality of sections. (2) In Embodiment 2, when folding is used, that is, when F is two or greater, the parameters given for the examples are N = 12, Q = 8, M = 4, and a folding factor of F = 2 However, no limitations on parameters N, M, Q, and F are intended. Here, F is the divisor of M and Q, and N is a multiple of M/F. (3) In Embodiment 2, when doubling is used, the value of F is given as two, which is the number of bits having the same level of robustness in 16 single QAM constellations. However, no limitations are intended. The value of F need not equal the number of bits having the same robustness level in a constellation, and may, in fact, be other than the number of bits having the same robustness level in a constellation. (4) In Embodiment 2, when doubling is used, the example describes a doubling factor of F = 2, and the QAM constellations being 16 QAM constellations. However, no limitations are intended. When F = 2, the QAM constellations can be other than 16 QAM constellations (for example, 64 QAM constellations, or 256 QAM constellations). (5) In the above-described Embodiments, the constellations are described as 16-QAM (ie, M = 4). However, constellations can be specified by other modulation methods such as QPSK and QAM, such as the circular constellations employed in the DVB-S2 standard, higher dimensional constellations, and so on. (6) The methods and devices discussed in the Embodiments above can be implemented as software or as hardware. No particular limitations are intended in this regard. Specifically, the above-described Embodiments can be implemented as a computer-readable medium having embodied computer-executable instructions therein that are adapted to enable a computer, a microprocessor, a microcontroller, and the like, to perform the above-described methods. Also, the Embodiments described above may be implemented as an Application-Specific Integrated Circuit (ASIC) or as a Field Programmable Gate Array (FPGA). Supplement 2
[00248] The bit interleaving method, bit interleaver, bit deinterleaving method, bit deinterleaver, and decoder of the present disclosure, and the effects of these, are described below.
[00249] In a first aspect of a bit interleaving method, a bit interleaving method for a communication system using quasi-cyclic low-density parity check codes comprises: a step of receiving and receiving a codeword of quasi-cyclic low-density parity check codes composed of N-cyclic blocks each including Q bits; a bit swapping step of applying a bit swapping process to the codeword so as to swap the bits in the codeword; and a step of dividing the codeword, after the bit permutation process, into a plurality of constellation words, each of the constellation words being composed of M bits, and indicating one of 2M constellation points in a predetermined constellation, in which before the bit permutation process, the codeword is divided into FxN/M folding sections, F being an integer greater than one, each of the folding sections including M/F of the cyclic blocks, and each of the constellation words being associated with one of the FxN/M folding sections, and in the bit permutation step, the bit permutation process is applied such that the M bits in each of the constellation words include F bits of each of the different M/F cyclic blocks in a given folding section associated with a given constellation word, and such that all bits in the given folding section are mapped to only Q/F of the constellation words associated with the given sectionof folding.
[00250] In another aspect, a first bit interleaver for a communication system using quasi-cyclic low density parity check codes comprises: a bit permutation unit receiving a codeword of the low parity check codes quasi-cyclic density composed of N-cyclic blocks each including Q bits, applying a bit permutation process to the codeword so as to swap bits in the codeword, and dividing the codeword, for output after the codeword permutation process. bit, in a plurality of constellation words, each of the constellation words being composed of M bits, and indicating one of 2M constellation points in a predetermined constellation, in which before the bit permutation process, the codeword is divided into FxN/M folding sections, F being an integer greater than one, each of the folding sections including M/F of the cyclic blocks, and each of the words of the const the link being associated with one of the FxN/M folding sections, and the bit permutation unit applies the bit permutation process such that the M bits in each of the constellation words include F bits of each of the M/F blocks different cyclics on a given folding section associated with a given constellation word, and such that all bits in the given folding section are mapped to only Q/F of the constellation words associated with the given folding section.
[00251] Consequently, reductions in circuit surface area and in electrical power consumption are achieved, in addition to enabling the realization of a bit interleaving process having high parallelism.
[00252] In a second aspect of the bit interleaving method, the bit permutation step includes a bending section permutation step of independently applying a bending section permutation process to each of the FxN/M bending sections so as to swap bits in each of the folding sections.
[00253] Also, in a second aspect of a bit interleaver, the bit permutation unit includes a bending section permutation unit independently applying a bending section permutation process to each of the FxN/M bending sections so as to swap bits in each of the folding sections.
[00254] Consequently, a plurality of bending section permutation processes is executable in parallel.
[00255] In a third aspect of the bit interleaving method, in the folding section permutation step, the folding section permutation process is performed such that the Q bits in a given cyclic block are each mapped to a bit of an identical level of robustness in the Q/F words of the constellation associated with one of the folding sections that correspond to the given cyclic block.
[00256] Also, in a third aspect of a bit interleaver, the folding section permutation unit applies the folding section permutation process such that the Q bits in a given cyclic block are each mapped to a bit of a identical robustness level in the Q/F constellation words associated with one of the folding sections corresponding to the given cyclic block.
[00257] Consequently, the codeword bits having the same importance are mapped to the constellation word bits having the same robustness level, allowing an equalization of importance and robustness level. For example, the codeword bit having the highest importance can be mapped to a constellation word bit having the highest robustness level. In such a case, high insurability is achieved in the reception time for the codeword bit having the highest importance, resulting in greater reception capability.
[00258] In a fourth aspect of the bit interleaving method, F is equal to a number of bits of an identical robustness level in one of the constellation words.
[00259] Also, in a fourth aspect of a bit interleaver, F is equal to a number of bits of an identical robustness level in one of the constellation words.
[00260] Consequently, an effective hardware implementation is realized.
[00261] In a fifth aspect of the bit interleaving method, F = 2, and the constellation words are QAM constellations.
[00262] Also, in a fifth aspect of a bit interleaver, F = 2, and the constellation words are QAM constellations.
[00263] Consequently, an effective hardware implementation is performed.
[00264] In a sixth aspect of the bit interleaving method, the folding section permutation step includes a column row permutation step of applying a column row permutation process to the M/FxQbits in each of the folding sections in order to swap the M/FxQbits.
[00265] In a seventh aspect of the bit interleaving method, the row-to-column permutation process is equivalent to writing the M/FxQ bits per row in a matrix having Q columns and M/F rows, then reading the M/FxQ bits per column.
[00266] Also, in a sixth aspect of a bit interleaver, the folding section permutation unit applies a column row permutation process to the M/FxQ bits in each of the folding sections so as to swap the M /FxQ bits.
[00267] Consequently, a column-row permutation is used in the bending section permutation process, thereby enabling the realization of an extremely efficient bending section permutation process.
[00268] In a further aspect, a bit deinterleaving method for deinterleaving a bit stream in a communication system using quasi-cyclic low density parity check codes comprises: a step of receiving and receiving a bit sequence composed of NxQbits; and a bit-reverse permutation step of applying a bit-reverse permutation process to the received bit sequence so as to swap the bits in the bit sequence so as to restore the codeword of the low-density parity check codes. quasi-cyclic, in which the reverse bit permutation process reverses the bit permutation process in the first aspect bit interleaving method.
[00269] In an alternate aspect, a bit deinterleaver for deinterleaving a bit stream in a communication system using quasi-cyclic low density parity check codes comprises: a reverse bit permutation unit that receives a bit sequence composed of NxQ bits, and applying a reverse bit-swapping process to the received bit stream so as to swap the bits in the bit stream so as to restore a codeword of the quasi-cyclic low-density parity check codes, in which the reverse bit permutation process reverses the bit permutation process applied by the first aspect bit interleaver.
[00270] In another aspect, a decoder for a bit interleaving and demodulation system using quasi-cyclic low-density parity check codes, comprising: a constellation mapper that generates a smooth bit sequence indicating a probability of a corresponding bit one being a zero-bit and one being a one-bit; the bit deinterleaver of the alternate aspect of smooth bit sequence deinterleaving; and a low-density parity check decoder that decodes the de-interleaved smooth bit sequence.
[00271] In yet another aspect, the decoder of the other aspect further comprises: a subtraction unit that subtracts input to the low density parity check decoder from output of the low density parity check decoder; and the first aspect bit interleaver, providing the difference from the subtraction unit to the constellation mapper as a return.
[00272] Consequently, a bit interleaving process having high parallelism is achievable. Industrial Applicability
[00273] The present invention is applicable to a bit interleaver in bit-interleaved coding and modulation system used for quasi-cyclic low-density parity codes, and to a bit deinterleaver corresponding to such a bit interleaver. List of Reference Signals 2000A Bit Interleaver 2010A Bit Exchanger 2021A Folding Section Exchanger 2131A, 2132A Column-Line Exchanger 2500A Transmitter 2510 LDPC Encoder 2520A Bit Interleaver 2530 Constellation Mapper 2700A, 2800A Receiver 2710 Constellation Mapper 2720A Bit Deinterleaver 2730 LDPC Decoder 2740 Subtractor 2750A Bit Interleaver

权利要求:
Claims (17)
[0001]
1. Bit interleaving method for a communication system using quasi-cyclic low-density parity check codes, including repeating accumulated quasi-cyclic low-density parity check codes, the bit-interleaving method comprising: a step of receiving receiving a codeword of the quasi-cyclic low-density parity check codes composed of N cyclic blocks each including Q bits; a bit swapping step of applying a bit swapping process to the codeword so as to swap the bits in the codeword; and a dividing step of dividing the codeword, after the bit permutation process, into a plurality of constellation words, each of the constellation words being composed of M bits and indicating one of 2M constellation points in a constellation predetermined, characterized by the fact that before the bit permutation process, the codeword is divided into FxN/M folding sections, F being an integer greater than one, each of the folding sections including M/F of the blocks cyclic, and each of the constellation words being associated with one of the FxN/M folding sections, and in the bit permutation step, the bit permutation process is applied such that the M bits in each of the constellation words include F bits of each of different M/F cyclic blocks in a given folding section associated with a given constellation word, and such that all bits in the given folding section are mapped to only Q/F of the constellation words associated with the given bending section.
[0002]
2. Bit interleaving method according to claim 1, characterized in that the bit permutation step includes a bending section permutation step of independently applying a bending section permutation process to each of the FxN/M folding sections so as to swap bits in each of the folding sections.
[0003]
3. Bit interleaving method according to claim 2, characterized in that in the step of bending section permutation, the bending section permutation process is performed such that the Q bits in a given cyclic block are , each mapped to a bit of an identical robustness level in the Q/F constellation words associated with one of the folding sections that correspond to the given cyclic block.
[0004]
4. Bit interleaving method according to claim 1, characterized in that F is equal to a number of bits of an identical robustness level in one of the constellation words.
[0005]
5. Bit interleaving method according to claim 1, characterized in that F = 2, and the constellation words are QAM constellations.
[0006]
6. Bit interleaving method according to claim 2, characterized in that the bending section permutation step includes a row-column permutation step of applying a row-column permutation process to the M/ FxQ bits in each of the folding sections in order to swap the M/FxQ bits.
[0007]
7. Bit interleaving method according to claim 6, characterized in that the row-column permutation process is equivalent to writing the M/FxQbits in the row sense in a matrix having Q columns and M/F rows, then read the M/FxQbits in the column direction.
[0008]
8. Bit deinterleaving method for reversing the bit interleaving method as defined in claim 1, deinterleaving a bit stream in a communication system using quasi-cyclic low density parity check codes including parity check codes of low-density accumulated quasi-cyclical repetition, bit deinterleaving method characterized by the fact that it comprises: a receiving step of receiving a bit sequence composed of NxQ bits; and a bit-reverse permutation step of applying a bit-reverse permutation process to the received bit sequence so as to swap the bits in the bit sequence, wherein the bit-reverse permutation process reverses the bit-permutation process in the bit interleaving method.
[0009]
9. Bit interleaver (2000A) for use in a communication system using quasi-cyclic low-density parity check codes, including repeating accumulated quasi-cyclic low-density parity check codes, bit interleaver (2000A) comprises : a bit permutation unit (2010A) receiving a codeword of quasi-cyclic low density parity check codes composed of N cyclic blocks each including Q bits, applying a bit permutation process to the mode codeword swapping the bits in the codeword, and dividing the codeword, for output after the bit swapping process, into a plurality of constellation words, each of the constellation words being composed of M bits and indicating one of 2M constellation points in a predetermined constellation, characterized by the fact that before the bit permutation process, the codeword is divided into FxN/Mdouble sections tion, F being an integer greater than one, each of the folding sections including M/F of the cyclic blocks, and each of the constellation words being associated with one of the FxN/M of the folding sections, and the permutation unit bitwise (2010A) applies the bit permutation process such that the M bits in each of the constellation words include F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word , and such that all bits in the given folding section are mapped to only Q/F of the constellation words associated with the given folding section.
[0010]
10. Bit interleaver (2000A) according to claim 9, characterized in that the bit permutation unit (2010A) includes a bending section permutation unit (2021A, 2022A, 2023A, 2024A, 2025A, 2026A) independently applying a bending section permutation process to each of the FxN/M bending sections so as to swap bits in each of the bending sections.
[0011]
11. Bit interleaver (2000A) according to claim 10, characterized in that the bending section permutation unit (2021A, 2022A, 2023A, 2024A, 2025A, 2026A) applies the process of bending section permutation folding such that the Q bits in a given cyclic block are each mapped to a bit of an identical robustness level in the Q/F constellation words associated with one of the folding sections that correspond to the given cyclic block.
[0012]
12. Bit interleaver (2000A), according to claim 9, characterized in that F is equal to a number of bits of an identical robustness level in one of the constellation words.
[0013]
13. Bit interleaver (2000A), according to claim 9, characterized by the fact that F = 2, and the constellation words are QAM constellations.
[0014]
14. Bit interleaver (2000A) according to claim 10, characterized in that the bending section permutation unit (2021A, 2022A, 2023A, 2024A, 2025A, 2026A) applies a line-permutation process. column to the M/FxQbits in each of the folding sections in order to swap the M/FxQbits.
[0015]
Bit deinterleaver (2730A) for reversing processing applied by the bit interleaver (2000A) as defined in claim 9, deinterleaving a bit stream in a communication system using quasi-cyclic low density parity check codes, including repeating accumulated quasi-cyclic low-density parity check, the bit deinterleaver (2730A) characterized in that it comprises: a reverse bit permutation unit receiving a bit sequence composed of NxQ bits, and applying a process of permutation of bit reverse to the received bit stream so as to swap the bits in the bit stream, wherein the bit reverse permutation process reverses the bit swap process applied by the bit interleaver (2000A).
[0016]
A decoder including the bit deinterleaver (2730A) as defined in claim 15, for use in a bit interleaving and demodulation system using quasi-cyclic low-density parity check codes, including quasi-cyclic low-density parity check codes. repeating accumulated cyclics, the decoder characterized in that it comprises: a constellation demapper (2720) generating a smooth bit sequence indicating a probability of a corresponding bit being one of a zero-bit and one-bit; the bit deinterleaver (2730A) deinterleaving the smooth bit sequence; and a low density parity check decoder (2740) decoding the de-interleaved smooth bit sequence.
[0017]
17. The decoder of claim 16, further comprising: a subtraction unit (2760) subtracting an input to the low density parity check decoder (2740) from the output of the check decoder low density parity (2740); and the bit interleaver (2750A) as defined in claim 9, providing the difference from the subtraction unit (2760) to the constellation demapper (2720) as feedback.

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2019-10-29| B06U| Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]|

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2021-02-02| B06A| Patent application procedure suspended [chapter 6.1 patent gazette]|

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2021-05-18| B09A| Decision: intention to grant [chapter 9.1 patent gazette]|

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2021-06-29| B16A| Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 18/05/2012, OBSERVADAS AS CONDICOES LEGAIS. |

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