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    • 专利摘要:
    system and method of parallel digitizers of stacked image sensor sub-columns using vertical interconnections the modalities of a hybrid imaging sensor and pixel sub-column data methods are read within a matrix of pixels. the hybrid imaging sensor and methods optimize the pixel matrix area and use a stacking scheme for a hybrid imaging sensor with minimal vertical interconnections between the substrates.
    公开号:BR112013029014A2
    申请号:R112013029014-5
    申请日:2012-05-14
    公开日:2020-05-12
    发明作者:Blanquart Laurent
    申请人:Olive Medical Corporation；
    IPC主号:
    专利说明:

    Descriptive Report of the Invention Patent for SYSTEM AND METHOD OF PARALLEL DIGITALIZERS OF HYBRID STACKED IMAGE SENSOR SUBCOLUMNS USING VERTICAL INTERCONNECTIONS.
    BACKGROUND
    The description generally refers to electromagnetic detection and sensors and also refers to low energy electromagnetic input conditions as well as low energy electromagnetic production conditions. The description refers more particularly, but not necessarily, to the optimization of the pixel matrix area and the use of a stacking scheme for a hybrid image sensor with minimal vertical interconnections between substrates and associated systems, methods and characteristics, which they can also include maximizing the pixel matrix size / actual size (area optimization).
    There has been a popularization of the number of electronic devices they use and include the use of image / camera technology in general. For example, smartphones, tablets, and other portable computing devices include and use image / camera technology. The use of image / camera technology is not limited to the consumer electronics industry. Several other fields of use also use image / camera technology, including various industrial applications, medical applications, residential and commercial security / surveillance applications, and more. In fact, imaging / camera technology is used in almost every industry.
    Due to this popularization, the demand for ever smaller high definition imaging sensors has increased significantly in the market. The device, system and methods of the description can be used in any imaging application where size and form factor are considerations. Several different types of imaging sensors can be used by the description, such as a charge-coupled device (CCD), or a complementary metal oxide semiconductor (CMOS), or any other image sensor currently known or that may become known in the future.
    2/32
    CMOS image sensors typically assemble the entire array of pixels and related circuitry, such as analog-to-digital converters and / or amplifiers, on a single chip. Due to the physical restrictions of the chip size itself and the physical space occupied by a set of related circuits involved in a conventional CMOS image sensor, the area that the pixel array can occupy on the chip is generally limited. Thus, even though the pixel matrix is maximized on a substrate that also contains the related circuitry, the pixel matrix is physically limited in area due to the amount of area and physical space that the related circuitry for signal processing and other functions it occupies on the chip.
    In addition, the application or field of use in which the CMOS image sensor can be used, generally requires that the CMOS image sensor be limited to a certain size also limiting the physical area that the pixel matrix can occupy. The size limitations of a CMOS image sensor often have conflicts between image quality and other important functions, such as signal processing, due to the number of considerations that must be considered when designing and manufacturing a CMOS image sensor. Thus, for example, the increase in the pixel matrix area may be associated with a conflict in other areas, such as A / D conversion or other signal processing functions, due to the reduced area that the related circuitry can occupy.
    The description optimizes and maximizes the pixel matrix without sacrificing the quality of the signal processing by optimizing and maximizing the pixel matrix on a first substrate and stacking the related circuitry on subsequent substrates. The description uses advances in backlighting and other areas to take advantage of the optimization of the pixel matrix area on a substrate. The stacking scheme and structure allows highly functional large-scale circuits to be used while maintaining a small chip size.
    The characteristics and advantages of the description will be presented in the description below, and in part will be visible from the description, or po
    3/32 must be instructed to practice description without undue experimentation. The characteristics and advantages of the description can be understood and obtained through the instruments and combinations particularly pointed out in the appended claims.
    BRIEF DESCRIPTION OF THE DRAWINGS
    The characteristics and advantages of the description will become visible from a consideration of the subsequent detailed description presented together with the attached drawings, in which:
    Figure 1 illustrates a modality of an image forming sensor built on a plurality of substrates and also illustrates a modality of the specific positioning of support circuits according to the instructions and principles of the description;
    figure 2 illustrates a modality of a pixel matrix in which the interconnections are spaced in relation to the pixels within the pixel matrix according to the instructions and principles of the description;
    figure 3 illustrates a modality of a pixel matrix in which the interconnections are spaced in relation to the columns within the pixel matrix according to the instructions and principles of the description;
    Figure 4 illustrates a modality of a pixel matrix in which the interconnections are spaced in relation to the areas within the pixel matrix according to the instructions and principles of the description;
    figure 5 illustrates a perspective view of an embodiment of an image forming sensor constructed on a plurality of substrates in which a plurality of pixel columns that form the pixel matrix is located on the first substrate and a plurality of circuit columns it is located on a second substrate and shows an electrical connection and communication between a column of pixels with its associated or corresponding column of circuitry through interconnections, in which the interconnections can be spaced in relation to defined pixel areas within the matrix of pixels according to the instructions and principles of the description;
    figures 6-10 illustrate top views of various modalities
    4/32 of an image forming sensor built on a plurality of substrates in which a plurality of pixel columns that form the pixel matrix is located on the first substrate and a plurality of circuit columns is located on a second substrate and shows an electrical connection and communication between a column of pixels with its associated or corresponding column of circuitry through interconnections, in which the interconnections can be spaced in relation to pixel areas defined within the pixel matrix according to the instructions and principles description;
    Figure 11 illustrates a top view of an embodiment of an image sensor built on a plurality of substrates in which a plurality of columns and sub-columns of pixels that form the pixel matrix is located on the first substrate and a plurality of columns of pixels. circuit is located on a second substrate and shows an electrical connection and communication between a column of pixels with its associated or corresponding column of circuitry;
    figure 12 illustrates a perspective view of an embodiment of a plurality of columns and sub-columns that forms a matrix of pixels located on a first substrate and a plurality of circuit columns located on a second substrate and shows an electrical connection and communication between a sub-column of pixels with their associated or corresponding circuitry column according to the instructions and principles of the description;
    figures 12a - 12c show front and side perspective views, respectively, of a single pixel column that has been formed into two separate pixel sub-columns, where each pixel sub-column is connected to a different pixel column reading bus, and illustrate two circuitry columns extracted from figure 12 that show an electrical connection between them;
    Figure 13 illustrates a perspective view of an embodiment of a plurality of columns and sub-columns that forms an array of pixels located on a first substrate and a plurality of circuit columns.
    5/32 dedicated to one or more sub-columns of pixels located on a second substrate and shows an electrical connection and communication between a column of pixels with its associated or corresponding column of circuits according to the instructions and principles of the description;
    Figure 13a illustrates a perspective view of a single pixel column that has been formed into two separate pixel sub-columns, where both pixel sub-columns are connected to a different pixel column reading bus, and illustrates an electrical connection between the reading buses to a circuitry column extracted from figure 13;
    figure 14 illustrates a perspective view of an embodiment of a plurality of columns and sub-columns that forms a matrix of pixels located on a first substrate and a plurality of circuit columns located on a second substrate and shows an electrical connection and communication between each sub-column of pixels with their associated or corresponding circuitry column according to the instructions and principles of the description;
    figures 14a - 14c illustrate front and side perspective views, respectively, of a single pixel column that has been formed into two separate pixel sub-columns, where each pixel sub-column is connected to a different pixel column reading bus, and illustrates two circuitry columns extracted from figure 14 showing an electrical connection between them; and figures 15-18 illustrate top views of various modalities of a plurality of columns and sub-columns that form a pixel array located on a first substrate and a plurality of circuit columns located on a second substrate and show an electrical connection and communication between each sub-column of pixels with their associated or corresponding circuitry column according to the instructions and principles of the description.
    DETAILED DESCRIPTION
    For the purposes of promoting an understanding of the principles
    6/32 according to the description, reference will now be made to the modalities illustrated in the drawings and a specific language will be used to describe them. However, it will be understood that no limitations on the scope of the description will be planned. Any further changes and modifications to the inventive features illustrated here, and any additional applications of the principles of the description as illustrated here, which could normally occur for an element versed in the relative technique and who owns that description, will be considered within the scope of the claimed description.
    Before devices, systems, methods and processes of alternating ADC or column circuit reliefs on a hybrid column or sub-column image sensor using vertical interconnections are shown and described, it will be understood that this description is not limited to structures, configurations, steps process, and particular materials described here since structures, configurations, process steps, and materials can vary widely. It will also be understood that the terminology used here is used only for the purpose of describing particular modalities and is not intended to be limiting as the scope of the description will be limited only by the attached claims and equivalents thereof.
    It should be noted that, as used in this specification and in the appended claims, the forms in the singular one, one, and include the referents in the plural except where the context clearly indicates otherwise.
    When describing and claiming the subject of the description, the following terminology will be used according to the definitions presented below.
    As used herein, the terms comprise, include, contain, characterized by, and grammatical equivalents of these are inclusive or open terms that do not exclude additional elements or method steps not cited.
    As used here, the phrase consists of and grammatical equivalents of that exclude any element or step not specified in the claim.
    7/32
    As used here, the phrase essentially consists of and grammatical equivalents of that limit the scope of a claim to the specified materials or steps and those that do not materially affect the basic and new features or characteristics of the claimed description.
    As used here, the term proximal should refer broadly to the concept of a portion closer to an origin.
    As used here, the term distal should generally refer to the opposite of proximal, and thus to the concept of a distant portion of an origin, or a more distant portion, depending on the context.
    A digital image, whether from a film, has many limitations imposed on this relation to the devices used to record the image data. As discussed here, an image sensor can include an array of pixels and support circuits that are arranged on at least one substrate. Devices generally have practical and optimal limitations on the form factor of the imaging sensor depending on the application. Usually the pixel matrix is not the only adjustment consideration, however, and the set of support circuits that needs to be accommodated. Support circuits can be, but are not necessarily limited to, analog to digital converters, power circuits, power collectors, amplifier circuits, dedicated signal processors and filters, serializers for transmission preparation, etc. In addition to circuits, physical property elements may be required, such as light filters and lenses. Each pixel must be read from the pixel matrix and have the data processed by the support circuits. With the increase in the number of pixels in a matrix, more data must be manipulated. Regarding film data, the sensor must unload its data and be ready to operate again immediately.
    Although size is an issue as shown above, pixel count numbers continue to rise across the industry regardless of the specific application, and often obscure the means that are used to actually view images after being recorded, such as a monitor computer or television. However,
    8/32 be understood that not all pixels are created equal. In the example above, a scope setting can be used in a limited light application.
    As pixel counts continue to grow in a given space, the distance between pixels decreases, thus requiring greater precision for electrical interconnect contact. Consequently, the cost of producing an image sensor may increase as the need for greater precision in data manipulation is required for the increased distance between pixels. Current technologies can be used to obtain image sensors with increased capacities, but at an increased cost as yields fall during manufacturing.
    The problems identified above describe the current state of the art in relation to some needs within the industry. An image sensor that has adequate resolution through pixel counting, a vertical architecture and form factor, and the largest possible pixel size is required, while restricted in a limited space. The description includes and will discuss the design modalities and methods that address these and potentially other issues by optimizing the size of the pixel matrix on a substrate / chip and remotely locating support circuits in a generally vertical configuration on one or more substrates / support chips.
    High-performance image sensors using analog to digital chip (ADC) converters, digital and analog chip algorithms, complex chip timers, and complex analog chip functions provide high-quality images for the following reasons (the list below is not a complete list, but is provided merely for 'exemplary purposes):
    No noise captured due to long lines of analog data outside the chip (if there is no ADC on chip, then analog signals are required to be sent outside the chip);
    Lower temporal noise due to digital conversion is initially performed on the data path (no amplifier, additional buffer
    9/32 which will add additional noise);
    Local timing optimization uses a complex chip timer generator. Due to the counting limitation, only a simple delay can be performed using the external system;
    Lower noise generated by I / O. Chip systems allow for a reduced count; and a faster operation can be carried out (more serial chip operation, reduced capacitances and parasitic resistances). With increasingly larger arrays, the need to read and process the data created in them is paramount.
    The description also includes an image sensor that must otherwise be manufactured with its pixel matrix and set of support circuits on a single monolithic substrate / chip and separating the pixel matrix from all or most of the set of pixels. support circuits. The description can use at least two substrates / chips, which will be stacked together using three-dimensional stacking technology. The first of the two substrates / chips can be processed using a CMOS image process. The first substrate / chip can be comprised exclusively of a pixel array or a pixel array surrounded by a limited circuitry. The second or subsequent substrate / chip can be processed using any process, and does not have to be a CMOS imaging process. The second substrate / chip can be, however without limiting character, a highly dense digital process to integrate a variety and numerous functions in a very limited space or area on the substrate / chip, or a mixed or analog process to integrate, for example , precise analog functions, or an RF process to implement wireless capability, or MEMS (Micro-Electro-Mechanical Systems) to integrate MEMS devices. The CMOS image substrate / chip can be stacked with the second or subsequent substrate / chip using any three-dimensional technique. The second substrate / chip can support most of the circuitry that could otherwise be implemented on the first image CMOS chip (if implemented on a substrate / monolithic chip) as peripheral circuits and therefore increased the area of
    10/32 total system while keeping the pixel matrix size constant and optimized to the maximum possible level. The electrical connection between the two substrates / chips can be made through interconnections, which can be wire connections, pbump and / or TSV (Via Via Silicon).
    Now with reference to figure 1, a modality of an image sensor with its pixel matrix and set of support circuits built on a plurality of substrates is illustrated using back lighting. As can be seen in the figure, a pixel array 450 can be arranged on a first substrate 452. The first substrate 452 can be made of silicon or other material to control the characteristics of light transmission. Solder balls, reliefs or 421 tracks can be used to electrically connect one substrate to another. One embodiment of a stacked image sensor may comprise a pixel array 450 on a first substrate 452. The pixel array 450 may include at least forty percent of a first surface 451 of the first substrate 452. In a backlight configuration, a matrix of pixels can be arranged at the rear of said first substrate. In addition, in a backlighting configuration, substrate 452 can be reduced to control light transmission through it. In a mode that uses backlighting, the first substrate can be made mainly of silicon material, or the first substrate can be made mainly of high-impedance (High-Z) semiconductor material (for example, Cadmium Telluride), or the first substrate can be made mainly of semiconductor materials ll-V (for example, Gallium Arsenide).
    In one embodiment, a pixel array 450 may include most of the first surface 451 of a first substrate 452. In that embodiment, the pixel array 450 may be located or located on any portion of said first surface 451. The remaining space on the first surface 451 can be used for secondary circuit positioning, if desired. Situations can arise where a secondary circuit can be dimensioned in such a way that the central positioning of the pixel matrix is not practical.
    11/32
    During use, the data created by individual pixels in the pixel array must be processed by a set of support circuits, since each pixel must be electronically connected to support circuits. Ideally, each pixel could be read simultaneously creating a global shutter.
    Now with reference to figure 2, it will be assessed that the ability to read data from an imaging device as a global shutter requires that there is an interconnection 1724 per pixel 1726, which is very difficult to obtain in practice due to the step of relief during manufacturing tolerances. Figure 3 illustrates a situation where pixels 1726 were formed in a plurality of columns, such as 1728. Using a pixel column format (1728) in a pixel matrix, a very high frame rate can be obtained using a bearing type shutter. It will be judged that a rolling shutter reads an entire row of pixels substantially simultaneously and then reads or moves from the top of the pixel columns to the bottom of the pixel columns. In other words, the first row of pixels: can be read followed by the next adjacent row of pixels since the data is read from the plurality of pixel columns, and the reading starts at the top of the pixel columns and then goes down to the columns, pixel by pixel at a time, and moves in a predetermined and calculated pattern across the entire array of pixels. In the case of a rolling shutter, only one 1730 read bus needs to be present per 1728 pixel column, and one 1740 read bus per circuit column.
    Due to the overlapping of the reading buses 1730 and 1740 on the first substrate 1752 and the second substrate 1754, respectively, only one interconnect / relief 1724 per pixel column bus 1730 is required to connect the 1730 pixel reading bus to the reading bus of circuit 1740, instead of an interconnect / relief 1724 per pixel 1726 as required by a global shutter.
    Figure 2 illustrates a configuration or relief scheme that uses a 1724 relief per 1726 pixel, which is close to a
    12/32 global shutter. In this configuration, the relief step is equal or substantially equal to the pixel step in the X and Y axes or directions. Figure 3 illustrates a relief configuration or scheme that uses an interconnection / relief 1724 per column of pixels 1728. This configuration can be used in a rolling shutter operation. This configuration or relief step scheme is more relaxed as compared to the relief step of figure 2 only in the vertical direction. However, it should be noted that in this configuration, the relief step is still required to be at least equal in one direction or dimension to the pixel step. Figure 3 illustrates a plurality of columns 1728, where each column 1728 is comprised of a plurality of pixels 1726. Each column of pixels can be oriented in the Y direction (y-axis) at a distance and can be one pixel wide as illustrated . Each column of pixels can be read through a single connection point at one end of each 1728 column. Although this configuration simplifies the chip architecture, strict tolerances must still be maintained due to the fact that the distance between the pixels laterally (horizontally) continue to limit the relief step (interconnection) due to the possibility that the interconnection does not make contact with an adjacent interconnection and is consequently dimensioned.
    Figure 4 illustrates a relief configuration that is even more relaxed than that shown in figures 2 or 3. In this figure, the relief step is relaxed (for example, the distance between the reliefs has been increased compared to figures 2 and 3) and half of the interconnections / reliefs 1724 can be used to process data on each side of the 1710 pixel array. This can be done by adding or introducing a second set of interconnections 1724 that alternate with the column reading buses and at opposite ends of the column reading buses (for example, a 1724 interconnect is used to connect the reading buses 1730, 1740 and can be located on each column reading bus on one side of the 710 pixel array and the opposite can be performed on the other side of the pixel array 710). As can be seen in figure 4, the second set of interconnections 1724b can
    13/32 can be used in combination with the first set of interconnects 724a and can be used to allow half of the data to be processed or read on each side of the 1710 pixel array. This configuration can allow you to almost double the relief step size ( interconnection step) as compared to the distance between pixels in at least one dimension, this could greatly reduce the cost of producing 1700 image sensors. In one embodiment, more than one interconnection or relief 1724 per column of pixels 1728 can be used per read bus, so that data can be read from each end of the 1728 pixel column.
    Figures 5-10 illustrate the modalities and configurations of an array of pixels 1810 that have an alternating interconnection or relief 1824 positioned on a substrate / chip. As noted above, due to the fact that there is a reading bus 1830 per column of pixels 1828, 1832 and the reading bus 1840 per column of circuit, and due to the fact that the reading buses 1830 and 1840 are executed from the part From the top of the column to the bottom of the column, the 1824 interconnect / relief can be positioned somewhere along the overlapping path of the busbars within the column. To relax the relief step, the relief distance can be increased from column to column by moving the next column relief 1824 up or down (in the Y direction) in the next column.
    As an example, it will be appreciated that the pixel pitch can be about 5 pm and the pixel column can be any length, for example, between about 2 mm and about 15 mm. It should be noted that the relief step is a pixel step function, so that the pixel step is determinative of an ideal relief step. For example, assuming there is a desired relief step of approximately 100 pm, the placement of a first interconnection or relief 1824 can then be performed by starting at the top of the first column and moving the next interconnection or column relief down by 100 pm . All other reliefs are similarly positioned up to the interconnection or relief
    14/32 20 in the column of the row is located at the bottom of the column of pixels. At this point, the interconnection 21 or raised in the column 1824 can be re - positioned at the top of the column of pixels 1828. The same pattern can then be repeated until the final pixel array 1810. Horizontally, the interconnections or embossments 1824 can be separated by 20 columns x 5 pm = 100 pm. In this example, all reliefs will then be separated by more than 100pm, even if the pixel pitch is about 5 pm. Redundancy can then be introduced in the pixel column for performance purposes. For example, the reliefs in all columns can be folded (that is, the two reading buses are connected by 2 interconnections or reliefs). This technique could significantly increase the stacking yield and reduce the cost of the total process.
    As can be seen in figure 5, a first column 1828 of pixels 1826 can be electrically accessed through a first interconnection 1824a. In the modality, a second column of pixels 1832 can be electrically accessed through a second interconnection 1824b, which was positioned during manufacture in an alternating configuration in relation to said first interconnection 1824a. As illustrated, the location or position of the second interconnect 1824b can be at least two pixel widths away from the position of the first interconnect 1824b (and any other interconnect 1824) in the X and Y dimensions or directions. A third interconnect 1824c can then be positioned similarly in a third column of pixels and so on in N-number of interconnections 1824 across the matrix of pixels 1810.
    This configuration provides an interconnect pass that is at least three times that of the pixel pass. It will be assessed that the gain in the interconnection step can be much greater than three times that of the pixel step under standard conditions. However, it will be assessed that the gain in the interconnection step can be at least three times the pixel step as noted above.
    Also, greater interconnection gains can be achieved with area-based spacing instead of network-based connectivity.
    15/32 column by column (see figures that illustrate a 6/1 pixel column aspect ratio and a 6/1 and 3/2 loop column aspect ratio, or a column aspect ratio of 6/1 8/1 pixels and a circuit column aspect ratio of 2/4). This can be accomplished by adding more bus structures or using direct reading on a subsequent substrate. In each configuration, the interconnection step can be described as follows:
    Interconnect _ Pitch = i1 (N * Pixel Pitch,) 2 + (M * Pixel Piich) 2 where N is the number of pixels between two adjacent interconnections in the X direction and M is the number of pixels between two adjacent interconnections in the Y direction. It will be assessed that each of the plurality of interconnections can be a relief where the distance from relief to relief can be greater than two pixels wide, or greater than four pixels wide, or greater than eight pixels wide.
    In many applications, N x Pixel Pass in the X direction will be equal to M x Pixel Pass in the Y direction. As illustrated in figures 6-10, larger pixel arrays 1810 can be accommodated or drawn by extrapolating the process described above through additional iterations. Figure 6 illustrates a stack of superimposed silicon substrate. In the figure, a first substrate 1852 consisting of an array of pixels 1810 is shown superimposed on the top of a support substrate 1854 which comprises support circuits. The area available to position the support circuits of a first column of 1881 pixels is drawn in dotted lines and marked for purposes of simplicity and discussion. It will be evaluated that the real area of the circuit column is not represented by the dotted lines, but it can be larger, smaller or equal to the area of the pixel column. As discussed above, the support circuit area is directly correlated to the area of a column of pixels to which they correspond. Each column of pixels can be one pixel wide and sixty-four pixels long and can have a read bus that runs from top to bottom of the pixel column. In figure 6, the area available for positioning the support circuit can be equal to one pixel unit
    16/32 wide by sixty-four pixel units long, this is shown as the thickest vertical lines in the figure. Therefore, the interconnection 1824 between the substrates in figure 6 must be within the area of sixty-four pixel units to read that column, since the pixel column reading bus and the column circuit reading bus are superimposed on the along the trajectory of the sixty-four pixels, so that the interconnection 1824 can be positioned somewhere along those sixty-four pixels to connect the reading buses.
    Furthermore, due to the fact that the interconnection can be located only where the pixel column reading bus and the supporting circuit reading bus overlap, the interconnection range for reading the corresponding pixel column is 1 pixel wide and 64 pixels long (for this example), this is the intersection between the column of pixels and the support circuit that will be connected.
    It should be noted that the exemplary aspect ratio of the support circuit area in figure 6 is illustrated as 1/64. There are many options for locating or positioning the 1824 interconnect within that area and the final location can then be selected by the designer to allow for the desired interconnect spacing for interconnection. For example, as best illustrated in figures 6-10, it will be assessed that in a modality where the interconnections or reliefs 1824 are in an alternating configuration, there may be an interconnection or relief 1824 per group of pixels 1826.
    In addition, it should be noted that several read bus architectures can be used depending on the desired application. As discussed above, larger dedicated support circuits can be employed to process the data read through each 1824 interconnect. Alternating the position of each 1824 interconnect / relief can also provide even more space for the support circuits in relation to each area or group of pixels within the 1810 pixel array.
    It should also be noted that many change settings
    17/32 optimum nations were found on the same base sensor with different support circuit aspect ratios as illustrated in figures 6-10. An optimal configuration can be found by varying the position of the interconnection within the range of the intersection between a column of pixels and the support circuit and the allocation pattern of the support circuit in each column of pixels. It should also be noted that all the interconnections illustrated in figures 6-10 are more than 7 pixels apart.
    In figure 7, the area available for positioning the support circuit can be equal to two pixel units wide by thirty-two pixel units long, this is shown as the thickest vertical lines in the figure. Therefore, interconnection 1824 between substrates 1852 and 1854 must be in the area of sixty-four pixel units to read that column. It should be noted that the aspect ratio of the support circuit area in this example is 2/32. Each pixel column is or can be one pixel wide and sixty-four pixels long and can have a read bus that moves from top to bottom of the pixel column. The selection of where to position the interconnection has many options within that area and can be performed to allow the desired spacing from interconnection to interconnection. Furthermore, due to the fact that the interconnect can be located only where the pixel column reading bus and the support circuit reading bus overlap to read the corresponding pixel column, the interconnection range can be 1 pixel wide and thirty-two pixels long (for this example), this is the intersection between the column of pixels and the support circuit that will be connected.
    In figure 8, the area available for positioning the support circuit can be equal to four pixel units wide by sixteen pixel units long, this is shown as the thickest vertical lines in the figure. Therefore, the interconnection between the substrates must be in the area of sixty-four pixel units to read the corresponding pixel column. It should be noted that the aspect ratio of the support circuit area in this example is 4/16. Each pixel column pos
    18/32 sui or can be one pixel wide and sixty-four pixels long and can have a reading bus that moves from top to bottom of the pixel column. The selection of where to position the interconnection has many options within that area and can be performed to allow the desired spacing from interconnection to interconnection.
    Furthermore, due to the fact that the interconnection can be located only where the pixel column reading bus and the support circuit reading bus overlap to read the corresponding pixel column, the interconnection range can be one pixel wide and sixteen pixels long (for this example), this is the intersection between the column of pixels and the support circuit that will be connected.
    In figure 9, the area available for positioning the support circuit can be equal to eight pixel units wide by eight pixel units long, this is shown as the thickest vertical lines in the figure. Therefore, interconnection 1824 between substrates 1852 and 1854 must be in the area of sixty-four pixel units to read the corresponding pixel column. It should be noted that the aspect ratio of the support circuit area in this example is 8/8. Each pixel column is or can be one pixel wide and sixty-four pixels long and can have a read bus that moves from top to bottom of the pixel column. The selection of where to position the interconnection has many options within that area and can be performed to allow the desired spacing from interconnection to interconnection.
    Furthermore, due to the fact that the interconnection can be located only where the pixel column reading bus and the support circuit reading bus overlap to read the corresponding pixel column, the interconnection range can be one pixel wide and eight pixels in length (for this example), this is the intersection between the column of pixels and the support circuit that will be connected.
    In figure 10, the area available for positioning the support circuit can be equal to sixteen pixel units wide by four pixel units long, this is shown as the vertical lines.
    19/32 thicker quays in the figure. Therefore, the interconnection between the substrates must be in the area of sixty-four pixel units to read the corresponding pixel column. It should be noted that the aspect ratio of the support circuit area in this example is 16/4, this example shows the flexibility that these methods and devices described here can provide. Each pixel column is or can be one pixel wide and sixty-four pixels long and can have a read bus that moves from top to bottom of the pixel column. The selection of where to position the interconnection has many options within that area and can be performed to allow the desired spacing from interconnection to interconnection.
    Furthermore, due to the fact that the interconnection can be located only where the pixel column reading bus and the support circuit reading bus overlap to read the corresponding pixel column, the interconnection range can be one pixel wide and four pixels long (for this example), this is the intersection between the column of pixels and the support circuit that will be connected.
    It should also be noted that the pattern of the association of the support circuit to the pixel column may be different from that of figures 6-10 and this association can finally provide the optimal distance between the interconnections. For example, interconnects can be optimally positioned at least two pixels wide, four pixels wide, eight pixels wide, or more. A designer can optimally determine the distance that the interconnections can be separated from each other based on two degrees of freedom: (1) the number of pixels per column, and (2) the aspect ratio and circuit location. In these examples shown in figures 6 - 10, the interconnections can be located approximately eight pixels apart. However, it will be understood that other designs can be implemented without abandoning the spirit or scope of the description.
    For example, as illustrated in figure 6, each 1824 interconnect can be located eight pixels long and one pixel wide.
    20/32 distance from each other. Because each circuit column has an aspect ratio of one pixel wide and sixty-four pixels in length, interconnections 1824 can then be located eight pixels apart from each other in adjacent columns as shown in figure 6, up to the lower part of circuit 1800 is reached, in which case the interconnections 824 are then moved over the next column and continue along the entire width of the 1810 pixel matrix. In contrast, in figure 10, the interconnections 1824 are still located eight pixels long and one pixel wide apart. However, in this example, the circuit column aspect ratio is now four pixels long and sixteen pixels wide. Thus, for interconnections 1824 to be at least eight pixels apart, an 1856b circuit column must be skipped since the aspect ratio is only four pixels in length, so that interconnections 1824 maintain optimal spacing. Thus, for example, an interconnection 1824 is positioned in the upper left corner of the matrix of pixels 1810 in figure 10 (in the first pixel of the first column 1828) and then it moves to the next column of pixels 1832 and counts eight pixels long, the next interconnect 1824 can then be positioned on the third column of circuit 1856c, skipping the second column of circuit 1856b in total. This pattern can be used throughout the pixel array. The second omitted circuit column 1856b is then connected to the pixel matrix by an interconnection 1824a which is placed in the ninth pixel column and the pattern is repeated for all omitted circuit columns. Thus, as illustrated, the optimal interconnection spacing can be obtained and various circuit designs can be accommodated without abandoning the scope of the description.
    Now with reference to figure 11, an array of pixels 1810 that has columns and sub-columns will be discussed. As can be better seen in figure 11, a portion of a pixel array 1810 is illustrated with six columns, each column moves from above the portion of the illustrated pixel array below the pixel matrix. It will be assessed that the circuit
    21/32 modern 1800 will have a matrix of pixels 1810 that comprises many more columns of pixels (a plurality of pixels move in the Y direction in the figure) and rows (a plurality of pixels move in the X direction in the figure) forming the matrix 1810 Only a limited number of columns and rows of pixels are shown here for purposes of illustration and for reasons of discussion and simplicity.
    Each column of pixels 1828 in the matrix of pixels 1810 can be divided into sub-columns. Sub-columns can be defined as a plurality of pixels within a column that is smaller than the entire column of pixels and that are electrically connected to a bus of pixel sub-columns. Thus, there can be a plurality of pixel sub-columns per column of 1828 pixels. Each sub-column can have a contact pad and / or an interconnect illustrated as 51, 52, 53 and 54 to electrically connect each sub-column bus on the first substrate to a associated or corresponding circuit column bus located on the support substrate.
    At least one pixel column bus can be used to provide an electrical connection for each pixel in column 1828. Column 1828 can be divided into a plurality of sub-columns, where at least one pixel sub-column bus is present per pixel sub-column . Sub-column buses can be differentiated by dividers 62, 63, 64, these dividers can be a physical space or gap or another device to electrically isolate the pixel sub-column and / or the sub-column bus from another sub-column and / or sub-column bus . During use, the pixel data can be read in the form of a rolling shutter, which is substantially simultaneous to each row of pixels in each sub-column (illustrated as four sub-columns in figure 11). In this configuration, the reading time can be substantially reduced due to the number of sub-columns that are connected to dedicated circuit columns via the pixel sub-column reading bus and the circuit column reading bus and the interconnections that electrically connect the buses . Thus, the reading time in the illustrated mode can be
    22/32 theoretically reduced (that is, the reading speed is increased) for the entire column (the one in figure 11 includes four sub-columns) by the number of sub-column buses. In figure 11, there are four sub-columns and sub-column buses, so that the reading time is reduced (the speed is increased four times) by seventy and belt percent. It will be assessed that the number or configuration of sub-columns is not important, the rolling shutter can operate row by row at the beginning of each sub-column by progressively reading each pixel in the sub-column to the end of the sub-column simultaneously with the other sub-columns (simultaneously reading the row of pixels starting from the pixel row located at 51.52, 53, 54).
    In other embodiments, the column can be divided into any number of sub-columns, with each division of the column (for example, the addition of a sub-column) approaching a global shutter feature. As can be seen in the figure, the contact pads and interconnection locations can be switched on each column. As illustrated, interconnections of the column labeled A from those in the column labeled B. Other iterations of sub-column alternation and interconnection are possible for N number of columns.
    Referring now to Figures 12 to 14c, several views of an embodiment of an image forming sensor 1200 constructed on a plurality of substrates with sub-column reading functionality and remotely located support circuits are illustrated. Figures 12 and 14 illustrate a plurality of pixel columns 1252 and 1452 forming the pixel array 1250 and 1450 on the first substrate 1210, 1410 and a plurality of circuit columns 1256, 1456 (representing the support circuitry 1270 , 1470) on the second substrate 1211, 1411.
    As illustrated in figures 12 - 12c, a pixel array 1250 can be divided into a plurality of columns and sub-columns 1252. The size of the columns and sub-columns can, for example, be based on the size of the associated circuitry 1270 and circuit columns 1256. For example, the pixel sub column 1252 can be one pixel wide and N number of pixels long (in figures 12 - 12c, the sub columns of
    23/32 pixels are illustrated as being one pixel wide and six pixels long) and circuit columns 1256 are illustrated as having an aspect ratio of one pixel wide by six pixels long. It will be assessed that the size or area of the 1256 circuit column can dictate or direct the size of the 1252 pixel sub column, since the 1252 pixel sub column must have substantially the same area as the 1256 circuit column. The 1252 pixel sub column can have be directly associated with circuit column 1256 through an electrical connection between an interconnection 11224 that electrically connects the pixel reading bus 1230 to the circuit reading bus 1240. The figures show an example of a connection between each sub column of pixels 1252 a its associated circuitry 1270 in a column of circuit 1256 through reading buses 1230 and 1240.
    The figures also show a read bus 1230 per sub column of pixels 1252 and a read bus 1240 per column of circuit 1256. In this embodiment, the associated circuit set 1270 in a column of circuit 1256 is one pixel wide and six pixels wide. length, however it will be assessed that any aspect ratio of the circuit column can be used by the description. As can be seen in figures 12-12c, the columns were divided into two sub columns 1287, 1288. Consequently, the pixel column reading bus 1230 can be manufactured in corresponding pixel sub column reading buses 1230a and 1230b. Each 1287, 1288 pixel sub column can be connected to a 1230a or 1230b pixel column bus first and then to the supporting circuit set 1270 and circuit column 1256, or each sub column 1287, 1288 can connect directly to the circuit set 1270 and circuit column 1256 through its own interconnect 1224a and 1224b, respectively, to an associated circuit bus 1240a and 1240b.
    As noted above, each 1252 pixel sub column can be electrically associated or connected to a 1230 pixel sub column bus, and each 1256 circuit column can be electrically associated
    24/32 da or connected to a circuit column bus 1240. Figures 12a-12c illustrate a perspective view, a front view and a side view, respectively, of a single column of pixels 1252 divided into sub-columns 1287, 1288 and two associated circuit columns 1256 separated from the plurality of pixel columns 1252 and the plurality of circuit columns 1256 illustrated in figure 12. As illustrated in figures 12a-12c, there are two reading buses 1230a, 1230b per column of pixels, thus , this separates the column into two sub-columns. Two support circuits (one support circuit per pixel sub-column reading bus). In this configuration, there is an aspect ratio of the circuit column of 6/1, the aspect ratio of the pixel sub column is also 6/1, and the aspect ratio of the entire column of pixels is 12/1.
    Figures 12a-12c also further illustrate the electrical connection between pixel sub-column buses 1230a and 1230b, pixel sub-columns 1287, 1288 and circuit columns 1256 that use one or more interconnections 1224 per sub-column connection. Although pixel subbuses 1230a and 1230b and busbars 1240a and 1240b can be electrically connected using one or more interconnects 1224, the figures illustrate that interconnections 1224 can be located somewhere along the overlapping path of pixel subbuses 1230a and 1230b and busbars 1240 without abandoning the spirit or scope of the description.
    Figures 13 and 13a illustrate an alternative modality in which the column of pixels has been divided into a plurality of sub-columns, each having its own bus. However, the sub-columns are illustrated as being connected by their individual busbars to a single circuit column.
    Similar to figures 12 - 12c, figures 14 - 14c illustrate a matrix of pixels 1450 being divided into a plurality of columns and sub-columns 1452. The size of the columns and sub-columns may, for example, be based on the size of the associated circuitry 1470 and circuit columns 1456. For example, the pixel sub column 1452 can have a pixel of
    25/32 width and N number of pixels long (in figures 14 - 14c, the pixel sub-columns are illustrated as having one pixel wide and six pixels long, while the entire column is illustrated as having one pixel wide and twelve pixels long) and circuit columns 1456 are illustrated as having an aspect ratio of two pixels wide by three pixels long. It will be appreciated that the size or area of the circuit column 1456 can dictate or direct the size of the pixel sub column 1452, since the pixel sub column 1452 must have substantially the same area as the circuit column 1456. The pixel sub column 1452 can be directly associated with circuit column 1456 through an electrical connection between an interconnect 1424 that electrically connects the pixel reading bus 1430 to the circuit reading bus 1440. The figures show an example of a connection between each sub column of pixels 1452 a its associated circuitry 1470 in a column of circuit 1456 through reading buses 1430 and 1440.
    The figures also show a reading bus 1430 per sub column of pixels 1452 and a reading bus 1440 per column of circuit 1456. In this embodiment, the associated circuit set 1470 in a column of circuit 1456 is two pixels wide and three pixels wide. length, however it will be assessed that any aspect ratio circuit column can be used by the description. As can be seen in figures 14-14c, all columns were divided into two sub-columns 1487, 1488. Consequently, the pixel column reading bus 1430 can be manufactured in corresponding pixel sub column reading buses 1430a and 1430b. Each pixel subcolumn 1487, 1488 can be connected to a pixel column bus 1430a or 1430b first and then to the supporting circuitry 1470 and circuit column 1456, or each subcolumn 1487, 1488 can be directly connected to the set of circuits 1470 and circuit column 1456 through their own interconnection 1424a and 1424b, respectively, to an associated circuit bus 1440a and 1440b.
    As noted above, each 1452 pixel sub-column can
    26/32 can be electrically associated or connected to a sub-column bus of pixels 1430, and each circuit column 1456 can be electrically associated or connected to a column bus circuit 1440. Figures 14a-14c illustrate a perspective view, a front view and side view, respectively, of a single column of pixels 1452 divided into sub-columns 1487, 1488 and two associated circuit columns 1456 separated from the plurality of pixel columns 1452 and the plurality of circuit columns 1456 illustrated in figure 14. As illustrated in figures 14a-14c, there are two reading buses present throughout the column of pixels. However, as illustrated, the presence of two reading buses 1430a, 1430b is illustrated as separate and distinct buses that are not electrically connected to each other, so that there is a separation or divider (as discussed above in relation to figure 11) that separate the column into two sub-columns. Consequently, there can also be two support circuit and column column reading buses (one support circuit bus and circuit column per pixel sub-column reading bus). In this configuration, there is an aspect ratio of the circuit column of 3/2, the aspect ratio of the pixel sub column is also 6/1, and the aspect ratio of the entire pixel column is 12/1.
    Figures 14a-14c further illustrate the electrical connection between pixel sub-column buses 1430a and 1430b of pixel sub-columns 1487, 1488 and circuit columns 1456 using one or more more interconnections 1424 per sub-column connection. Although pixel subbuses 1430a and 1430b and circuit column buses 1440a and 1440b can be electrically connected using one or more interconnects 1424, the figures illustrate that interconnections 1424 can be located somewhere along the overlapping path of the pixel subbars 1430a and 1430b and circuit column buses 1440 without abandoning the spirit or scope of the description.
    Figures 14 - 14c also illustrate how differentiating the aspect ratio between substrates can allow flexibility in bus contact points. In the modality, the circuit bus column
    27/32
    1440 was designed with a general u shape to occupy the 1456 circuit column area more evenly, thus providing options for connecting the 1424 interconnect throughout the 1456 circuit column. Note that the 1430 pixel column bus does not have a generally u-shaped, but the circuit column bus 1440 can be generally u-shaped, so that the same column circuit 1456 can be used with the two adjacent but different pixel column configurations. The first leg of the U-shaped circuit column buses 1440a and 1440b can be superimposed on the reading buses 1430a and 1430b of pixel sub-columns 1487 and 1488 (as illustrated in figure 14a). The second leg of the U-shaped circuit column bus 1442 that is located between the circuit column buses 1440a and 1440b can be superimposed on the reading bus 1430 of the next adjacent pixel column 1452 (as best illustrated in figure 14) . Figures 14a-14c illustrate a single set of pixel sub-columns 1487 and 1488 obtained from the pixel array 1450 of figure 14. It should be noted that due to the fact that the aspect ratio of circuit column 1456 is illustrated as being two pixels of width by three pixels in length, which is half the length of the corresponding pixel subcolumns 1487 and 1488, the interconnect location options 1424 are available only for a portion of the pixel subcolumn length.
    Figure 14b illustrates that for a complex bus format there may be two interconnection path paths along buses 1440a and 1440b in a circuit column 1456 that is twice the width of the pixel subcolumn 1487 and 1488 that it supports . Figure 14b illustrates a front view of the superposition of the first leg of the U-shaped circuit column bus 1440b to the reading bus 1430b of the pixel sub column 1488 and uses the outermost portion of bus 1440b to locate the interconnect 1424 as opposed to innermost portion of bus 1440b as illustrated in figures 14 and 14a to locate interconnection 1424 in the next adjacent pixel column 1452.
    28/32
    Figure 14 illustrates the next pixel sub-column 1452 located on the left and in relation to the pixel sub-columns 1487 and 1488 illustrated in Figures 14a-14c. The bus 1430 of the next pixel sub-column 1452 shown in figure 14 can be electrically connected to a different circuit bus 1442 which can be located between the circuit buses 1440a and 1440b as illustrated. It should be noted that due to the fact that the occupied area of circuit column 1456 has an aspect ratio of 2 pixels wide by 3 pixels in length, the overlap of the sub column bus of pixels 1430 to the circuit column bus 1442 requires that the second leg of the circuit column bus 1442 has a generally u shape to then allow a natural combination or overlap of the bus 1442 in relation to the next pixel sub column 1452 and its corresponding bus (in relation to the sub column 1187) illustrated in figure 14 .
    Figure 15 illustrates a modality and configuration of a matrix of pixels 1810 that has an alternating positioning of interconnection or relief 1824 and sub-columns in a substrate / chip. As noted above, due to the fact that there is a reading bus per 1828 pixel column (or sub-column) and a reading bus per circuit column, and due to the fact that the reading buses move from the top of the column to the bottom of the column. column, and because the pixel columns are divided into sub-columns that have their own pixel column bus, the 1824 interconnect / relief can be positioned anywhere along the overlapping path of the sub column bus and column bus circuit. In the figure, a divider 1866, which can be a physical space or gap or another device to electrically isolate the pixel sub-column and / or the sub-column bus from another sub-column and / or sub-column bus, dividing the column bus from pixels on sub-column pixel buses.
    As can be seen in figure 15, a first 1828 pixel sub-column 1826 can be electrically connected to its corresponding circuit column 1856 through a first interconnection 1824a that
    29/32 is connected to buses 1830 and 1840, and a second sub-column 1828b by a second interconnect 1824b in a similar manner. In the modality, the second column of pixels can be electrically accessed through a second set of sub-column interconnections, which was positioned during manufacture in a sub-column configuration relative to said first column interconnections. As illustrated, the location or position of the second interconnection can be two pixels wide by separating the position of the first interconnection in the X and Y dimensions or directions. A third set of interconnections can then be positioned similarly in a third column of pixels and so on for N number of interconnection sets across the 1810 pixel array.
    Figure 16 illustrates a pixel matrix that is configured so that each column is divided into two sub-columns and then interspersed. The area available to position the support circuits of a first 1881 pixel column is correlated to the pixel sub-column configuration as described above. As further discussed above, the support circuit area is directly correlated to the area of a column of pixels to which it corresponds. In figure 16, the area available for positioning the support circuit can be equal to one pixel unit wide by sixty-four pixel units long, this is shown as the thickest vertical lines in the figure. In addition, each circuit column can be correlated to one of the sub-columns or, alternatively, the circuit column can also be found in a way that corresponds to the column of pixels.
    It should be noted that the exemplary aspect ratio of the support circuit area in figure 16 is illustrated as 1/64. There can be many options for locating or positioning the sub-column interconnections within that area and the final location can then be selected by the designer to allow the desired interconnection spacing for interconnection.
    Figure 17 illustrates a schematically large image sensor that shows the scalability of the principles and instructions in the description.
    30/32
    As can be seen in the figure, the area available for positioning the support circuit can be equal to four pixel units wide by sixty-four pixel units long, this is shown as the thickest vertical lines in the figure. As illustrated, there can be a plurality of interconnections 2516 and 2518 per column of pixels denoting the pixel sub-columns to allow for greater sub-column functionality for larger matrix configurations. Therefore, the interconnection between the substrates must be somewhere in the sub-column pixel unit areas to read the corresponding pixel column. It should be noted that the aspect ratio of the support circuit area in this example is 4/16, the sub-column aspect ratio is 1/64 and the pixel column is 1/128. Therefore, there are sub-columns of pixels per column of pixels. In this example, the frame reading time (a rolling cycle) is half of what it could be if that matrix could not be divided. There are two rows addressed at the same time. The total pixel matrix can be referred to as two independent consistent submatrices. In the modality, this lends itself to the set of support circuits that correspond directly to the pixel sub-columns. The selection of where to position the interconnection has many options within that area and can be performed to allow the desired spacing from interconnection to interconnection. As illustrated in the figure, repeating the methods of that description until the latest imaging sensor technology can be used with these methods.
    Figure 18 illustrates a schematically large image sensor that shows the scalability of the principles and instructions in the description. The plurality of interconnections 2616, 2618 per column indicates that the column of pixels has been divided into sub-columns. As can be seen in the figure, the area available for positioning the support circuit of the pixel sub-columns can be equal to two pixel units wide by thirty-two pixel units long, this is shown as the thickest vertical lines in the figure. Therefore, the interconnection between the substrates must be somewhere in the area of sixty-four pixel units to read the corresponding pixel sub-columns. It should be noted that the ra
    31/32 aspect ratio of the support circuit area is 2/32. The selection of where to position the interconnection has many options within that area and can be performed to allow the desired spacing from interconnection to interconnection. As illustrated in the figure, repeating the methods of that description until the latest imaging sensor technology can be used with these methods.
    It will be appreciated that the structures and devices described here are merely exemplary for optimizing an image forming sensor, and it should be appreciated that any structure, device or system for optimizing an image sensor, which performs functions equal or equivalent to those described here, is intended to be included within the scope of this description, including those structures, devices or systems for imaging, which are currently known, or which may be made available in the future. Anything that works the same way, or equivalent to a means to optimize an imaging sensor is included within the scope of this description.
    Those skilled in the art will appreciate the advantages provided by the characteristics of the description. For example, a potential feature of the description is to provide an optimized imaging sensor, which is simple in design and manufacture. Another potential feature of the description is to provide an image sensor with pixels larger than the total size.
    In the previous Detailed Description, several characteristics of the description are brought together in a single modality for the purpose of simplifying the description or are discussed in different modalities. This method of description should not be interpreted as reflecting an intention that the claimed description requires more features than expressly stated in each claim. Preferably, as the following claims are examined, the inventive aspects are inferior to all the characteristics of a single modality described above and several inventive features described in separate modalities can be combined to form their own modality as claimed more
    32/32 overall below. Accordingly, the following claims are incorporated into that Detailed Description by way of reference, with each claim remaining as a separate modality from the description.
    It will be understood that the provisions described above are only illustrative of the request for the principles of the description. Numerous modifications and alternative dispositions can be planned by the elements versed in the technique without abandoning the spirit and scope of the description and the attached claims are intended to include these modifications and dispositions. Thus, although the description is shown in the drawings and described above with 10 particularities and details, it will be visible by the elements versed in the technique that numerous modifications, including, but without limiting character, variations in size, materials, format, shape, function and manner operation, assembly and use can be done without abandoning the principles and concepts presented here.
    权利要求:
    Claims (27)
    [1]
    1. Imaging sensor comprising:
    a plurality of substrates;
    a pixel array comprising pixels formed in pixel columns;
    wherein said pixel columns are divided into pixel sub-columns that are configured to be read independently via a pixel sub-column bus from one sub-column to another; a plurality of support circuits having a circuit bus;
    wherein a first substrate of the plurality of substrates comprises the pixel array;
    wherein the plurality of support circuits is arranged on a support substrate which is remotely disposed in relation to said first substrate;
    wherein one of said plurality of support circuits is electrically connected to, and in electrical communication with, a corresponding sub-column of said pixel array; and wherein said electrical communication is provided by an interconnection between said first substrate and said support substrate.
    [2]
    2. Imaging sensor according to claim 1, wherein each pixel sub-column bus and each circuit bus are superimposed, so that each pixel sub-column bus and each circuit bus are substantially aligned within a portion of the sub-column; and wherein at least one interconnect provides an electrical connection between each pixel sub-column bus and each circuit bus within the aligned portion of the sub-column.
    [3]
    3. Imaging sensor according to claim 2, in which the electrical connection between a sub-column of pixels and a circuit bus is carried out by a single interconnection.
    [4]
    4. Imaging sensor, according to claim
    2/6 tion 2, in which the electrical connection between a pixel sub-column bus and a circuit bus is made by a plurality of interconnections in which each one between a plurality of interconnections is arranged within the pixel sub-column.
    [5]
    5. Imaging sensor according to claim 1, wherein said imaging sensor has backlight.
    [6]
    An imaging sensor according to claim 1, wherein the plurality of substrates further comprises a plurality of subsequent support substrates.
    [7]
    7. Imaging sensor according to claim 1, wherein each pixel sub-column is electrically isolated from other pixel sub-columns.
    [8]
    8. Imaging sensor according to claim 1, wherein said pixel sub-columns are electrically connected to the same support circuits that are supporting the pixel column where they reside.
    [9]
    An imaging sensor according to claim 1, wherein said support substrate comprises dedicated support circuits corresponding to each pixel sub-column of the pixel array.
    [10]
    10. Imaging sensor according to claim 1, wherein said pixel sub-columns are electrically configured to be read substantially at the same time.
    [11]
    11. Method for accessing data on an imaging sensor comprising:
    electronically connect the pixels in a pixel array located on the first substrate to the support circuits on a second substrate;
    wherein said matrix of pixels is organized in columns of pixels;
    wherein said pixel columns are divided into sub-columns
    3/6 pixels;
    reading a plurality of pixel sub-columns starting with a first pixel in each sub-column and sequentially reading the pixel data of each pixel until the last pixel in the sub-column is read;
    transmitting said pixel data via interconnections to a plurality of corresponding support circuits located on the second substrate and comprising a plurality of circuit columns, wherein the data of a sub-column of pixels is processed by a circuit column corresponding to said sub-column of pixels, process said pixel data in an image.
    [12]
    12. Method for accessing data in an imaging sensor according to claim 11, which further comprises reading the pixel data from each pixel sub-column simultaneously.
    [13]
    13. Method for accessing data in an image-forming sensor according to claim 11, which further comprises transmitting said pixel data to a support circuit corresponding to a plurality of pixel sub-columns within the same pixel column .
    [14]
    14. Imaging sensor comprising:
    a plurality of substrates comprising at least a first substrate and a second substrate;
    a matrix of pixels located on the first substrate and comprising a plurality of pixel columns, each of which between the plurality of pixel columns is defined as one pixel wide and a plurality of pixels long enough to cover the dimension of the matrix;
    wherein said pixel columns are divided into pixel sub-columns so that each pixel sub-column is electrically isolated from other pixel sub-columns;
    a plurality of support circuits located on the second substrate and comprises a plurality of circuit columns, where one
    4/6 circuit column corresponds to a sub-column of pixels, where each of the plurality of circuit columns is defined as having an area that corresponds to an area of a corresponding sub-column of pixels;
    a plurality of buses, where there is a sub-column bus of pixels for at least one sub-column of pixels that resides on the first substrate and a circuit column bus per circuit column that resides on said second substrate;
    wherein at least a portion of each pixel sub-column bus is superimposed with at least a portion of each corresponding circuit column bus and at least one interconnect that provides electrical communication between a pixel sub-column bus and a column bus of corresponding circuit; and wherein said at least one interconnect is located anywhere between a pixel sub-column bus and a corresponding circuit column bus and is superimposed.
    [15]
    An image forming sensor according to claim 14, which further comprises a plurality of interconnections arranged between said substrates and wherein said plurality of interconnections is spaced at a distance that is greater than a distance between pixels of said pixel array.
    [16]
    16. Imaging sensor according to claim 14, wherein the first substrate and the second substrate are in alignment.
    [17]
    The imaging sensor according to claim 14, wherein an area of one of said pixel sub-columns on said first substrate is substantially equal to an area of one of said corresponding circuit columns on said second substrate.
    [18]
    The imaging sensor according to claim 14, wherein said second substrate is substantially the same size as said first substrate.
    [19]
    19. Imaging sensor according to claim 14, in which an area of one of said pixel sub-columns in said
    5/6 the first substrate is greater than an area of one of said corresponding circuit columns on said second substrate.
    [20]
    An image forming sensor according to claim 14, wherein an area of one of said pixel sub-columns on said first substrate is smaller than an area of one of said corresponding circuit columns on said second substrate.
    [21]
    21. The imaging sensor according to claim 14, wherein an aspect ratio of one of said pixel sub-columns is substantially similar to an aspect ratio of one of said circuit columns.
    [22]
    22. Imaging sensor according to claim 14, wherein a plurality of interconnections connect a pixel sub-column bus to a corresponding circuit column bus.
    [23]
    23. Imaging sensor according to claim 14, wherein an aspect ratio of one of said pixel sub-columns is different from an aspect ratio of one of said circuit columns.
    [24]
    24. Imaging sensor according to claim 14, wherein the aspect ratio of at least one of said circuit columns is N pixels wide and 1 / M pixels long of the aspect ratio of said sub-columns of pixels.
    [25]
    The image forming sensor according to claim 14, wherein the aspect ratio of at least one of said circuit columns is twice greater than half the length of the aspect ratio of one of said pixel sub-columns.
    [26]
    26. Imaging sensor according to claim 14, wherein the aspect ratio of at least one of said circuit columns is four times wider and a quarter of the length of the aspect ratio of one of said sub-columns of pixels.
    [27]
    27. Imaging sensor according to claim 14, wherein the aspect ratio of at least one of said columns
    6/6 of circuit is eight times wider and one eighth the length of the aspect ratio of one of said pixel sub-columns.
    类似技术:
    公开号 | 公开日 | 专利标题
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    法律状态:
    2020-06-23| B06F| Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]|
    2020-07-14| B25C| Requirement related to requested transfer of rights|Owner name: OLIVE MEDICAL CORPORATION (US) Free format text: A FIM DE ATENDER O REQUERIDO ATRAVES DA PETICAO NO 870190013465 DE 08/02/2019, ENECESSARIO COMPLEMENTAR A TAXA RECOLHIDA POR MEIO DA GRU 29409161900720247 PARA O VALORCORRESPONDENTE AO SERVICO DE TRANSFERENCIA, UMA VEZ QUE A DOCUMENTACAO APRESENTADA INDICATRANSFERENCIA POR INCORPORACAO. |
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    2020-11-10| B06U| Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]|
    2021-02-09| B25E| Requested change of name of applicant rejected|Owner name: OLIVE MEDICAL CORPORATION (US) |
    2021-02-23| B11B| Dismissal acc. art. 36, par 1 of ipl - no reply within 90 days to fullfil the necessary requirements|
    2021-10-19| B350| Update of information on the portal [chapter 15.35 patent gazette]|
    优先权:
    申请号 | 申请日 | 专利标题
    US201161485426P| true| 2011-05-12|2011-05-12|
    US201161485440P| true| 2011-05-12|2011-05-12|
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