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    • 专利摘要:
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME. The present invention relates to an anode region 106 formed in the bottom portion of a trench 105 in which a gate electrode 108 is formed or in a drift region 102 immediately under trench 105. A contact hole 110 is formed in the trench 105 at a depth that reaches the region of anode 106. A source electrode 112 is embedded in the contact hole 110, at the same time interspersing an insulating film between the inner wall between them. The anode region 106 and the source electrode 112 are electrically connected to each other in an isolated state from the port electrode 108 by the insulating film of the inner wall 111.
    公开号:BR112013027105B1
    申请号:R112013027105-1
    申请日:2012-02-24
    公开日:2021-01-12
    发明作者:Shigeharu Yamagami；Tetsuya Hayashi；Taku Shimomura
    申请人:Nissan Motor Co., Ltd.；
    IPC主号:
    专利说明:

    [0001] [001] The present invention relates to a semiconductor device that includes a transistor and a diode and its method of manufacture. Fundamentals of Technique
    [0002] [002] So far, as this type of technology, for example, is known to that described in the literature presented below (see and Patent Literature: Japan Patent Open to Public Inspection No. 2005-183563). This literature describes a semiconductor device technology including: a trench-type transistor in which a gate electrode is embedded in a trench; and a diode in which a straight semiconductor region is used as an anode and a drift region is used as a cathode. The straight semiconductor region that makes up the diode anode is arranged along such gate electrodes, which are adjacent to each other, at a predetermined interval in order to remain sandwiched between the gate electrodes of interest. Summary of the Invention
    [0003] [003] In the conventional semiconductor device described above, the hetero semiconductor region is arranged in the direction of a plane of the semiconductor substrate in relation to the gate electrodes so as to be adjacent to the gate electrodes. That is, a region in which the straight semiconductor region will be formed is necessary in the direction of the plane of the semiconductor substrate. As a result, the efficiency of an element's area on the semiconductor substrate is low, and this has been an obstacle in the case of increasing the degree of integration.
    [0004] [004] In this regard, the present invention was designed in consideration of the mentioned problem. An objective of the present invention is to provide a semiconductor device in which the degree of integration is improved by increasing the efficiency of the area, and to provide a method for its manufacture.
    [0005] [005] To solve the above problem, the present invention is characterized by the fact that a region of the anode is formed at the bottom of a trench in which a gate electrode is formed or in a drift region immediately below the trench, that a contact orifice is formed in the trench at a depth that reaches the anode region, that a source electrode is embedded in the contact orifice, while interposing, between them, an insulating film of the inner wall, and that the anode region and the source electrode are electrically connected to each other in an isolated state from the door electrode by the insulating film of the inner wall. Brief Description of the Drawings:
    [0006] [006] Figure 1 is a cross-sectional view showing a configuration of a semiconductor device in accordance with Modality 1 of the present invention.
    [0007] [007] Figure 2A is a cross-sectional view of the process, showing a method of manufacturing the semiconductor device according to Modality 1 of the present invention.
    [0008] [008] Figure 2B is a cross-sectional view of the process, showing the method of manufacturing the semiconductor device according to Modality 1 of the present invention.
    [0009] [009] Figure 2C is a cross-sectional view of the process, showing the method of manufacturing the semiconductor device according to Modality 1 of the present invention.
    [0010] [010] Figure 2D is a cross-sectional view of the process, showing the manufacturing method of the semiconductor device according to Modality 1 of the present invention.
    [0011] [011] Figure 2E is a cross-sectional view of the process, showing the method of manufacturing the semiconductor device according to Modality 1 of the present invention.
    [0012] [012] Figure 2F is a cross-sectional view of the process, showing the method of manufacturing the semiconductor device according to Modality 1 of the present invention.
    [0013] [013] Figure 2G is a cross-sectional view of the process, showing the manufacturing method of the semiconductor device according to Modality 1 of the present invention.
    [0014] [014] Figure 2H is a cross-sectional view of the process, showing the method of manufacturing the semiconductor device according to Modality 1 of the present invention.
    [0015] [015] Figure 2I is a cross-sectional view of the process, showing the method of manufacturing the semiconductor device according to Modality 1 of the present invention.
    [0016] [016] Figure 2J is a cross-sectional view of the process, showing the method of manufacturing the semiconductor device according to Modality 1 of the present invention.
    [0017] [017] Figure 3 is a cross-sectional view showing a configuration of a semiconductor device in accordance with Modality 2 of the present invention.
    [0018] [018] Figure 4A is a cross-sectional view of the process, showing a method of manufacturing the semiconductor device according to Modality 2 of the present invention.
    [0019] [019] Figure 4B is a cross-sectional view of the process, showing a method of manufacturing the semiconductor device according to Modality 2 of the present invention.
    [0020] [020] Figure 4C is a cross-sectional view of the process, showing the method of manufacturing the semiconductor device according to Modality 2 of the present invention.
    [0021] [021] Figure 5 is a plan view showing a configuration of a semiconductor device in accordance with Modality 3 of the present invention.
    [0022] [022] Figure 6 is a plan view showing another configuration of the semiconductor device according to Modality 3 of the present invention.
    [0023] [023] Figure 7 is a plan view showing another configuration of the semiconductor device according to Modality 3 of the present invention.
    [0024] [024] Figure 8 is a plan view showing another configuration of the semiconductor device according to Mode 3 of the present invention.
    [0025] [025] Figure 9 is a plan view showing a configuration of a semiconductor device in accordance with Modality 4 of the present invention.
    [0026] [026] Figure 10 is a plan view showing another configuration of the semiconductor device according to Mode 4 of the present invention.
    [0027] [027] Figure 11 is a plan view showing another configuration of the semiconductor device according to Mode 4 of the present invention. Description of Modalities
    [0028] [028] From the drawings, the modalities for carrying out the invention will be described. (Mode 1)
    [0029] [029] Figure 1 is a view showing a configuration of a semiconductor device in accordance with Mode 1 of the present invention. The Mode 1 semiconductor device, which is shown in Figure 1, is formed using a silicon carbide semiconductor substrate and including a MOSFET and a diode. In Figure 1, on one of the main surfaces of a high concentration semiconductor substrate (type N +) of type N 101 of silicon carbide, a drift region 102 is formed composed of a low concentration epitaxial layer of type N (type N ') made of silicon carbide.
    [0030] [030] On one of the main surfaces (ie, a front surface) of drift region 102, a cavity region of type P 103 and a source region of type N + 104 are formed. In addition, a trench 105 is formed with a depth that penetrates the region of cavity type P 103 and the source region of type N + 104 and reaching drift region 102. In drift region 102 immediately under trench 105, a anode region 106 is formed by the selective introduction of impurities, and an upper surface of anode region 106 forms a bottom surface of trench 105. This region of anode 106 is formed of a type P conductor in Mode 1, composes a diode type PN junction on a junction surface with the type N drift region, and functions as anode of this diode.
    [0031] [031] On a lateral surface of the trench 105 and a bottom portion of the trench 105, an insulating film of door 107 is formed in order to contact the drift region 102, the cavity region 103 and the source region 104. On a lateral surface of the trench, a port electrode 108 is embedded while interleaving the insulating film of port 107 between them. An insulating film between layers 109 is formed on the upper surface of the door electrode 108, and lines the door electrode 108.
    [0032] [032] In trench 105, a contact orifice 110 is formed so as to be surrounded by the port electrode 108. In the contact orifice 110, a source electrode 112 is formed, while interposing an insulating film between the inner wall between them 111 that lines a lateral surface of the port electrode 108. The source electrode 112 is formed in the source region 104 and in the insulating film between layers 109. This source electrode 112 connects the source region 104 and the anode region 106 with each other in ohmic contact with low electrical resistance. The source electrode 112 and the port electrode 108 are isolated from each other by the insulating film between layers 109 and by the insulating film of the inner wall 111.
    [0033] [033] On the other main surface (ie the back surface) of the semiconductor substrate 101, a drain electrode 113 is formed in order to connect to it in ohmic contact with low electrical resistance.
    [0034] [034] Next, using the cross-sectional views of Figures 2A to 2J, a method of manufacturing the semiconductor device according to Mode 1 is described.
    [0035] [035] First, in a process shown in Figure 2A, on this main surface of the semiconductor substrate of type N + 101, the drift region 102 is formed, composed of the epitaxial layer of silicon carbide. Silicon carbide has some polytypes (crystal polymorphisms), and here, the description is made on the premise that it is the typical 4H polytype. The thickness of the semiconductor substrate 101 ranges from approximately a few dozen to several hundred microns. The drift region 102 is formed, for example, with the impurity concentration range between 1E14 to 1E18cm-3 and thickness in the range of several micrometers to tens of micrometers.
    [0036] [036] Next, in a process shown in Figure 2B, the cavity region 103 and the source region 104 are formed in the drift region 102 by ion implantation. A mask material can be formed in the drift region 102 by a process, which is shown below, in order to stamp an ion implanted region. For example, a silicon oxidation film can be used as a mask material, and as a deposition method, a thermal CVD method and a plasma CVD method can be used.
    [0037] [037] Next, a resistor is stamped (not shown) on the mask material. As a printing method, the general photolithography method can be used. The mask material is selectively removed by caustication using the stamped resistor as a mask. As a caustication method, wet etching using hydrofluoric acid and dry etching, such as reactive ions etching, can be used.
    [0038] [038] After the mask material is selectively removed by caustication, the resistor is removed by oxygen plasma, sulfuric acid and similar methods. When using the stamped resistor as a mask, impurities of type N and type P are implanted by ions, and the cavity region of type P 103 and the source region of type N + 104 are formed. As impurities of type P, for example, aluminum and boron can be used. As type N impurities, nitrogen can be used. At this time, such ions are implanted in a state in which the semiconductor substrate 101 is heated to about 600 ° C, and thereby preventing the crystal defect from occurring in the implanted region.
    [0039] [039] After the ion implantation, the mask material is removed, for example, by wet etching with hydrofluoric acid. After that, the impurities implanted by the ion are activated by carrying out the heat treatment for this purpose. As a heat treatment temperature, a temperature of approximately 1700 ° C can be used, and as an atmosphere, the use of argon and nitrogen is convenient. This heat treatment process can be implemented after the process shown in Figure 2D and described later.
    [0040] [040] Next, in a process shown in Figure 2C, trench 105 is formed in the drift region 102. First, the mask material 201, an insulating film stamped in a manner similar to the process previously shown in Figure 2B, can be used. Thereafter, trench 105 is formed using the mask material 201 as a mask. As a method for forming the trench, the dry etching method is used properly. The depth of trench 105 is adjusted to a depth that penetrates the region of cavity 103 and the region of source 104 and reaches the region of drift 102.
    [0041] [041] Next, in a process shown in Figure 2D, the anode region of type P 106 is selectively formed in the drift region 102 immediately under trench 105. As a method of forming the anode region 106, ion implantation can be used. As a mask at the time of ion implantation, the mask material 201 used in the process previously shown in Figure 2C can be used. In this way, in the drift region 102 immediately under trench 105, the anode region 106 can be selectively formed in self-alignment. The ionic species for use in ion implantation and the substrate temperature are similar to the process previously shown in Figure 2B, and are therefore omitted here.
    [0042] [042] Next, in a process shown in Figure 2E, on the top surface of anode region 106 (ie, bottom surface of trench 105), on the side surface of trench 105 and in the source region 104, the insulating film of door 107 is deposited and formed, for example, with a thickness in the range of about 100 to 1000 A. As insulating film of door 107, a silicon oxidation film can be used properly, and as a deposition method, a method of thermal oxidation, thermal CVD method, plasma CVD method, sputtering method and other similar methods are used.
    [0043] [043] After the insulating film of door 107 is deposited and formed, the annealing treatment can be carried out at an approximate temperature of 1000 ° C in an atmosphere of nitrogen, argon, N2O and the like in order to reduce the state of the interface between the cavity region 103 and the door insulating film 107.
    [0044] [044] Subsequently, the polycrystalline silicon 202 containing introduced impurities, which becomes the door electrode 108, is deposited and formed in the trench 105 and in the source region 104 at the same time interleaving the door insulating film 107 between them. As a deposition method, it is possible to use the general low pressure CVD method.
    [0045] [045] Next, in a process shown in Figure 2F, the entire surface of polycrystalline silicon 202 is etched again, and polycrystalline silicon 202 in one region, except the interior of trench 105, is removed. Alternatively, a resistor stamping is formed on polycrystalline silicon 202, and using this resistor stamping as a mask, polycrystalline silicon 202 is selectively removed and stamped, for example, using dry etching. In this way, polycrystalline silicon 202 in the region, except for the interior of trench 105, is removed.
    [0046] [046] Next, in a process shown in Figure 2G, the insulating film between layers 109 is selectively formed on polycrystalline silicon 202. As an insulating film between layers 109, a silicon oxidation film is used appropriately. As a forming method, insulating film between layers 109 can be formed by thermally oxidizing polycrystalline silicon 202 selectively. The rate of thermal oxidation of polycrystalline silicon is faster than that of silicon carbide. Consequently, in the case of performing thermal oxidation for polycrystalline silicon 202, the insulating film between layers 109 can be formed on polycrystalline silicon 202 in an self-aligned manner. Alternatively, first, the insulating film between layers 109 is deposited using the thermal CVD method, plasmatic CVD method, sputtering method and other similar methods, and the resistor stamp is formed on the deposited insulating film between layers 109. Thereafter, using this stamping of the resistor as a mask, the insulating film between layers 109 in the source region 104 can be selectively removed.
    [0047] [047] Next, in a process shown in Figure 2H, the contact orifice 110 is opened and formed in the insulating film between layers 109 and in the polycrystalline silicon 202. As a formation method, dry etching can be used using a mask , resistor stamped by photolithography. In this way, port electrode 108 produced from polycrystalline silicon is formed to surround contact hole 110. Figure 2H illustrates the case where the insulating film of port 107 is left in the bottom portion of contact hole 110. At the same time time, an upper surface of part of the anode region 106 can be exposed by selectively removing, by caustication, the insulating film of port 107 in the bottom portion of the contact orifice 110.
    [0048] [048] Next, in a process shown in Figure 2I, the insulating film of the inner wall 111 is formed on the inner wall of the contact hole 110, that is, on the side surface to which the port electrode 108 is exposed. As a method of formation, the insulating film of the inner wall 111 can be formed by thermally oxidizing the gate electrode 108 produced in polycrystalline silicon. Alternatively, the insulating film of the inner wall 111 can be deposited and formed using the thermal CVD method, plasma CVD method, sputtering method and other similar methods.
    [0049] [049] Next, in a process shown in Figure 2J, the surface of anode region 106 immediately under contact orifice 110 is selectively exposed. As a method of exposure, the insulating film of door 107 in the bottom portion of the contact orifice 110 is selectively removed by anisotropic dry etching.
    [0050] [050] At this time, the insulating film between layers 109 is formed with a greater thickness before the insulating film of door 107 left on the bottom surface of the contact hole 110 and than the insulating film of the inner wall 111. Thus, the interlayer insulating film 109 can be left even after the door insulating film 107 left on the bottom surface of contact hole 110 is etched. Furthermore, when using anisotropic dry etching, it is possible to selectively remove, by etching, the insulating film of door 107 in the bottom portion of trench 105 without etching the insulating film of the inner wall 111 on the inner wall of the contact hole 110. When In order to implement the process described above, the contact hole 110 can be formed in the trench 105 in an upright manner to be surrounded by the port electrode 108.
    [0051] [051] Then, the source electrode 112 is deposited and formed in order to connect to the region of cavity 103, the region of source 104 and the region of anode 106 in ohmic contact with low electrical resistance. Furthermore, the drain electrode 113 is deposited and formed on the other of the main surfaces of the semiconductor substrate 101.
    [0052] [052] As source electrode 112 and drain electrode 113, nickel silicide is used properly; however, cobalt silicate alloys, titanium silicate and similar substances can be used. As a deposition method, the evaporation method, sputtering method, CVD method and the like can be used. In addition, the electrode structure with stacked structure, in which titanium and aluminum are stacked on source electrode 112 or drain electrode 113, can be adopted. As a method of forming nickel silicide, nickel is first deposited and then annealed at a temperature of 1000 ° C, the liquid forming an alloy with silicon carbide.
    [0053] [053] Upon being submitted to the processes described above, the semiconductor device according to Mode 1, which is shown in Figure 1, is finalized.
    [0054] [054] The following describes the basic operations on the semiconductor device with the configuration shown in Figure 1.
    [0055] [055] The semiconductor device with the configuration shown in Figure 1 controls a potential of gate electrode 108 in the state where a predetermined positive potential is applied to drain electrode 113, while taking a potential from source electrode 112 as a reference, and thus acting as a transistor. That is, when the voltage between the port electrode 108 and the source electrode 112 is regulated at a predetermined threshold voltage or above it, an inversion layer is formed in the channel region of the cavity region 103 on the side surface of the door electrode 108. In this way, the transistor triggers the ON state, and current flows from the drain electrode 113 to the source electrode 112.
    [0056] [056] Meanwhile, when the voltage between the port electrode 108 and the source electrode 112 is regulated as the predetermined threshold voltage or below it, the inversion layer disappears, and the transistor triggers the OFF state, and the current is interrupted . In this state, a voltage of several hundred to several thousand is applied between the drain and the source, depending on the voltages applied to the source electrode 112 and the drain electrode.
    [0057] [057] In the case where a predetermined negative potential is applied to the drain electrode 113 while taking as reference the source electrode 112, a reflux current flows through a diode in which the P 103 cavity region and the anode region 106 is used as an anode, and the drift region of type N 102 is used as a cathode. That is, this diode will work as a reflux diode.
    [0058] [058] As previously described, in Mode 1 described above, anode region 106 is formed in drift region 102 immediately under trench 105, and thus drift region 102 immediately under trench 105 can be used as formed region reflux diode. Thus, in comparison with the case of formation of the diode in the direction of the plane in relation to the substrate along the gate electrode as before, the efficiency of the substrate area in the hypothesis of element formation can be improved. Therefore, it is possible to increase the degree of integration of the semiconductor device that includes the reflux diode and transistor.
    [0059] [059] Furthermore, through the contact hole 110 formed in order to penetrate the port electrode 108, the anode region 106 formed in the drift region 102 immediately under the trench 105 and the source electrode 112 are connected together in resistance electrically low. In this way, it may be possible to reduce the parasitic resistance between the region of anode 106 and the source electrode 112, and a low loss semiconductor device, in which the loss at the time of a reflux operation is reduced, can be provided.
    [0060] [060] In general, in the case of a MOSFET formed on a silicon carbide substrate, an electric drain field is larger than a MOSFET formed on silicon substrate, and accordingly, until then, the countermeasure of make the bottom part thicker. Therefore, the ON resistance of the MOSFET has been deteriorated.
    [0061] [061] In contrast, in Mode 1 described above, anode region 106 is formed in drift region 102 immediately under trench 105, and with this, the electric field of the drain to be applied to the bottom portion of the insulating film of port 107 when the MOSFET is OFF, it can be relaxed. As a result, the low loss semiconductor device including the reflux diode can be supplied, while suppressing the deterioration of the ON resistance of the MOSFET.
    [0062] [062] In general, it is difficult to form a low resistance P-type region in silicon carbide. In addition, in order to relax the electric field of the drain, a concentration gradient is required, in which the bottom portion of the type 106 anode region is regulated in low concentration, and its upper portion is regulated in high concentration. Therefore, if only the anode 106 region is formed in the drift region 102 immediately under trench 105, the blade resistance in the anode 106 region towards the depth of Figure 1 is increased, with the parasitic resistance deteriorating, occurring, which is caused by a variation in the plane of the reflux current and the resistance of the blade.
    [0063] [063] In contrast, in Mode 1 described above, the anode 106 region is connected directly to the source electrode 112 at low resistance immediately above it and, accordingly, it is possible to suppress the variation in the plane of the reflux current.
    [0064] [064] The diode that uses anode 106 as an anode is a PN junction type diode and, accordingly, has the same threshold voltage as the PN junction type diode formed in cavity region 103 and drift region 102. Therefore, a uniform reflux current flows in the plane at the time of the reflux operation, and thus, the occurrence of current variation can be suppressed.
    [0065] [065] In Modality 1 described above, first, trench 105 is formed, with a depth that penetrates into the cavity region 103 and the source region 104 and reaching the drift region 102. Then, the anode region 106 is formed in the drift region 102 immediately under the trench 105. Then, the door electrode 108 is embedded in the trench 105, while interposed between the insulating film of door 107, and in the door electrode 108, the contact hole 110 that exposes the surface of the anode 106 region is formed. Thereafter, the source electrode 112 to be electrically connected to the anode region 106 in the isolated state of the door electrode 108 by the insulating film between layers 109 is embedded and formed in the contact hole 110. When subjected to the manufacturing processes described above, the reflux diode can be formed in the drift region 102 immediately under the trench 105. In this way, compared to the case of formation of the diode in the direction of the plane in relation to the substrate along the gate electrode as before, the efficiency of the substrate area in the hypothesis of element formation can be improved. Therefore, it is possible to provide a manufacturing method to increase the degree of integration of the semiconductor device that includes the reflux transistor and diode.
    [0066] [066] In the contact hole 110 formed in the door electrode 108 in the trench 105, the source electrode 112 is embedded and formed, while interposing, between them, the insulating film of the inner wall 111, with which it is possible to electrically connect to each other the anode region 106, which is formed in the drift region 102 immediately under trench 105, and the source region 104 in the isolated state of gate electrode 108. In this way, anode region 106 and source electrode 112 can be connected to each other in low resistance in the isolated state of gate electrode 108. As a result, it is possible to provide a manufacturing method capable of making the low loss semiconductor device.
    [0067] [067] The insulating film between layers 109 is formed with a greater thickness before the insulating film of door 107 left on the bottom surface of the contact hole 110 and than the insulating film of the inner wall 111. In this way, the insulating film between layers 109 can be left even after the door insulating film 107 left on the bottom surface of the contact hole 110 is etched. As a result, the diode can be formed immediately under trench 105 with proper control.
    [0068] [068] In the case of etching the insulating film of door 107 left on the bottom surface of the contact orifice 110, anisotropic dry etching is used. In this way, without causticistically removing the insulating film from the inner wall 111 on the inner wall of the contact hole 110, the insulating door film 107 can be selectively removed, and the surface of the anode region 106 can be exposed. As a result, it is possible to form the contact orifice 110 in a self-aligned manner, and this low loss semiconductor device, in which the diode is formed in the drift region 102 immediately under the trench 105, can be formed with proper control. (Mode 2)
    [0069] [069] Figure 3 is a cross-sectional view showing a configuration of a semiconductor device in accordance with Modality 2 of the present invention.
    [0070] [070] Mode 2 is different from Mode 1 in that an anode region 106 is formed in the bottom portion of trench 105, and because this anode region 106 is formed from a type of material other than carbide of silicon that makes up the drift region 102. Other basic configurations and operations are similar to those shown in Modality 1 already mentioned, and therefore are omitted in this case.
    [0071] [071] Although the anode 106 region of Mode 1 mentioned above is formed in the drift region 102 immediately under trench 105, the region of anode 106 of Mode 2 is formed in the bottom portion of trench 105.
    [0072] [072] As a distinct type of material that makes up the anode 106 region, the following can be used: metallic materials such as titanium, aluminum, nickel, molybdenum; or semiconductor materials, for example, polycrystalline silicon, which is different in the energy range of drift region 102. In the case where anode region 106 is formed of metallic material, a Schottky junction is formed on the junction surface between the region anode 106 and drift region 102, and a Schottky diode is formed by both. This Schottky diode has the function of flowing the reflux current in a similar way to the PN junction type diode described in Modality 1 mentioned above.
    [0073] [073] At the same time, the Schottky diode is a unipolar diode, capable of forming a low loss diode in which the reverse recovery charge is suppressed in relation to the Mode 1 diode (bipolar diode).
    [0074] [074] Next, using Figures 4A to 4C, the method of manufacturing a semiconductor device will be described in the event of formation of the polycrystalline silicon anode 106 region. Note that the processes prior to the process shown in Figure 4A are similar to the processes shown in Figure 2A and Figure 2B of Mode 1 already mentioned.
    [0075] [075] After the process shown in Figure 2B has been completed, in the processes shown in Figure 4A, trench 105 is formed using the mask material 201 in a similar manner to the process shown in Figure 2C previously presented. At this point, if a depth at which the anode region 106 has to be formed is similar to the depth of Figure 2C, in this case, a different point from the processes shown in Figure 2C is that trench 105 is formed more deeply than trench 105 formed in the process shown in Figure 2C. The reason for this is that anode region 106 is formed in the bottom portion in trench 105 in this Mode 2, while anode region 106 is formed in drift region 102 immediately under trench 105 in Mode 1 mentioned above.
    [0076] [076] Next, in the process shown in Figure 4B, polycrystalline silicon 401 is deposited and formed on the entire surface of the semiconductor device in order to be loaded into trench 105. As a deposition method, the general low pressure CVD method can be used.
    [0077] [077] Next, in a process shown in Figure 4C, the entire surface of the polycrystalline silicon 401 thus deposited and formed is again etched, and the mask material used in the process shown in Figure 4A above and the polycrystalline silicon 401 in one region , except the bottom portion of trench 105, are selectively removed. In this way, the region of anode 106 produced in polycrystalline silicon 401 as a separate material is formed in the bottom portion of trench 105.
    [0078] [078] The processes below are similar to the process shown in Figure 2E of Modality1, mentioned above, and will be omitted below.
    [0079] [079] As described above, in Mode 2 already discussed, the anode 106 region, with a function similar to that of Mode 1 mentioned above, is formed in the bottom portion of trench 105 and, thus, effects similar to those obtained in Mode 1 can be achieved.
    [0080] [080] Furthermore, in this Modality 2, the anode 106 region is formed from a material different from the silicon carbide of the drift region 102, and with that the unipolar dio-do is formed between the anode 106 region and the drift 102. The unipolar diode can suppress the reverse recovery load in relation to the Mode 1 diode (bipolar diode) mentioned above. In this way, it is possible to provide a semiconductor device including a low loss diode.
    [0081] [081] Also, the anode 106 region is formed of polycrystalline silicon. Thus, a hetero junction through the junction of different semiconductors in the energy gap is formed on the surface of the junction between the anode region 106 and the drift region 102. As a result, a diode of the hetero junction type is formed, in which the region of anode 106 produced in polycrystalline silicon is used as an anode and the drift region 102 of silicon carbide is used as a cathode. Such a silicon carbide hetero junction diode operates with the unipolar diode, for example, as described in Japan Patent Patent No. 4211642. Therefore, in comparison with the Mode 1 diode mentioned above, it is possible to suppress the reverse recovery charge, and the semiconductor device including the low loss diode can be provided.
    [0082] [082] The anode region 106 is formed of polycrystalline silicon, and thus, in comparison with the case of the formation of anode region 106 in metal or alloy, the metallic contamination of the insulating film of door 107, the state of interface and can be prevented from increasing.
    [0083] [083] Silicon oxidation film can be formed by oxidizing polycrystalline silicon. Thus, in the case where the door insulating film 107 is formed by thermal oxidation, the side surface and the bottom surface of the door insulating film 107 can be formed from the same silicon oxidation film. As a result, it is possible to suppress the concentration of the electric field due to the de-continuity of the materials forming the door insulating film 107, which allows to provide a highly reliable semiconductor device. (Mode 3)
    [0084] [084] Figures 5 to 8 are plan views showing diagrams in the direction of the plane (direction of the main surface of a semiconductor substrate) of a semiconductor device according to Modality 3 of the present invention.
    [0085] [085] Figures 5 to 8 are seen from the states seen when the source electrode 112 of the semiconductor device shown in Figure 1 is removed, and a cross section along line AA in Figure 5 corresponds to the cross section shown in Figure 1. In each of the exemplary schemes shown in Figures 5 to 8, the contact holes 110 formed in the trenches 105 are ordered intermittently (discretely). Here, the following description is carried out by defining, at the same time, in each of Figures 5 to 8, a lateral direction of a blade surface in relation to the plane (main surface) of the semiconductor substrate 101 as an X direction, and a longitudinal direction as Y direction.
    [0086] [086] In a configuration shown in Figure 5, a plurality of trenches 105 are formed continuously (linearly) in the Y direction on the plane (main surface) of the semiconductor substrate 101, arranged discreetly and parallel to each other in the X direction. contact 110 formed in the trenches 105 adjacent to each other are arranged linearly in the X direction. The trenches 105 are formed so that one of their widths (W1), in the portions in which the contact holes 110 are formed, can be wider than one width (W2) in the portions where the contact holes 110 are not formed (W1> W2).
    [0087] [087] Adopting this configuration, in addition to the effects obtained in Modes 1 and 2 already mentioned, it is possible to increase the length (width of the transistor channel) of the peripheries of the trenches 105, while maintaining a distance (L1) between the trenches 105 and the contact holes in a predetermined value according to similar specifications and indications. In this way, it is possible to reduce the ON resistance of the MOSFET, and the low loss semiconductor device can be supplied. Here, the distance (L1) between the trenches and the contact holes is the distance between the side surfaces of the trenches and the side surfaces of the contact holes.
    [0088] [088] In the configuration shown in Figure 6, with respect to the configuration shown in Figure 5, the contact holes 110 formed in the individual trenches 105 adjacent to each other are arranged alternately (not in opposition to each other). Other details are similar to the configuration in Figure 5.
    [0089] [089] By adopting this configuration, in comparison to the configuration shown in Figure 5, it is possible to shorten a door step (L3) in comparison to the configuration shown in Figure 5 above, still maintaining an electrode distance between ports (L2) similar to that of configuration shown in Figure 5. Thus, compared to the configuration shown in Figure 5, the degree of integration of the semiconductor device can be further improved. In addition, it is possible to reduce the ON resistance of the MOSFET, and the low loss semiconductor device can be supplied. Here, as shown in Figure 5 and Figure 6, the electrode distance between doors (L2) is the distance between the door electrodes 108 formed in the trenches 105 adjacent to each other, and the door step (L3) is the distance between the centers of the trenches 105 adjacent to each other.
    [0090] [090] In the configuration shown in Figure 7, trenches 105 are formed in a reticulated manner. In this lattice, each section is quadrangular in shape as shown in Figure 7. The contact holes 110 are arranged at individual intersections of the lattice (that is, in the portions where the intersection between the longitudinal and lateral trenches 105 occurs).
    [0091] [091] Adopting this configuration, it is possible to increase the density of the reticle, while maintaining the distance (L1) between the trenches and the contact holes at the value predetermined by the specifications or similar indications. In this way, the degree of integration of the semiconductor device can be improved. Furthermore, it is possible to reduce the ON resistance of the MOSFET, and the low loss semiconductor device can be formed with satisfactory control.
    [0092] [092] In the configuration shown in Figure 8, trenches 105 are formed in a reticulated manner similar to Figure 7 shown above; however, the configuration shown in Figure 8 is different from that shown in Figure 7, as the shape of each section of the grid is hexagonal. The contact holes 110 are arranged at individual vertices of the lattice (i.e., at the portions where the trenches 105 intersect).
    [0093] [093] Adopting this configuration, it is possible to increase the density of the label, while maintaining the distance (L1) between the trenches and the contact holes at the value predetermined by the specifications or similar indications. In this way, the degree of integration of the semiconductor device can be improved. Furthermore, it is possible to reduce the ON resistance of the MOSFET, and the low loss semiconductor device can be formed with satisfactory control.
    [0094] [094] Note that, although the description above illustrates the case where the shape of each section is quadrangular or hexagonal, the section can assume other polygonal or circular shapes. In that case, the contact holes 110 can be arranged at the vertices of a polygon or along the circumference of a circle. (Mode 4)
    [0095] [095] Figures 9 to 11 are plan views showing diagrams in the direction of the plane (direction of the main surface of a semiconductor substrate) of a semiconductor device according to Modality 4 of the present invention.
    [0096] [096] Figures 9 to 11 are seen from the states seen when the source electrode 112 of the semiconductor device shown in Figure 1 is removed. Although the contact holes 110 are arranged discretely in Figures 5 to 8, which are shown above, the contact holes 110 are formed continuously in each of the exemplary diagrams shown in Figures 9 to 11.
    [0097] [097] In the configuration shown in Figure 9, contact holes 110 are formed in straight lines along the inside of trenches 105 formed in the longitudinal direction of a blade surface.
    [0098] [098] Adopting this configuration, the contact holes 110 are formed continuously and, therefore, the regions of anode 106 can connect to the regions of the source electrodes 112 continuously embedded in the contact holes 110 immediately above them. In this way, the contact area between the anode 106 regions and the source electrodes 112 is increased, and both can be mutually connected at low resistance. As a result, it is possible to provide a low loss semiconductor device in which the ON resistance of the diode is reduced.
    [0099] [099] In the configuration shown in Figure 10, trenches 105 are formed in a reticulated manner, where each section is quadrangular like the case shown in Figure 7 above, and the contact holes 110 are formed continuously in a reticulated manner along the parts reticulated trenches 105.
    [0100] [0100] In the configuration shown in Figure 11, trenches 105 are formed in a reticulated manner, where each section is hexagonal as in the case shown in Figure 8 above, and the contact holes 110 are also formed continuously in a reticulated manner along the internal parts of the reticulated trenches 105.
    [0101] [0101] Adopting this configuration, the contact holes 110 are formed continuously and, therefore, the regions of anode 106 can connect to the regions of the source electrodes 112 continuously embedded in the contact holes 110 immediately above them. In this way, the contact area between the anode 106 regions and the source electrodes 112 is increased, and both can be mutually connected at low resistance. As a result, it is possible to provide a low loss semiconductor device in which the ON resistance of the diode is reduced.
    [0102] [0102] As above, in the respective Modalities 1 to 4 mentioned above, while a unit cell is illustrated in each cross-sectional view of the semiconductor devices, a structure in parallel connection can be formed in which a plurality of unit cells is aggregated and repeated . Furthermore, a relaxation structure of the electric field of a protection ring or a termination structure can be provided in the most peripheral portion of the device.
    [0103] [0103] This application claims priority based on Japan Patent Application No. 2011-092962 filed on April 19, 2011, and the content of this application is incorporated into the specification of the present invention by means of this quotation. Industrial Applicability
    [0104] [0104] According to the present invention, the anode region is formed in the bottom portion of the trench in which the door electrode is formed or in the drift region immediately under the trench. Accordingly, with respect to the gate electrode, the diode can be formed in the vertical direction of the substrate. As a result, the efficiency of the element area on the semiconductor substrate is improved, and thus the degree of integration can be improved.
    权利要求:
    Claims (2)
    [0001]
    Semiconductor device comprising: a semiconductor substrate (101); a drift region (102) of the first type of conductivity formed on one of the main surfaces of the semiconductor substrate; a cavity region (103) of the second type of conductivity formed in the drift region; a source region (104) of the first type of conductivity formed in the cavity region; a trench (105) with a depth penetrating the source region and the cavity region and reaching the drift region; a door electrode (108) formed on a lateral portion of the trench, while interposing, between them, a door insulating film (107); a source electrode (112) connected to the cavity region and the source region; a drain electrode (113) connected to another of the main surfaces of the semiconductor substrate; an insulating film between layers (109) which is formed on the door electrode and covers the door electrode; an anode region (106) formed in a bottom portion of the trench; a contact orifice (110) formed at a depth that reaches the anode region in the trench; and an insulating film of the inner wall (111) formed on a lateral surface of the inner wall of the contact hole while in contact with the door electrode, where the source electrode (112) is embedded in the contact hole (110) while interposing the insulating film of the inner wall (111) between the source electrode (112) and the door electrode (108), being electrically connected to the anode region (106) in an isolated state of the door electrode (108) by the insulating film of the inner wall (111), wherein the trench (105) is formed in a reticulated form with respect to a direction of the main surface of the semiconductor substrate (101), and CHARACTERIZED by the fact that the anode region (106) is formed from a different semiconductor in the energy range of the drift region (102), wherein the contact holes (110) are formed continuously in a reticulated form along an interior of the trench (105).
    [0002]
    Semiconductor device, according to claim 1, CHARACTERIZED by the fact that the anode region (106) composes a unipolar diode at a junction surface with the drift region (102).
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    同族专利:
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    法律状态:
    2018-12-18| B06F| Objections, documents and/or translations needed after an examination request according art. 34 industrial property law|
    2019-11-26| B06U| Preliminary requirement: requests with searches performed by other patent offices: suspension of the patent application procedure|
    2020-11-10| B09A| Decision: intention to grant|
    2021-01-12| B16A| Patent or certificate of addition of invention granted|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 24/02/2012, OBSERVADAS AS CONDICOES LEGAIS. |
    优先权:
    申请号 | 申请日 | 专利标题
    JP2011-092962|2011-04-19|
    JP2011092962|2011-04-19|
    PCT/JP2012/054622|WO2012144271A1|2011-04-19|2012-02-24|Semiconductor device and method for producing same|
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