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    • 专利摘要:
    BUILT-IN DRAM WITH LOW ENERGY SELF-CORRECTION CAPACITY. Apparatus and methods for combined low energy consumption self-restoration and self-correction of a Dynamic Random Access Memory (DRAM) matrix. During a self-restore cycle, a first part of a first row of the DRAM array is accessed and analyzed for one or more errors, where a bit width of the first part is less than a bit width of the first row . If one or more errors are detected, the one or more errors are corrected to form a corrected first part. The corrected first part is selectively recorded back to the first row. If no errors are detected in the first part, a recording of the first part back to the first row is prevented.
    公开号:BR112013014412B1
    申请号:R112013014412-2
    申请日:2011-12-12
    公开日:2021-03-16
    发明作者:Jungwon Suh
    申请人:Qualcomm Incorporated；
    IPC主号:
    专利说明:

    Field of the Invention
    [0001] The described modalities refer to Dynamic Random Access Memory (DRAM). More specifically, exemplary modalities refer to embedded DRAMs with low energy consumption self-correcting capability. Description of the Prior Art
    [0002] DRAM systems provide low-cost data storage solutions due to the simplicity of their construction. Essentially, DRAM cells are composed of a switch / transistor and a capacitor to store information in terms of charge. Therefore, the construction of DRAM cells is simple, requires much less area compared to Static Random Access Memory (SRAM) cells; and receptive to high-density integration in memory arrays and embedded systems. However, due to the fact that the capacitors leak, the charge stored in the capacitors needs to be periodically renewed to properly maintain the stored information. The need for periodic and frequent renewal of DRAM cells consumes considerable energy, and makes DRAM systems unattractive for low-energy applications, despite their low cost.
    [0003] Renewal operations on DRAM cells consume a lot of energy because whenever a single DRAM cell in a DRAM matrix needs to be renewed, the entire row in which the cell resides is read and then written back. DRAM cells are automatically renewed when they are read / written back during memory read / write operations. However, DRAM cells must be renewed at a certain minimum frequency to ensure that errors are not introduced. Therefore, when memory read / write operations have not occurred within a certain period of time since the DRAM cells were last renewed, or when the system is in a standby mode, a DRAM controller can be used to monitor the renewal fees and perform renewal cycles at the required frequency. The realization of a renovation using a DRAM controller, outside of the regular read / write operations of memory, is also known as “auto restoration”.
    [0004] Normally, in auto-restore mode, each row of a DRAM array is taken through a read and write process back in sequence, during the course of a renewal cycle. Each of these read-write processes back stimulates lines of words, a pair of complementary bit lines, detection amplifiers, etc. The minimum frequency at which renewal cycles may need to be programmed to minimize errors is typically in the order of several thousand renewal cycles per second.
    [0005] Errors that can occur in DRAM arrays can be broadly classified as software errors and hardware errors. Software errors are caused due to radioactive contaminants introduced during packaging of the embedded DRAM systems, cosmic rays, thermal neutrons, etc. Software errors are also susceptible to the operating temperature of DRAM systems, so that errors are more likely at higher temperatures. Software errors, if detected in a DRAM cell, can be rectified by just rewriting the correct data back into the DRAM cell. However, hardware errors are physical defects, and can be attributable to, say, manufacturing defects. Hardware errors are usually difficult to rectify.
    [0006] Commonly used techniques for error detection and error correction include the use of error correction code (ECC) bits. ECC bits are introduced in the DRAM matrix as additional information, such as parity data, related to the data stored in the DRAM matrix. One or more ECC bits are normally computed for each data segment, such as a data byte, in the DRAM array. The ECC bits can be stored together with the data in the DRAM matrix. When a data row, comprising several data segments, is read from the DRAM matrix, the corresponding ECC bits are also read. Error detection can be performed on each of the data segments within a row, using the corresponding ECC bits. If errors are detected in one or more data segments, known techniques can be used to correct the errors, and the entire row comprising correct data segments is written back to the DRAM matrix.
    [0007] Error detection and correction as described above can be performed in the direction of a processor or CPU coupled to an embedded DRAM system. As can be seen, error detection and correction also involves read and write operations back to be performed on the DRAM matrix. Therefore, error detection and correction can be combined with regular read / write operations to memory as initiated by a CPU or other bus master. However, the integration of this error detection and correction aspect with regular read / write operations results in an extension of the latency required for these read / write operations, which may be unacceptable in high performance systems.
    [0008] Error detection and correction can also be controlled automatically within a DRAM system, which is sometimes referred to as “auto-correction”. Normally, self-correction and self-restoration are performed as separate operations. Therefore, each of these self-healing and self-healing operations ends up consuming energy associated with reading and writing back to the DRAM matrix. Some techniques try to adapt the frequency of self-correction based on the probability of errors to known frequencies of self-restoration. However, even with such solutions, the energy consumption associated with each self-correcting and self-restoring operation is not reduced. As is well known, the associated high energy consumption is a serious disadvantage, especially for embedded systems and battery-powered devices.
    [0009] There is, therefore, a need in the technique to minimize the energy consumption of the DRAM arrays incurred during the various memory read / write operations, renewal operations and error detection and correction operations. Summary of the Invention
    [0010] Exemplary modalities are addressed to systems and method for low energy consumption combined with self-restoration and self-correction of a Dynamic Random Access Memory (DRAM) matrix.
    [0011] For example, an exemplary modality refers to a method of accessing a Dynamic Random Access Memory (DRAM) matrix comprising accessing a first part of a row of the DRAM matrix, and analyzing the first part in relation to one or more errors, where the bit width of the first part is less than a bit width of the first row. If one or more errors are detected, correct one or more errors to form a corrected first part, and selectively record the corrected first part back to the first row. If no errors are detected, avoid recording back from the first part to the first row.
    [0012] Another exemplary modality refers to a Dynamic Random Access Memory (DRAM) array comprising a first row, and logic for detecting one or more errors in a first part of the first row, in which a bit width of the first part is less than a bit width of the first row. If errors are detected in the first part, logic to correct the errors, to form a corrected first part, and logic to selectively record the corrected first part back to the first row. If no errors are detected, logic to avoid writing back from the first part to the first row.
    [0013] Yet another exemplary modality refers to a Dynamic Random Access Memory (DRAM) matrix comprising: mechanisms for accessing a first part of one of a first row of the DRAM matrix, and mechanisms for analyzing the first part for one or more errors, where a bit width of the first part is less than a bit width of the first line. If one or more errors are detected, mechanisms to correct the one or more errors to form a corrected first part and mechanisms to selectively record the corrected first part back to the first row. If no errors are detected, mechanisms to avoid recording back from the first part to the first row.
    [0014] Similarly, another exemplary modality refers to the non-transient, computer-readable storage medium comprising code, which, when executed by a processor, causes the processor to perform operations to access a Dynamic Random Access Memory (DRAM) array. ), the computer readable non-transient storage medium comprising code for accessing a first part of a first row of the DRAM array, and code for analyzing the first part for one or more errors, where a bit width of the first part is less than a bit width of the first row. If one or more errors are detected, code to correct the one or more errors to form a corrected first part and code to selectively write the corrected first part back to the first row. If no error is detected, code to avoid writing back from the first part back to the first row.
    [0015] Yet another exemplary modality refers to a method of accessing a Dynamic Random Access Memory (DRAM) matrix comprising the step to access a first part of a first row of the DRAM matrix and step to analyze the first part for one or more errors, where a bit width of the first part is less than a bit width of the first row. If one or more errors are detected, the step to correct the one or more errors to form a corrected first part and step to selectively record the corrected first part back to the first row. If no errors are detected, step to avoid recording the first part back to the first row. Brief Description of the Figures
    [0016] The attached drawings are presented to assist in the description of the various modalities and are provided only for illustration of the modalities and not for their limitation.
    [0017] Figure 1 - is a schematic illustration of a conventional DRAM cell.
    [0018] Figure 2 - illustrates a DRAM system capable of implementing low energy consumption self-restoration and self-correction, according to the revealed modalities.
    [0019] Figure 3 - is a timing diagram illustrating the timing relationship between the various processes involved in self-restoration / self-correction operations in exemplary modalities.
    [0020] Figures 4A-C - illustrate systems and methods for monitoring errors in the DRAM matrices in relation to different operating temperatures and determining a frequency to perform auto-restoration / self-correction operations in exemplary modalities, for specific operating temperatures.
    [0021] Figure 5 - is a flowchart illustration of the sequence of operations performed in an exemplary method of performing self-restoration / self-correction operations in an exemplary DRAM matrix.
    [0022] Figure 6 - is a block diagram showing an exemplary wireless communication system in which modalities of the invention can be used advantageously. Detailed Description of the Invention
    [0023] Aspects of the invention are revealed in the following description and related drawings addressed to specific modalities. Alternative modalities can be devised without departing from the scope of the invention. In addition, well-known elements of the various modalities will not be described in detail or will be omitted so as not to obscure the relevant details of the various modalities discussed here.
    [0024] The word “exemplary” is used here meaning “serving as an example, instance or illustration”. Any modality described here as "exemplary" should not necessarily be considered as preferred or advantageous in relation to the other modalities. Similarly, the term "modalities" or "invention modalities" does not require that all modalities include the discussed feature, advantage or mode of operation.
    [0025] The terminology used here is intended to describe only specific modalities and is not intended to limit the various modalities. As used here, the singular forms "one", "one" and "o" are intended to also include the plural forms, unless the context clearly indicates otherwise. It will also be understood that the terms "comprises", "comprising", "includes" and / or "including", when used here, specify the presence of declared characteristics, integers, steps, operations, elements, and / or components, but do not prevent the presence or addition of one or more other characteristics, completeness, stages, operations, elements, components and / or groups thereof.
    [0026] Additionally, many modalities are described in terms of sequences of actions to be performed, for example, by the elements of a computing device. It will be recognized that several actions described here can be performed by specific circuits (for example, application-specific integrated circuits (ASICs)), by program instructions being executed by one or more processors, or by a combination of both. In addition, this sequence of actions described here can be considered to be fully incorporated into any form of computer-readable storage medium having stored in it a corresponding set of computer instructions that from execution would cause an associated processor to perform functionality here described. Thus, the various aspects of the invention can be incorporated into a number of different forms, all of which were considered to be within the scope of the claimed study material. In addition, for each of the modalities described here, the corresponding form of any such modality can be described here, for example, as "logic configured to" perform the described action.
    [0027] In general, exemplary modalities are directed to a DRAM system with self-healing and self-healing capabilities with low energy consumption. Unlike conventional DRAM systems, self-healing and self-healing operations can be integrated into a combined operation requiring reduced read and write access to a DRAM array in the DRAM system. A combined auto-restore and auto-correction can be performed separately from regularly scheduled read and write operations directed by a CPU or other bus master, thereby ensuring that the latencies of these regularly scheduled read and write operations are not affected.
    [0028] In addition, partial back recording operations can be performed selectively during autocorrection, in such a way that back recording of the data is prevented if no error is detected in a particular row of the DRAM matrix. In addition, the write back operation can be segmented in such a way that only the data segments requiring correction need to be written back to the DRAM matrix, thereby saving energy on unnecessary back recording of the data segments that do not require correction. Consequently, as will be seen in further detail below, fine-tuning logic can be used to analyze through columns of data segments in the DRAM matrix in addition to the row decoders to penetrate each row of the DRAM matrix during self-restoration and self-correction operations. .
    [0029] Exemplary modalities can also monitor the temperature at which the DRAM system is operated and thereby determine an appropriate frequency to perform self-restoration and self-correction operations based on the operating temperature.
    [0030] It will be understood that although modalities are described with reference to the embedded DRAM arrays, systems and techniques disclosed are not limited to the embedded DRAM systems, but can be easily extended to independent DRAM systems, as well as other implementations of DRAM devices.
    [0031] The exemplary DRAM system is now described with reference to Figures 1-5. Figure 1 illustrates a conventional DRAM cell 100, comprising transistor 106 and capacitor 108. Transistor 106 is switched on when word line 102 is activated, and leads to information in bit line / column line 104 for capacitor 108. Subsequently , the information is stored in capacitor 108.
    [0032] With reference to Figure 2, an embedded DRAM system 200 is shown. The DRAM system 200 comprises the DRAM matrix 202 formed of DRAM cells such as the DRAM cell 100. In an illustrative example, the DRAM 202 matrix will be described as comprising 64 bits or 8 bytes of data, byte 0-byte 7, with an ECC bit added for each data byte, in each row. The DRAM matrix 202 comprises 1K (1024) of such rows. However, the disclosed modalities should not be considered in any way limited to specific data sizes or ECC bits. For example, the DRAM matrix 202 may be part of a larger DRAM matrix, such as a 1MB matrix comprising of 16 matrices such as a DRAM matrix 202, such that a row of the 1MB DRAM matrix has word lines of length 1KB (64 bits x 16) and 1K (1024) data from such word lines. The size of the 1MB array is appropriately expanded to include 8 ECC bits for each 64 bits or 8 bytes of data.
    [0033] As shown in Figure 2, the eight ECC bits can be stored as an ECC byte next to the eight data bytes, byte 0-byte 7 within the DRAM matrix 202. The eight data bytes can be received from a source external memory, such as a CPU or other master bus, and be temporarily stored in input register D_in 220. The ECC byte can be computed by the ECC 214 encoder. The 72-bit field comprising the ECC byte together with 8 bytes of data, byte 0-byte 7, can then be recorded in the DRAM 202 matrix using the IO 206 recording trigger / detection amplifier.
    [0034] The row decoder 204 can be configured to activate a specific word line within the DRAM matrix 202, by decoding the 10-bit field, XRA [9: 0]. 1024 or 1K word lines can be encoded by the XRA [9: 0] field. To save energy and prevent unnecessary switching, the activation of the word lines can be controlled by the word line control logic, WL control 208. The renewal counter 210 comprises a row counter 240. Row counter 240 can be configured to penetrate the values 0 to 1023, encoded in XRA [9: 0] to activate each line of words in the DRAM 202 matrix in sequence, through a renewal cycle. Command register 224 can receive instructions from a CPU or other master bus and transfer them to command decoder 218. Command decoder 218 can subsequently direct renewal counter 210 to perform an auto-restore mode using "sref" command in which the renewal counter 210 essentially operates to cause row counter 240 to penetrate each word line of the 1024 word lines per self-reset cycle. Alternatively, command decoder 218 can direct renewal counter 210 to activate specific word lines based on instructions received at command register 224, and row address as derived from address register 226.
    [0035] With combined reference to Figures 1-2, the activation of the word line 230 effectively activates the transistor 106 of each DRAM cell 100 coupled to the word line 230. The operation leading to the activation of a word line is common for two operations, reading and writing. Normally, a renewal operation on word line 230 would involve reading from capacitor 108 of each DRAM cell 100 coupled to word line 230, via activated transistor 106, column line 104 and recording trigger / detection amplifier I / O 206; storing the data in a temporary storage register; and recording the data back from the buffer recorder, through column 104 and activated transistor 106 to capacitor 108. The word line 230 is kept elevated throughout this renewal operation. As described in additional detail below, exemplary modalities depart from this common renewal operation, in which although the word line 230 is activated, a self-correction process is also integrated into the renewal operation, before the data is written back to the matrix DRAM 202 at the end of the renewal cycle. Exemplary modalities also depart from the common renewal operation, in which data is only written back selectively to the DRAM matrix 202 in segments smaller than the entire word line 230. In addition, only those data segments in which errors can be detected , can be configured to be written back to save energy.
    [0036] With reference now to Figure 2, the renewal counter 210 also comprises column counter 250 to penetrate through columns of the DRAM matrix 202. Column counter 250 can be configured to penetrate through nine byte size columns including the ECC byte and eight data bytes, byte 0-byte 7, using the encoded XCA bits [3: 0]. The IO 206 recording trigger / detection amplifier can be configured to make it possible to read one byte at a time from the word line 230, based on a column address for a specific byte, as indicated by XCA [3: 0]. The ECC byte can be read first, and stored separately for use in conjunction with the data bytes, byte 0-byte 7. Alternatively, all nine bytes in the word line 230 can be read at least through appropriate configuration of the recording trigger / detection amplifier IO 206.
    [0037] When the ECC byte and data bytes, byte 0-byte 7, are read, they are sent to the ECC 216 decoder. The ECC 216 decoder is configured to detect errors, if any, in each data byte, byte 0-byte 7, using a corresponding ECC bit from the ECC byte. Known techniques can be used to perform error detection using ECC bits. If an error is detected in any of the eight data bytes, byte 0-byte 7, the ECC 216 decoder can signal the byte that contains an error, using the signal error_flag [8: 0]. Each bit in the error_flag [8: 0] can index to a specific data byte, byte 0-byte 7, to indicate that an error was detected in that specific data byte.
    [0038] The logic block autocorrection control 212 generally monitors the error correction process. Autocorrection control 212 can be controlled by command decoder 218 based on instructions received at command register 214, or autocorrection control 212 can be configured to operate more autonomously to perform autocorrection during an auto restore operation. The same command, "sref" that is sent to the renewal counter 210 can be used to guide the auto-correction control 212 to perform auto-correction during an auto-restore mode. In one embodiment, although word line 230 is still kept high during an auto-restore operation, auto-correction control 212 can receive the signal, error_flag [8: 0] from the ECC 216 decoder. Based on which bytes of byte 0-byte 7, if any, has been flagged as containing an error, auto-correction control 212 can initiate a selective correction and write back the process in the specific bytes that may have an error.
    [0039] For example, if byte 0 was signaled as containing an error, with the guarantee of an appropriate bit, say error_flag [0], in the error_flag signal [8: 0], then the 212 auto-correction control generates the byte_ctrl [8 : 0], only with the byte_ctrl [0] asserted, to indicate that only byte 0 needs to be written back in the word line 230, after byte 0 has been corrected. Known techniques for correcting errors detected using the ECC bits can be employed, and will not be described in detail here. In one embodiment, the ECC 216 decoder can be configured to correct the error in byte 0, upon receipt of a write_back signal from the auto-correction control 212, indicating that at least one byte needs to be written back. If, on the other hand, the ECC 216 decoder has previously detected any error in any of the eight data bytes, byte 0-byte 7, all error_flag bits [8: 0] would be inversely asserted to indicate no error in any byte of data, and autocorrection control 212 would assert inversely (or maintain in an inverse asserted state), the write_back signal, to indicate that no write back operations need to be performed. The byte_ctrl signal [8: 0] would also disable recording back to all bytes in this case. In other words, the write back operation is performed only on the data bytes that may contain an error, and if no error is detected in any of the data bytes, then none of the data bytes is written back in the process of auto correct.
    [0040] In the exemplary modalities, the output of the ECC 216 decoder comprising correct data (corrected, if an error is detected; and unchanged if no error is detected), can be stored in a temporary recorder 228, and then recorded back on the line of words 230 through the recording trigger / detection amplifier IO 206, under the control of byte_ctrl [8: 0]. The IO 206 recording trigger / detection amplifier is appropriately configured to allow for back data recording in byte-sized segments. As can be seen, only one byte of data that can comprise an error will be corrected and written back during the combined auto-restoration and auto-correction operation. When back recording, if any, is completed, word line 230 is inversely asserted. Renewal counter 210 directs row counter 240 to increment the next row of the DRAM matrix 202, and the process is repeated until all 1024 rows are carried out through a combined auto-restore and auto-correction operation. It will be understood that requests for external service reading can also be integrated into the above process, by extracting the data from the ECC 216 decoder, and reading the data from the DRAM system using the register, D_out 222. The timing for the various processes may have source from a system clock, such as clk 201.
    [0041] Referring now to Figure 3, a schematic timing diagram is shown detailing the timing relationship between the various processes described above with respect to self-restoration and self-correction. In the timing diagram 300, selected cycles of the system clock, clk 201 are shown. A command 304 is received from command decoder 218. At time 330, command sref 306 is asserted, essentially activating a combined operation of auto-restoration and auto-correction. In an illustrated example, the word line WL 310 is selected via XRA [9: 0] at time 340. At that time, byte [k] of the eight data bytes in word line 310 is highlighted by the XCA signal [ 3: 0]. Right afterwards, bit lines BL & / BL 308 are activated at time 344 to read a specific bit of byte [k]. The ECC 216 decoder receives byte [k] and detects that byte [k] comprises an error in the bit selected by BL & / BL 308, which is signaled for self-correction control 212, by asserting the bit, error_flag [k] at time 380 Autocorrection control 212 asserts the write_back signal (not shown) and error decoder 216 then corrects the error and stores a corrected value of byte [k] in register 228. At time 390, autocorrection control 212 asserts byte_ctrl [k] to allow the corrected value of byte [k] in register 228 to be written back to word line 310 through the IO 206 recording trigger / detection amplifier. At time 350, the byte error [k] is corrected, as illustrated by the change in values of bit lines BL & / BL 308. Thus, the operation of an autocorrection is illustrated when an error is detected, during an auto restoration.
    [0042] Continuing with reference to Figure 3, the operation of the revealed modalities is also illustrated when no error is detected. At time 360, a renewal cycle continues to be in effect, and the word line WL 314 is selected through XRA [9: 0]. The bit lines BL & / BL312 of byte [m] (selected by XCA [3: 0]) are activated at time 364 to read the bits of the byte [m]. However, in that case, the error decoder 216 does not detect any errors in bytes [m]. Therefore, no errors are signaled via the corresponding terror_flag [m] signal and therefore the corresponding write_back and byte_ctrl [m] are not asserted and, subsequently, no back recording is performed at time 370. Thus, useless back recording activity is avoided , because it is determined that no error is detected. If, at a later time, during a different cycle, an error is detected in byte [m], then byte [m] is corrected and also renewed at the same time.
    [0043] Consequently, continuing with reference to Figure 3, exemplary modalities include a method of accessing a DRAM array comprising: accessing a first part (for example, byte [k]) of a first row (for example, word line WL 310) the DRAM matrix, where a bit width of the first part is less than a bit width of the first row; analyzing the first part for one or more errors; correcting the one or more errors to form a corrected first part (for example, corrected byte value [k] stored in register 228) if one or more errors are detected; and selectively recording the corrected first part back to the first row.
    [0044] It will be seen that, exemplary modalities provide significant energy savings by preventing unnecessary costly back recording operations on the DRAM 202 matrix. Additionally, the modalities combine the two auto-restore and auto-correction operations on the DRAM matrix into an efficiently integrated operation in which read and write back, if any, are shared. Energy savings are also extracted by segmenting each line of words and performing a selective recording back. Revealed techniques will be considered to incur very little hardware overhead and do not affect the latencies of regular read / write operations programmed into DRAM arrays by a CPU or other bus master, because the combined auto-restore and auto-correction operations are performed regardless of such regular read / write operations.
    [0045] An additional modality is now described to adapt the frequency of the self-restoration and self-correction operations to the operating temperature of the built-in DRAM system 200. It is advantageously recognized that the operating temperature can play a significant role in the frequency of errors occurring in the DRAM matrix 202. In general, the number of errors is likely to increase with an increase in operating temperature. The data extracted from error_flag [8: 0] through a large number of self-restoration / self-correction cycles, by varying the operating temperature, can reveal a statistical relationship between the number of errors and the temperature. When the number of errors that are likely to occur at a given temperature has been determined, an optimal frequency for performing auto-restore / self-correction operations to minimize errors can be determined at that temperature. It is recognized that different systems have different forms of error tendencies at a given operating temperature.
    [0046] With reference to Figures 4A-C, intelligent systems are illustrated to optimally adapt the frequency of the self-restoration / self-correction cycles to the operating temperature. For example, Figure 4C illustrates a table, classifying DRAM systems based on their susceptibility to errors. The signal, error_info [1: 0] is determined from error_flag [8: 0] and broadly classifies DRAM systems into four categories based on the number of errors at a given operating temperature. In the example in Figure 4C, 0-4 errors are classified as a "normal" SREF mode. The SREF mode refers to the frequency at which self-restoration / self-correction cycles need to be performed to minimize errors. Similarly, the table in Figure 4C classifies the SREF modes as "conservative 1", "conservative 2", and "extreme" based on the number of errors as indicated by error_info [1: 0].
    [0047] Each SREF mode refers to a specific frequency at a given temperature, which can be determined appropriately from the graph in Figure 4B. With reference to Figure 4B, a graph is shown illustrating the relationship between an internal self-restoration period and temperature for each SREF mode. A corresponding self-restoration / self-correction frequency can be determined as the inverse of the internal self-restoration period.
    [0048] With reference now to Figure 4A, a system is shown to adjust the frequency of the self-restoration / self-correction cycles in the DRAM 200 system from Figure 2, based on the information obtained from Figures 4B-C. The error counter 406 emits error_info [1: 0] by accumulating and studying error_flag [8: 0] through a large predetermined number of self-healing / self-correcting cycles. The temperature sensor 408 determines the operating temperature of the DRAM 200 system. The internal oscillator 402 provides a baseline frequency, which can be adjusted by the frequency divider 404. The frequency divider 404 receives error_info [1: 0] , and the operating temperature from error counter 406 and temperature sensor 408, respectively, and based on the table in Figure 4C and the graph in Figure 4B, determines the frequency to perform auto-restore / self-correction cycles in the DRAM 200 system This information is then transferred to the 201 clock in Figure 2, to properly control the DRAM 200 system's auto-restore / auto-correction cycles.
    [0049] It will be considered that modalities include several methods to carry out the processes, functions and / or algorithms disclosed here. For example, as illustrated in Figure 5, a modality can include a method of starting an auto-restore / auto-correction cycle in a DRAM matrix (block 502). Through the use of a row counter, for example, a row address for a given first row, and the first row is activated (block 504). Then, using a column counter, for example, a column address is determined, and a first word is read from the first row activated using a column address, where a word can comprise one or more bytes (block 506). ECC decoding and error detection are performed on the first word, in Block 508. In Block 510, if an error is detected, the method enters Block 512. In Block 512, the error is corrected and a partial lap recording of the first word is performed to its original location, and the method continues to Block 514. If no error is detected in Block 510, no back recording is performed, and the method enters Block 514. In Block 514, the column address is verified to see if he's aiming for the last word in the first row. If in Block 514, it is determined that the last word in the first row is not reached, then the column address is increased to point to the next word in the first row, in Block 518, and the method is repeated from Block 506. If in Block 514, it is determined that the last word of the first row is reached, then the row address is incremented in Block 516. In Block 520, it is determined whether the last row of the DRAM matrix is reached, and if not, the method repeats from Block 504. If in Block 520, it is determined that the address of the last row is reached, then the auto-restore / self-correction cycle started in Block 502 ends at Block 522.
    [0050] Those skilled in the art will consider that the information and the signal may be represented by the use of any of the varieties of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description above may be represented by voltages, currents, electromagnetic waves, optical fields or particles, or any combination of these.
    [0051] Additionally, those skilled in the art will consider that several illustrative logic blocks, modules, circuits, and steps of algorithms described in connection with the present invention can be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, several illustrative components, blocks, modules, circuits and steps, have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and project restrictions imposed on the system as a whole. Those skilled in the art can implement the functionality described in different ways for each specific application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
    [0052] The methods, sequences and / or algorithms described in connection with the modalities described here can be incorporated directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module can reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor in such a way that the processor can read the information from the storage medium and write information to it. Alternatively, the storage medium can be integral to the processor.
    [0053] Consequently, a modality may include a computer-readable medium incorporating a method to access a DRAM matrix and perform low energy consumption autocorrection by integrating an autocorrection operation within an auto restoration cycle. Consequently, the various modalities are not limited to the illustrated examples and any mechanism for carrying out the functionality described here is included in the various modalities.
    [0054] Figure 6 illustrates an exemplary wireless communication system 600 in which an embodiment of the invention can be advantageously employed. For the purpose of illustration, Figure 6 shows three remote units 620, 630, and 650 and two base stations 640. In Figure 6, remote unit 620 is shown as a mobile phone, remote unit 630 is shown as a computer handheld and remote unit 650 are shown as a fixed location remote unit in a wireless local loop system. For example, remote units can be mobile phones, handheld personal communication systems (PCS) units, portable data units such as personal data assistants, GPS enabled devices, navigation devices, set top boxes, playback devices music players, video playback devices, entertainment units, fixed location data units such as meter reading equipment, or any other device that stores or retrieves computer data or instructions, or any combination thereof. Although Figure 6 shows the remote units in accordance with the teachings of the invention, the invention is not limited to those exemplary illustrated units. Modalities of the invention can be employed suitably in any device that includes active integrated circuitry including memory and chip circuitry for testing and characterization.
    [0055] The devices and methods previously revealed are typically designed and configured in GDSH and GERBER computer files, stored on computer-readable media. These files are in turn provided to the manufacturers who manufacture the devices based on these files. The resulting products are semiconductor sheets that are then cut into semiconductor inserts and packaged on a semiconductor chip. The chips are then used in the devices described above.
    [0056] Although the preceding invention shows illustrative modalities, it should be noted that various changes and modifications could be made here without departing from the scope of the invention as defined by the appended claims. The functions, steps and / or actions of the method claims according to the various modalities described here do not need to be performed in any specific order. In addition, although elements of the various modalities disclosed may be described or claimed in the singular, the plural is considered unless limitation to the singular is explicitly stated.
    权利要求:
    Claims (15)
    [0001]
    1. Method for performing a combined auto-restoration and self-correction operation in a Dynamic Random Access Memory (DRAM) array, comprising: activating (504) a first row of the DRAM array, the first row comprising a first part, in which a bit width of the first part is less than a bit width of the first row; read (506), by a writing driver / detection amplifier (206), from the first row and send the first row to a corrector code decoder error, ECC (216); record the first row, by the writing driver / detection amplifier (206); analyze (508), by the ECC decoder (216), the first row for one or more errors; avoid recording of the first part, if no error is detected by the ECC decoder (216); correct (512) the one or more errors to form a corrected first part, if one or more errors are detected in the first part by the ECC decoder (216) the method, man characterized by the fact that it additionally comprises: recording, by the writing driver / detection amplifier (206), only the first corrected part in the first row.
    [0002]
    2. Method according to claim 1, characterized by the fact that it further comprises storing error correction code, ECC bits, associated with the first part in the first row, and detecting an error in the first part, using the ECC.
    [0003]
    3. Method according to claim 2, characterized by the fact that the first part comprises 8 bits of data, and in which 1 bit of ECC is associated with the first part, such that the first row comprises 8 bits of ECC and 64 bits of data.
    [0004]
    4. Method, according to claim 1, characterized by the fact that it additionally comprises: associating column addresses with parts of the first row; updating (518) the column address to point to a second part of the first row; second part: analyze (508) the second part for one or more errors, if errors are detected, correct one or more errors to form a second corrected part and record the second corrected part in the first row; if no error is detected, avoid (512) recording the second part.
    [0005]
    5. Method, according to claim 4, characterized by the fact that it repeats for all parts of the first row.
    [0006]
    6. Method, according to claim 5, characterized by the fact that it repeats for all rows of the DRAM matrix.
    [0007]
    7. Method according to claim 1, characterized by the fact that it additionally comprises tracking a number of errors detected in the DRAM matrix during a screening period, and determining an optimal frequency to access the DRAM matrix based on the number of errors detected during the tracking period.
    [0008]
    8. Method according to claim 7, characterized by the fact that it additionally comprises tracking the number of errors for a specific operating temperature, and determining the optimal frequency for the specific operating temperature.
    [0009]
    9. Dynamic random access memory array, DRAM, adapted to perform a combined auto-restoration and self-correction operation, comprising: mechanisms to activate (504) a first row of the DRAM matrix, the first row comprising a first part, in which a bit width of the first part is less than a bit width of the first row; mechanisms for effecting reading (506), by a writing driver / detection amplifier (206), of the first row and sending the first row to a decoder error correction code, ECC (216); mechanisms for recording the first row, by the writing driver / detection amplifier (206); mechanisms for analyzing (508) the first part for one or more errors; mechanisms for avoiding a recording of the first part, if no error is detected by the ECC decoder (216) mechanisms to correct (512) the one or more errors to form a corrected first part, if one or more errors are detected by the decod ECC ifier (216), the DRAM matrix, characterized by the fact that it additionally comprises: mechanisms to record, by the writing driver / detection amplifier (206), only the first corrected part in the first row.
    [0010]
    10. DRAM matrix, according to claim 9, characterized by the fact that it additionally comprises mechanisms to store error detection and error correction associated with the first part in the first row, and stored in the DRAM matrix.
    [0011]
    11. DRAM matrix, according to claim 9, characterized by the fact that it additionally comprises: mechanisms for associating column addresses with parts of the first row; mechanisms for updating the column address to point to a second part of the first row; mechanisms to access the second part, mechanisms to analyze the second part for one or more errors and if errors are detected, mechanisms to correct one or more errors to form a corrected second part; mechanisms to selectively record the corrected second part back to the first row.
    [0012]
    12. DRAM matrix, according to claim 9, characterized by the fact that it additionally comprises mechanisms to track a number of errors detected in the DRAM matrix during a screening period, and mechanisms to determine an optimal frequency to access the DRAM matrix based on the number of errors detected during the tracking period.
    [0013]
    13. DRAM matrix, according to claim 9, characterized by the fact that it is integrated in at least one semiconductor wafer.
    [0014]
    14. DRAM matrix, according to claim 9, characterized by the fact that it is integrated into a device, selected from the group consisting of a set top box, music player, video player, entertainment unit, device navigation device, communication device, personal digital assistant, PDA, fixed location data unit, and a computer.
    [0015]
    15. Non-transient computer-readable memory, characterized by the fact that it comprises instructions that, when executed by a processor, cause the processor to perform the operations to perform the method as defined in claim 1.
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    法律状态:
    2020-08-18| B06U| Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]|
    2021-01-05| B09A| Decision: intention to grant [chapter 9.1 patent gazette]|
    2021-03-16| B16A| Patent or certificate of addition of invention granted|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 12/12/2011, OBSERVADAS AS CONDICOES LEGAIS. |
    优先权:
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    US12/964,761|US8621324B2|2010-12-10|2010-12-10|Embedded DRAM having low power self-correction capability|
    US12/964,761|2010-12-10|
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