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    • 专利摘要:
    TRANSACTIONS OF AUTOMATIC HARDWARE PERFORMANCE STATUS IN SYSTEM IN SUSPENSION AND PROCESSOR ACTIVATION EVENTS The present invention relates to a modality, a power management unit (PMU) that can carry out the transition automatically (in hardware) of performance states of one or more performance domains on a system. The performance target states to which the performance domains must perform the translation can be programmed into the PMU by the software, and the software can signal the PMU that a processor in the system is about to enter the sleep state. The PMU can control the transition from performance domains to performance target states, and can cause the processor to go to sleep. In one embodiment, the PMU can be programmed with a second set of performance target states to which the performance domains must transition when the processor leaves the sleep state. The PMU can control the transition from the performance domains to the second target performance state and cause the processor to come out of sleep.
    公开号:BR112012025292B1
    申请号:R112012025292-5
    申请日:2011-04-06
    公开日:2020-11-03
    发明作者:Josh de Cesare；Jung Wook Cho；Toshi Takayanagi；Timothy J. Millet
    申请人:Apple Inc；
    IPC主号:
    专利说明:

    Background Field of the Invention
    [001] The present invention relates to the field of systems that include processors and peripheral devices, and to the management of energy consumption in such systems. Description of the Related Art
    [002] As the number of transistors included in a "chip" integrated circuit continues to increase, power management in integrated circuits continues to increase in importance. Power management can be critical to the integrated circuits that are included in mobile devices, such as personal digital assistants (PDAs), cell phones, smartphones, laptop computers, nettop computers, etc. These mobile devices generally rely on battery power, and reducing power consumption on integrated circuits can increase battery life. Additionally, reducing energy consumption can reduce the heat generated by the integrated circuit, which can reduce the cooling requirements on the device that includes the integrated circuit (whether it is using battery power or not).
    [003] Clock switching is often used to reduce the dynamic power consumption of an integrated circuit, disabling the clock to inactivate the circuit set and thus preventing switching in the inactivated circuit set. In addition, some integrated circuits have energy switching implemented to reduce static energy consumption (for example, consumption due to leakage currents). With the switching of energy, the energy to the terrestrial path of the inactive circuit is interrupted, reducing the leakage current to almost zero.
    [004] Clock switching and energy switching can be effective energy preservation mechanisms. However, in some cases, these mechanisms are not as effective as desired. For example, systems that include processors can cause processors to enter a sleep state to preserve power. While the processor is in a sleep state, other components in the system are still active and, in general, are operating at levels of performance that support active processors. When processors are in the sleep state, these other components need not be operating at such a high level of performance. Similarly, when processors are activated from sleep, the level of performance at which processors and other components need to operate to sustain the activities that are performed by the system may be different than the level of performance before the processor enters the state suspension.
    [005] Transitions between suspended / active processors and other components are changed under the control of the software. The software runs on processors, so changing the performance levels of processors and other components can affect the amount of time required to run the software. These effects have an impact on the efficiency of the transition, causing an impact on the preserved energy and the performance of the application. In addition, the runtime of the software can affect the frequency with which the processor transitions to the tested suspension, and the amount of reduced performance that can be tolerated in the rest of the system. summary
    [006] In one mode, a power management unit can be configured to carry out the transition automatically (in hardware) in the performance states of one or more performance domains in a system. The performance target states to which the performance domains must transition can be programmed into the power management unit by the software. In addition, the software can signal the power management unit that a processor in the system is about to enter the sleep state. Alternatively, the power management unit can monitor the processor to detect that the processor is entering sleep or has entered sleep. The power management unit can be configured to control the transition from performance domains to target performance states, and can also cause the processor to go to sleep in some modes. In one embodiment, the power management unit can be programmed with a second set of performance target states to which the performance domains must transition when the processor resumes from sleep. The power management unit can be configured to control the transition from the performance domains to a second target performance state and can also cause the processor to come out of sleep in some modes.
    [007] In one embodiment, the transition of performance domains in different target states can be faster when controlled by the power management unit than can be possible with software control. Accordingly, energy conservation can be more efficient than a purely software-driven implementation, and the performance of applications running on the system can also be positively affected. In addition, the ability to configure performance states can allow more rigorous control of the level of performance in the system and thus can allow for additional energy savings. In some cases, performance states may be further reduced than would be possible in software-driven implementation, as the time required for the software to run while the system is in the underperforming states is a reduced factor (or can even be eliminated ).
    [008] Each component of the system can be included in a performance domain, and each performance domain can include at least one component, but can include multiple components, in various modalities. The power management unit can be programmed with performance state identifiers for each performance domain, and for each hardware-managed transition (for example, in the sleep state, outside the sleep state, or both outside and in the state. suspension, in various modalities). The processor sleep state can also be a performance state, as can several other performance states that the processor can be programmed in various modes. Brief Description of Drawings
    [009] The following detailed description refers to the accompanying drawings, which are now briefly described.
    [0010] figure 1 is a block diagram of a modality of a system;
    [0011] figure 2 is a block diagram of a modality of performance configuration records illustrated in figure 1;
    [0012] figure 3 is a flow chart that illustrates the operation of a modality of an energy management unit to automatically change energy states;
    [0013] figure 4 is a block diagram illustrating a modality of driver components;
    [0014] figure 5 is a flow chart that illustrates the operation of a modality of a driver component of the power management unit;
    [0015] figure 6 is a block diagram illustrating another modality of a system;
    [0016] figure 7 is a block diagram of a modality of a storage medium accessible by computer.
    [0017] Although the invention is susceptible to several modifications and alternative forms, the specific modalities of it are shown by way of example in the drawings and will be described here in detail. It should be understood, however, that the drawings and detailed description are not intended to limit the invention to the specific form presented, but rather, the invention must cover all modifications, equivalents and alternatives that fall within the spirit and scope of the present invention as defined by the appended claims. The headings used here are for organizing purposes only and are not intended to be used to limit the scope of the description. As used throughout this application, the word "can" is used in the permissive sense (that is, it means that it has the potential for), rather than the mandatory sense (that is, it means must). Similarly, the words "include", "including" and "includes" mean including, but not limited to.
    [0018] The various units, circuits or other components can be described as "configured to" perform a task or tasks. In such contexts, "configured for" is a broad mention of the structure, which generally means "that has the circuitry that" performs the task or tasks during operation. Thus, the unit / circuit / component can be configured to perform the task even when the unit / circuit / component is not currently connected. In general, the circuit that forms the structure that corresponds to "configured for" can include hardware circuits. Similarly, several units / circuits / components can be described as performing a task or tasks, for convenience in the description. Such descriptions should be interpreted as including the expression "configured for". The mention of a unit / circuit / component that is configured to perform one or more tasks is expressly intended not to invoke 35 USC § 112, interpretation of the sixth paragraph for that unit / circuit / component. Detailed Description of the Modalities
    [0019] Now, with reference to figure 1, a block diagram of a modality of a system is shown. In the embodiment of figure 1, the system includes an integrated circuit (IC) 10 that forms a system on a chip, and a power supply 12. Integrated circuit 10 includes a set of performance domains 14A-14F. Each performance domain 14A-14F includes at least one component of integrated circuit 10, and a given performance domain can include more than one component. For example, performance domain 14A in figure 1 includes two components, a processor 16A and another component 18; and the performance domain 14E can include two or more peripherals 24. In the illustrated embodiment, the performance domain 14B includes an optional second processor 16B; the performance domain 14C includes a graphics unit 20; the performance domain 14D includes an audio unit 22; performance domain 14E includes networked peripherals and / or other peripherals and / or peripheral interface units 24; and performance domain 14F includes a memory controller 26. Integrated circuit 10 also includes a power management unit (PMU) 28 (which includes one or more performance configuration records 30) and a clock / control unit voltage 32. The various components shown in figure 1 can be coupled in any way desired. For example, there may be one or more buses or other interfaces between the components. PMU 28 and clock / voltage control unit 32 can also be coupled to various components in addition to being coupled to interfaces. For example, the clock / voltage control unit 32 can supply the components with power signals (not shown in figure 1). The clock / voltage control unit 32 can be configured to communicate with power supply 12 to request one or more supply voltages from power supply 12. Power supply 12 can generate the requested voltage or voltages and can supply the integrated circuit with voltages.
    [0020] PMU 28 can be configured to control transitions between performance states for the various performance domains 14A-14F. In particular, PMU 28 can be configured to automatically transition one or more of the 14A-14F performance domains in response to one or more 16A-16B processors that enter a sleep state (or in response to the determination that the processor is about to enter the sleep state). PMU 28 can also be configured to automatically transition one or more of the 14A-14F performance domains in response to the processor coming out of sleep (or in response to the determination that the processor is about to come out of sleep) suspension). The exit from the sleep state can also be called "activation" of the processor. The sleep state and other states of the processors can be the performance states of the performance domains that include the processors. Alternatively, the sleep state and other processor states can be the performance characteristics in a performance state for the performance domains that include the processors.
    [0021] A performance domain can be one or more components that can be controlled by the PMU 28 as a unit for the purposes of performance configuration. That is, PMU 28 can be configured to establish a corresponding performance state for each performance domain, and can be configured to control the transitions between performance states in each performance domain. The components that make up a performance domain can transition from one performance state to another performance state together. On the other hand, components in different performance domains can be independent of each other, at least from the hardware point of view, and can have performance states determined independently. Some performance domains can be logically linked to a higher level (for example, in software). For example, the 18C-18D performance domains can be logically linked if a user is watching a video that includes sound (thus using the graphics unit 20 to display the video images and the audio unit 22 for transmit the sound (mapping)).
    [0022] The performance state can include any combination of performance characteristics for the components in a corresponding performance domain. A performance characteristic can be any setting that can be configured for a component that affects the performance of that component. For example, the frequency of operation of the clock signal provided to a component can affect its performance. A lower operating frequency can result in lower performance. A corresponding supply voltage can also be a performance characteristic. Some performance characteristics may be component specific. For example, cache sizes in multiple caches can be a performance characteristic. A data width or other data transfer rate parameter for an interface can be a performance characteristic. A component that includes a number of symmetric units that can operate in parallel (for example, execution units on a processor, pixel channels or other image processing channels on a graphics unit, etc.) can be configured as the number symmetric units that are active. Numerous instructions (processor), operations (graphic or audio), communications (network or other peripheral interface), or memory request (memory control unit) processed per unit of time can be a performance characteristic. A resolution or size of graphics in the color palette (for example, bits per pixel) can be a performance characteristic. Resolution and audio sample rates can be a performance characteristic. Memory bandwidth can be a performance feature. The processor's suspend / wake state can be a performance characteristic. If the components or parts of them are controlled by power and / or controlled by clock, the power and / or clock qualifications can be performance characteristics. Any parameter that can be changed and that can affect performance can be a performance characteristic in several modalities.
    [0023] Changing the performance state in a performance domain can affect the energy consumption of the performance domain. Reducing the operating frequency and supply voltage has a direct effect on energy consumption. Reducing the size of the cache can reduce power consumption, as a part of the cache cannot be accessed, and further reduction can be performed if the unused part is turned off. Additionally, the size of the cache can reduce the reached cache rates, which can increase the amount of memory for the consumer. Increased memory latency can reduce consumer activity by reducing energy consumption. The reduced data transfer rates / widths on the interfaces can reduce energy consumption through reduced switching. In addition, reducing the rate at which data is provided to a consumer can reduce consumer activity, which can reduce consumer energy consumption. Parallel reduced activity in symmetric units can reduce energy consumption through reduced activity, as can reduce instruction issuance rates or other operations. Reducing the graphics / audio resolution and the color palette can reduce the amount of data transferred per image or sound unit. Reduced memory bandwidth can reduce power consumption when accessing memory per unit of time, and can reduce consumer activity.
    [0024] In some embodiments, the performance state may include multiple instances of a performance characteristic. For example, if the processor is turned off in the sleep state and other components are in the same performance domain, the voltage for the processor can be adjusted separately from the voltage for the other components that remain active. Similarly, any other performance characteristics that apply more than one component in a performance domain and that can be independently controlled for such components can be represented by multiple instances in the performance state.
    [0025] In modalities in which a processor is in a performance domain with other components, the other components can remain active during the times when the processor is in the sleep state. For example, component 18 in performance domain 14A can remain active during times when processor 16A is in the sleep state. The performance characteristics of the component can be changed to reflect reduced operation while the processor is in the sleep state. For example, component 18 can be a level 2 (L2) cache coupled to processor 16A. In such an embodiment, the L2 cache may not be accessed by the suspended processor 16A, but may remain active to maintain cache coherence. The L2 cache can operate at a lower clock frequency (and voltage) in some modes, while still providing sufficient performance to ensure cache coherence.
    [0026] The PMU 28 may include the circuitry configured to cause the performance state transitions to occur in the performance domains. In one embodiment, the PMU 28 can detect that the processor 16A-16B is entering / leaving the sleep state, and can perform the corresponding transitions in the performance domains. In other modalities, the software can explicitly communicate the suspension / activation events to the PMU 28. In one modality, the PMU 28 can be programmed with the performance settings for each performance domain. For example, the performance states to be used in the performance domains 14A-14F when the processor is in the sleep state can be specified in the performance configuration records 30. The performance states to be used when the processor 16A- 16B exits the sleep state (is activated) can also be specified. When both events occur, PMU 28 can make the desired transitions.
    [0027] In the case of voltage and clock frequency changes, the PMU 28 can communicate the new settings to the clock / voltage control unit 32. The clock / voltage control unit 32 can implement the new settings, generating the clocks at the requested frequencies and requesting the desired supply voltages from the power supply 12. The clock / voltage control unit 32 can order modifications, if necessary, to carry out the transitions safely. For example, if the clock frequency and supply voltage are increased, it may be safer to increase the voltage first and then increase the clock frequency, as the increased clock frequency can lead to incorrect operation if the circuitry operating slower at the current (lower) supply voltage. In some embodiments, the amount of time that elapses in a change in supply voltage can be substantially greater than the time to change the clock frequency. If the clock frequency and supply voltage are decreased, the clock frequency can be reduced first (or the frequency and voltage can be reduced in parallel, since the lower clock frequency can be reached before the supply voltage in this case).
    [0028] The clock / voltage control unit 32 can include the circuitry to communicate with the power supply 12 to request the desired supply voltages, and can include the clock generation circuitry. For example, the clock / voltage control unit 32 may include one or more phase-locked loops (PLLs), clock splitters / multipliers, etc. to generate the clocks for the components.
    [0029] The various components included in integrated circuit 10 can implement any desired functionality .. In general, a component can refer to any set of circuits that is defined to perform a set of operations specified in the integrated circuit, and has a defined interface to communicate with other components on the integrated circuit. As shown in Figure 1, exemplifying components can include processors 16A-16B, component 18, graphics unit 20, audio unit 22, networking peripheral and other peripheral / peripheral interfaces 24 (which can multiple components), and the memory controller 26.
    [0030] Processors 16A-16B can implement any instruction set architecture, and can be configured to execute the instructions defined in that instruction set architecture. Any microarchitecture implementation can be used (for example, in order, out of order, speculative, non-speculative, escaped, superscale, channeled, superchanneled, etc.). Microcoding techniques can be used in some modalities, in combination with any of the above.
    [0031] As mentioned above, the performance state of 16A-16B processors can include a sleep state. In the sleep state, the processor is disabled (does not execute instructions). The clock for the processor can be stopped. In some embodiments, power can also be removed from the processor in the sleep state. Alternatively, there may be more than one state of suspension. One of the sleep states can include processor power, and another sleep state can include processor power retention. In addition, the processor may include at least one "activated state". There may be multiple states enabled. For example, different combinations of supply voltage / operating frequency can be supported, different combinations of enabled execution units can be supported, different instruction issuance rates can be supported, etc.
    [0032] A graphics unit 20 can include any circuitry involved in displaying images on a display device for, for example, viewing by the user. The images can be still images, or they can be part of a video. Graphics 20 can include rendering hardware, updating hardware (of the display device), video encoders and / or decoders, video compression and decompression units, etc. The audio unit 22 can include any circuit involved in the reproduction or recording of sounds in the system. The audio unit 22 may include, for example, audio encoders and / or decoders, digital signal processors, etc.
    [0033] Networking peripherals and other peripherals 24 may include variety of circuitry. For example, networking peripherals may include a media access controller (MAC) unit for the supported network, as well as the physical layer circuitry. The other peripherals can include any desired peripheral, and / or peripheral interface controllers configured to control peripheral interfaces outside the chip, such as peripheral component interconnection (PCI), PCI express (PCIe), firewire, Universal serial bus (USB) ), etc.
    [0034] The memory controller 26 can be configured to access memory devices, such as dynamic random access memory (DRAM), synchronized DRAM (SDRAM), dual data rate SDRAM (DDR, DDR2, DDR3, DDR4, etc.), low-power DDR (LPDDR2, etc.), SDRAM, RAMBUS DRAM (RDRAM), etc. In one embodiment, memory controller 26 can be configured to interface to one or more memory modules (for example, single-line memory modules (SIMMs), dual-line memory modules (DIMMs), etc.) that include one or more of the above memories. Accordingly, memory controller 26 can be configured to communicate with memory interfaces, to organize memory requests from other components in integrated circuit 10, and to communicate with other components to complete memory operations.
    [0035] Although the integrated circuit mode 10 shown in figure 1 includes numerous performance domains, more or less performance domains can be supported. For example, a single performance domain can be supported, or two performance domains can be supported (for example, a domain that includes 16A-16B processors and another domain that includes the remaining components 18, 20, 22, 24 and 26 ). One or more processors 16A-16B can be included in a performance domain with any subset of components 18, 20, 22, 24 and 26. Any combination of performance domains and components included in those domains can be implemented in several modalities.
    [0036] Other modalities of the integrated circuit 10 may include other combinations of components, which include any subset of the illustrated components with or without other components, super-assemblies with other components, etc. In addition, although the illustrated embodiment illustrates components 16A-16B, 18, 20, 22, 24 and 26 all included in integrated circuit 10, other embodiments can implement the components as two or more integrated circuits. Any level of integration or different components can be used.
    [0037] Now, with reference to figure 2, a block diagram illustrating a modality of performance configuration records 30 is shown. In the illustrated embodiment, registers 30 include register set 30A, register set 30B and register set 30C. Registry set 30B can include a setting for each performance domain, and for the sleep state and the activation state. Accordingly, the illustrated set supports up to "n" performance domains, where "n" is a positive integer. The sleep state for a given performance domain indicates the performance state for the domain in response to the processor entering the sleep state. The activation state for the given performance domain indicates the performance state for the domain in response to the processor coming out of sleep.
    [0038] In some modalities, the 30B records can directly store the values that define the performance state to be established in the corresponding energy domain. In such cases, the software that prepares the integrated circuit 10 for a sleep state of the processors 16A-16B can program each register 30B for the sleep state and the activation state below, according to the activity in the system.
    [0039] In the illustrated modality, the 30B records can store the indicators to the 30A or 30C record sets, where a set of records to which the indicator refers depends on the performance domain corresponding to that record. In some embodiments, there may be record sets similar to 30A or 30C for each performance domain. Alternatively, similar performance domains can share record sets. For example, if the processor's 14A and 14B performance domains are the same in terms of performance characteristics that can be changed, the 14A-14B performance domains can share the same 30A or 30C record sets. Each record set 30A and 30B can store the performance state settings for the corresponding performance domain. Accordingly, the software can program a set of performance states in register sets 30A or 30C and then select a suitable performance state for both the processor suspension transition and the processor activation transition before performing the transition to the processor in the sleep state. The selection can be made by recording the indicator in each record that corresponds to the performance domain in the 30B records. Accordingly, performance states can be dynamically modified based on activity in the system before each sleep state transition.
    [0040] Providing performance state settings to processor enable state can allow multiple performance domains to automatically transition to a performance state that is different from the performance state of the performance domain before the processor that goes into sleep state. So, for example, if the software can predict the operations that can be performed when the processor is activated, a performance state that is desirable for these operations can be established even in the case that the activation performance state is different from the activation state. performance before the processor transitioning from sleep state.
    [0041] In some embodiments, the 30B registers may include a valid bit or other indication used to indicate whether or not a transition is to occur in the corresponding performance domain. Thus, a performance domain that is more efficient in a given performance state at all times can be left unmodified by clearing the valid bit. Or, a performance domain that is disabled can be prevented from becoming enabled during a performance domain transition.
    [0042] The 30B records can also include a record that can be written by the software to indicate that the suspension transition is being initiated. PMU 28 can be configured to monitor an update to the suspend command record, and can be configured to perform the suspension transition from the processor and various other state transitions from the performance domain. Alternatively, the software can use processor instruction execution mechanisms to bring the processor into sleep, and PMU 28 can be configured to perform other performance domain state transitions.
    [0043] The PMU 28 can also be configured to monitor interruptions or other events that will cause the processor to be activated, in order to perform the performance state transitions to exit the performance state. In some embodiments, the PMU 28 can also be configured to monitor processor operation to automatically detect a processor that enters a sleep state (for example, without the processor recording a command to a suspend command record).
    [0044] In some cases, one or more performance domains can be more precisely linked to a specific processor in multiple processor configurations. In such cases, the closely linked performance domains can transition to different performance states in response to the corresponding processor entering the sleep state, while other performance domains that are closely linked to a still active processor can do not transition. Whether the transition of performance domains is controlled by hardware or not by PMU 28, or controlled by software using valid indications in the performance configuration records, as described above. Alternatively, transitions can be performed when the last of the processors enters the suspend state (while the other processors are already in the suspend state) and transitions to exit the suspend state can be performed when the initial processor exits sleep state (for example, in response to an external outage).
    [0045] The 30A set can store various performance state settings (up to "m" settings, where "m" is a positive integer). Thus, for example, several registers in set 30A can store the voltages (VO, V1), which operate the frequencies (FO, F1), and / or other performance status information for performance domain 0 (PDO). The 30C register set can also store various performance state settings (up to "p" settings, where "p" is a positive integer) for the performance domain "n". The integers n, m, and p do not have to be the same.
    [0046] In some modalities, the integrated circuit can support a certain pair of voltage and clock frequency (for example, there may be a minimum supply voltage to operate at a certain clock frequency). Although the clock voltage and frequency settings in registers 30B and 30C may not violate the minimum supply voltage, in some cases it may be desirable to use a supply voltage other than the minimum. For example, if the software predicts that a first clock frequency is the correct frequency to return to a performance domain when the processor comes out of sleep, but a higher clock frequency may be the correct setting if the forecast is wrong , the corresponding voltage in registers 30B and 30C may be the voltage used for the highest frequency. In this way, if the predicted frequency is incorrect, the supply voltage may already be adjusted to the desired magnitude, reducing the delay when making the adjustment to correct the performance state when a wrong forecast occurs.
    [0047] Next, with reference to figure 3, a flowchart is shown that illustrates the operation of a modality of the PMU 28 and the clock / voltage control unit 32 to manage the performance state transitions in the performance domains when a processor is entering or exiting the sleep state. Although the blocks are shown in a specific order to facilitate understanding, other orders can be used. The blocks can be performed in parallel in combinatorial logic on the PMU 28 and / or on the clock / voltage control unit 32. The blocks, block combinations, and / or the flowchart as a whole can be channeled into multiple clock cycles . In particular, decision blocks 40 and 48 can be independent and can be carried out in parallel or in both orders. PMU 28 and / or clock / voltage control unit 32 can be configured to implement the operation shown in figure 3.
    [0048] PMU 28 can detect that the processor is entering (or is about to enter) the sleep state, or that a last processor in a processor set is about to enter the sleep state, while other processors are in the sleep state in some modalities (decision block 40, part "yes"). In various modalities, detection can occur by monitoring 16A-16B processors, by receiving a command in the suspend command register, etc. The PMU 28 can load the suspended performance state for each performance domain from the performance configuration records 30 (block 42). In some embodiments, an indication of whether the performance state is valid in the records 30 may qualify whether the performance state is loaded or not. If the performance state includes changes in supply voltage and / or clock frequency, PMU 28 can provide values that specify the voltage / frequency for the clock / voltage control unit 32. If the performance state includes other changes (for example, changing the cache size, changing the interface size, etc.), the PMU 28 can transmit the changes to the corresponding component. PMU 28 and / or clock / voltage control unit 32 can transition from performance domains to new performance states (block 44). Changes in the supply voltage can be transmitted to the power supply 12, and the timing of adjusting to a new voltage can be determined. The clock frequency changes can be programmed in the clock generation circuitry in the clock / voltage control unit 32 and the timing to adjust to a new frequency can be determined if necessary (for example, the time for PLL to lock the a new frequency). For other changes, the component can be signaled to switch to the new state. If the time is needed to implement the change (for example, clearing the part of the cache that is disabled, resetting the components on an interface that has modified widths, etc.), that time can be determined. In one embodiment, the PMU 28 can record a timestamp (for example, in a performance configuration record 30 dedicated to storing a timestamp) that indicates a time when a performance state transition was made. finished. The software can capture the date / time stamp for statistical analysis to determine the effectiveness of energy savings in the system, for example. The date / time stamp can be captured in any desired way. For example, the system may include a free run counter that is increased or decreased at a regular interval. The system can capture the counter value as a date / time stamp.
    [0049] PMU 28 can detect that a processor is leaving the sleep state (or is about to leave the sleep state) (decision block 48, part "yes"). In various modalities, detection can occur by monitoring 16A-16B processors (for example, to detect an interruption being made to one of the processors), etc. The PMU 28 can load the performance state enabled for each performance domain from the performance configuration records 30 (block 50). Similar to the discussion above regarding loading the suspended performance states, several communications can occur to implement the new performance state configuration. The PMU 28 and / or the clock / voltage control unit 32 can transition from the performance domains to the new performance states (block 52), and can record a time stamp when the transition has ended (block 54 ). The date / time stamp for activation can be recorded in a different record than the date / time stamp recorded for suspension, to allow the software to capture both date / time stamps once the processor is in suspension between timestamp captures.
    [0050] Next, with reference to figure 4, a block diagram that illustrates a software structure that can be implemented in a system modality is shown. The software can include one or more application programs (Apps), an operating system (OS), and various other software 60. Software 60 can interact with various drivers when using system components. For example, a graphics driver 62 can be used for graphics unit 20; an audio driver 64 can be used for audio unit 22; a network driver 66 can be used for the networking device 24; other peripheral drivers 68 can be used for other peripherals 24; and a PMU 70 driver can be used for PMU 28. Accordingly, if software 60 communicates with graphics unit 20, software 60 calls graphics driver 62, etc. Each of the drivers can communicate with the corresponding components.
    [0051] Additionally, each of the 62, 64, 66 and 68 drivers can communicate with the PMU 70 driver. The PMU 70 driver can monitor activity on the components driven by drivers 62, 64, 66 and 68 in a table device activity 72. Monitored activities may include enabling and disabling the corresponding components. Monitored activities may also include changes to other performance characteristics of the unit. Based on the activities that are monitored, the PMU 70 driver can select the performance state for each performance domain to be used in the suspension and activation settings of the performance configuration records 30. Additionally, other information can be encoded in the device activity table (for example, performance needs several components when the processor is in sleep state) which can also affect selected performance states.
    [0052] Software 60 can also communicate directly with the PMU 70 driver. For example, in addition to the performance state transitions carried out for the suspension and activation transitions in processors, software 60 can also change the states of performance directly based on activity in the system as a whole. That is, even if the processors do not go to sleep, changes in the performance state of one or more performance domains may be desirable. Software 60 can directly request such changes.
    [0053] Next, with reference to figure 5, a flow chart illustrating the operation of a modality of the PMU 70 driver is shown. The PMU 70 driver can include instructions that, when executed on the system, implement the operation described in the flowchart. Although the blocks are shown in a specific order to facilitate understanding, other orders can be used.
    [0054] If a component driver 62, 64, 66 or 68 receives a request to enable or disable the device, the driver can transmit the request to the PMU 70 driver. The PMU 70 driver can receive the e request (block of decision 80, part "yes") record the enabling or disabling event in the activity table of device 72 (block 82). In some modes, the PMU 70 driver can enable or disable devices. In other modalities, the corresponding component driver can perform the enable / disable and can call the PMU 70 driver to record the event.
    [0055] In some modalities, the PMU 70 driver can monitor other events in a given component. The component driver can also report these events to the PMU 70 driver. Upon receipt of such events (decision block 84, part "yes"), the PMU 70 driver can record the event in the device activity table (block 82).
    [0056] The PMU 70 driver can determine whether the events recorded in the device activity table 72 indicate that a change in the performance state for one or more performance domains should be performed. In addition, software 60 can directly request a change in one or more performance domains. In both cases (decision block 86, part "yes"), the PMU 70 driver can prepare the corresponding hardware components for changing the performance state (for example, communicating the new performance characteristics - block 88), and can invoke the transition (block 90). Blocks 88 and 90 can thus represent a software-controlled performance state transition to one or more performance domains.
    [0057] The PMU 70 driver can also detect that a processor is preparing to enter the sleep state (decision block 92, part "yes"). The PMU 70 driver can determine the desired sleep and activation states for the performance domains based on at least part of the activity table for device 72 (block 94). The PMU 70 driver can update performance configuration records 30 to select performance states, if necessary (block 96), and can transmit the suspend command to PMU 28 to perform performance state transitions (for example, record the suspension command record in PMU 28) (block 98). Other modalities can detect the processor entering the sleep state directly, and can perform the performance state transitions based on that detection. Such modalities can eliminate block 98.
    [0058] Accordingly, blocks 94 and 96 can represent the programming of the PMU 28 with the performance states for the performance domains, for both sleep and activation state transitions in the processor (s). Computer accessible Storage System and Media
    [0059] Next, with reference to figure 6, a block diagram of a modality of a system 150 is shown. In the illustrated embodiment, the system 150 includes at least one instance of an integrated circuit 10 (of figure 1) coupled to one or more peripherals 154 and an external memory 158. A power supply 156 is also provided that supplies the supply voltages to the integrated circuit 10 as well as one or more supply voltages to memory 158 and / or peripherals 154. The power supply 156 may include the power supply 12 shown in figure 1, for example. In some embodiments, more than one instance of integrated circuit 10 may be included (and more than one external memory 158 may also be included).
    [0060] Peripherals 154 can include any set of circuits desired, depending on the type of system 150. For example, in one embodiment, system 150 can be a mobile device (for example, a personal digital assistant (PDA), a smartphone , etc.) and peripherals 154 may include devices for various types of wireless communication, such as wifi, Bluetooth, mobile, global positioning system, etc. Peripherals 154 may also include additional storage, which includes RAM storage, solid state storage, or disk storage. Peripherals 154 may include user interface devices, such as a display screen, which includes touch or multi-touch display screens, keyboards or other data entry devices, microphones, speakers , etc. In other embodiments, system 150 can be any type of computing system (for example, desktop personal computer, laptop, workstation, nettop, etc.).
    [0061] External memory 158 can include any type of memory. For example, the external memory 158 can be SRAM, dynamic RAM (DRAM) as well as synchronized DRAM (SDRAM), SDRAM, RAMBUS DRAM of double data rate (DDR, DDR2, DDR3, etc.), etc. External memory 158 can include one or more memory modules to which memory devices are mounted, such as single in-line memory modules (SIMMs), dual in-line memory modules (DIMMs), etc.
    [0062] Now, with reference to figure 7, a block diagram of a computer accessible storage medium 200 is shown. In general, a computer-accessible storage medium can include any storage medium that can be accessed by a computer during use to provide instructions and / or data to the computer. For example, a computer accessible storage medium may include the storage medium, such as the magnetic medium or the optical medium, for example, disk (fixed or removable), tape, CD-ROM, DVD-ROM, CD-R, CD-RW, DVD-R, DVD-RW, or Blu-Ray. The storage medium may also include volatile or non-volatile memory medium, such as RAM (for example, synchronized dynamic RAM (SDRAM), DRAM Rambus (RDRAM), static RAM SRAM), etc.), ROM, flash memory, memory non-volatile (for example, flash memory) accessible through a peripheral interface, such as the Universal serial bus interface (USB), a flash memory interface (FMI), a peripheral interface would be (SPI), etc. The storage medium can include microelectromechanical systems (MEMS), as well as the storage medium that can be accessed through a communication medium, such as a network and / or a wireless link. The computer accessible storage medium 200 in Figure 7 can store one or more of the software 60, the graphics driver 62, the audio driver 64, the network driver 66, other peripheral drivers 68, the PMU driver 70, and / or the device activity table 72. The PMU driver 70 can include instructions that, when executed, implement the operation described above with respect to figure 5. In general, the computer accessible storage medium 200 can store any set instructions that, when executed, implement part or all of the operations shown in figure 5. A carrier medium may include the computer accessible storage medium, as well as the transmission medium, such as wired or wireless transmission.
    [0063] Numerous variations and modifications will be evident to those skilled in the art once the above description is fully observed. The following claims must be interpreted to cover all such variations and modifications.
    权利要求:
    Claims (11)
    [0001]
    1. Integrated circuit (10), comprising: at least one processor (16A, 16B); one or more records (30) that can be programmed to indicate one or more performance states; and a control circuit (28) coupled to one or more registers (30) and the processor (16A, 16B), where the control circuit (28) is configured to detect that the processor (16A, 16B) is coming into contact a low performance state, and where the control circuit (28) is configured to change a performance state of at least one performance domain (14A, 14B, 14C, 14D, 14E, 14F) in the integrated circuit (10) for a first performance state of one or more performance states in response to the processor (16A, 16B) which enters the low performance state; characterized by the fact that the control circuit (28) is configured to detect that the processor (16A, 16B) is leaving the low performance state, and that the control circuit (28) is configured to change the performance state from at least one performance domain (14A, 14B, 14C, 14D, 14E, 14F) on the integrated circuit (10) to a second performance state of one or more performance states in response to the outgoing processor (16A, 16B) the low performance state; and in that the second performance state differs from a third performance state that was in effect before the processor (16A, 16B) entered the low performance state.
    [0002]
    2. Integrated circuit (10) according to claim 1, characterized by the fact that the at least one performance domain (14A, 14B, 14C, 14D, 14E, 14F) includes the processor (16A, 16B).
    [0003]
    3. Integrated circuit (10), according to claim 2, characterized by the fact that the control circuit (28) is configured to register a first timestamp that indicates a time at which the change to the first performance state has ended, and the control circuit (28) is configured to register a second timestamp indicating a time at which the change to the second performance state has ended.
    [0004]
    4. Integrated circuit (10) according to claim 1, characterized by the fact that it additionally comprises: a plurality of components (16A, 16B, 18, 20, 22, 24, 26), each component included in one of a plurality of performance domains; and wherein the control circuit (28) is configured to transmit at least a second performance domain from the plurality of performance domains (14A, 14B, 14C, 14D, 14E, 14F) to a fourth performance state programmed in the registers ( 30) in response to the processor (16A, 16B) that transitions to a different performance state, where the first performance domain (14A, 14B, 14C, 14D, 14E, 14F) does not include the processor (16A, 16B ).
    [0005]
    5. Integrated circuit (10), according to claim 4, characterized by the fact that the second performance domain corresponds to one or more components (18, 20, 22, 24, 26) that are active during a time when the processor (16A, 16B) is in a low performance state.
    [0006]
    6. Integrated circuit (10), according to claim 4, characterized by the fact that the processor (16A, 16B) is configured to execute a plurality of instructions to monitor the activity in the plurality of components (16A, 16B, 18, 20, 22, 24, 26); and to program registers (30) to indicate performance states for the plurality of performance domains (14A, 14B, 14C, 14D, 14E, 14F) to be used in response to the incoming processor (16A, 16B) in the low power state and to indicate the other performance states to be used in response to the processor (16A, 16B) leaving the low performance state.
    [0007]
    7. Integrated circuit (10) according to claim 6, characterized by the fact that the processor (16A, 16B) is configured to execute the plurality of instructions in response to a request to activate a first component of the plurality of components ( 16A, 16B, 18, 20, 22, 24, 26), and where activity monitoring includes recording an indication of the activation of the first component.
    [0008]
    8. Integrated circuit (10) according to claim 6, characterized in that the processor (16A, 16B) is configured to execute the plurality of instructions in response to a request to disable a second component of the plurality of components ( 16A, 16B, 18, 20, 22, 24, 26), and where activity monitoring includes recording an indication of the deactivation of the second component.
    [0009]
    9. Method, which comprises the steps of: a processor (16A, 16B) entering a low performance state in a system; a control circuit (28) causes a performance domain (14A, 14B, 14C, 14D, 14E, 14F) of the system to transition to a first performance state to operate during a time when the processor (16A, 16B) is in the low performance state, where the first performance state can be programmed in the control circuit (28); characterized by the fact that it still comprises the control circuit (28) detecting that the processor (16A, 16B) is leaving the low performance state; and the control circuit (28) still causes the performance domain (14A, 14B, 14C, 14D, 14E, 14F) to transition to a second performance state to operate subsequent to the processor (16A, 16B) that leaves the low performance state, where the second performance state is programmed in the control circuit (28), and the second performance state differs from a third performance state that was in effect in the performance domain (14A, 14B , 14C, 14D, 14E, 14F) before the processor (16A, 16B) enters the low performance state.
    [0010]
    10. Method, according to claim 9, characterized by the fact that it additionally comprises determining the first performance state to program in the control circuit (28) in response to the system monitoring operation.
    [0011]
    11. Method, according to claim 10, characterized by the fact that it additionally comprises: continue to monitor the system; and reprogramming the control circuit (28) with a fourth performance state in response to continuous monitoring.
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    同族专利:
    公开号 | 公开日
    BR112012025292A2|2017-08-01|
    EP3872604A1|2021-09-01|
    EP2375305B1|2018-06-06|
    US20140122908A1|2014-05-01|
    US20110252251A1|2011-10-13|
    JP2013524367A|2013-06-17|
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    TW201202915A|2012-01-16|
    WO2011127128A1|2011-10-13|
    US8959369B2|2015-02-17|
    JP5697278B2|2015-04-08|
    EP2375305A3|2017-05-03|
    US8443216B2|2013-05-14|
    AU2011237758B2|2013-10-03|
    GB2479452A|2011-10-12|
    CN102213998B|2014-03-26|
    MX2012011619A|2012-11-30|
    TWI533117B|2016-05-11|
    EP2375305A2|2011-10-12|
    KR20110112791A|2011-10-13|
    US8271812B2|2012-09-18|
    AU2011237758A1|2012-09-20|
    US20130232364A1|2013-09-05|
    EP3367212A1|2018-08-29|
    GB2479452B|2012-07-18|
    CN102213998A|2011-10-12|
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    法律状态:
    2018-12-26| B06F| Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]|
    2019-09-17| B06U| Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]|
    2020-06-09| B09A| Decision: intention to grant [chapter 9.1 patent gazette]|
    2020-11-03| B16A| Patent or certificate of addition of invention granted|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 06/04/2011, OBSERVADAS AS CONDICOES LEGAIS. |
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