• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    TWO SIDES INTERCONNECTED CMOS FOR STACKED INTEGRATED CIRCUITS. A stacked integrated circuit (IC) can be manufactured with a second blade connected to a first flush blade on two sides. The first two-sided flush blade includes rear end layers (BEOL) on the front and back sides of the blade. Contacts extended inside the first leveled blade connect the BEOL layers on the front and back sides. The extended contact extends through a junction of the first level blade. The second leveled blade is coupled to the front side of the first leveled blade through the extended contacts. Additional contacts connect the device within the first leveled blade to the BEOL layers on the front. When double-sided blades are used in stacked CIs, the height of the stacked CIs can be reduced. Stacked CIs can include slides with identical functions or slides with different functions.
    公开号:BR112012025183B1
    申请号:R112012025183-0
    申请日:2011-04-06
    公开日:2021-01-19
    发明作者:Arvind Chandreaskaran；Brian Henderson
    申请人:Qualcomm Incorporated；
    IPC主号:
    专利说明:

    TECHNICAL FIELD
    [001] The present disclosure refers in general to integrated circuits. More specifically, the present disclosure relates to the packaging of integrated circuits. BACKGROUND
    [002] Stacked ICs increase the functionality of the devices and decrease the area occupied by the vertical stacking of the matrices. In stacked CIs, a second matrix is stacked on top of a first matrix, allowing the construction to expand in three dimensions (3D). Stacked CIs allow products with a greater number of components to fit small form factors. The component density of a semiconductor matrix is the number of components in the matrix divided by the area of the matrix. For example, stacking a matrix on an identical matrix approximately results in doubling the number of components in the same area, in order to double the density of components. When a second matrix is stacked on top of a first matrix, the two matrices share the same packaging and communicate with external devices through the packaging.
    [003] The matrices can be stacked using several methods, which include Package-over-Package (PoP) processes and stacking-through-silicon (TSS) processes. In some applications, however, the height of the stacked CI is restricted. For example, ultra-thin cell phones may not support stacked ICs that have multiple arrays. Thus, there is a need to reduce the thickness of stacked CIs. BRIEF SUMMARY
    [004] According to one aspect of the development, a stacked integrated circuit is presented that includes a first leveled blade. The stacked integrated circuit also includes a first extended contact that extends through a joint on the first level blade to provide electrical connectivity through the first level insert. The stacked integrated circuit also includes a second level blade attached to the first level blade. The second leveled blade includes an electrical component electrically coupled to the first extended contact.
    [005] According to another aspect of the disclosure, a method for making a stacked integrated circuit includes thinning a first level blade to expose an extended contact that extends through a junction of the first level blade, the extended contact being coupled to posterior end layers on the anterior side. The method also includes depositing a dielectric on the first leveled blade after thinning the first leveled blade. The method also includes depositing layers of the posterior end of the posterior side on the dielectric, the layers of posterior end of the posterior side coupling to the extended contact. The method also includes attaching a second leveled blade to the first leveled blade after depositing the rear end layers on the rear side, so that the circuitry on the second leveled blade is coupled to the rear end layers on the front side through the extended count. .
    [006] According to another aspect of the disclosure, a method for making a stacked integrated circuit includes the steps of thinning a first leveled blade in order to expose an extended contact that extends through at least one of a region of origin and a drain region of the first leveled blade, the extended contact being coupled to posterior end layers on the anterior side. The method also includes the step of depositing a dielectric on the first leveled blade after thinning the first leveled blade. The method also includes the step of depositing layers of the posterior layer of the posterior side on the dielectric, the layers of posterior end of the posterior side coupling to the extended contact. The method also includes the step of connecting a second leveled blade to the first level blade after deposition of the rear end layers on the rear side, so that the circuitry on the second leveled blade is coupled to the rear end layers on the front side. through extended contact.
    [007] According to another aspect of the disclosure, a stacked integrated circuit includes a first leveled blade that has a first rear end layer on an anterior side and that has a second rear end layer on a posterior side. The stacked integrated circuit also includes a device for coupling the first rear end layer to the second rear end layer via a junction of the first level blade. The stacked integrated circuit also includes a first contact attenuator on the rear side of the first level blade coupled to the second rear end layer. The stacked integrated circuit also includes a second level blade that has a third rear end layer on an anterior side. The stacked integrated circuit also includes a second contact attenuator on the front side of the second level blade coupled to the third rear end layer and coupled. to the first contact attenuator. The coupling device couples the third rear end layer to the first rear end layer.
    [008] What has been exposed above has somewhat outlined the features and technical advantages of the present revelation so that the following detailed description can be better understood. Additional features and advantages that form the subject of the claims of the disclosure will be described below. Those skilled in the art should understand that the specific design and modalities disclosed can be readily used as a basis for modifying or designing other structures to perform the same purposes as the present disclosure. Those skilled in the art should also realize that such equivalent constructions do not deviate from the disclosure technology presented in the appended claims. The unpublished features that are believed to be characteristics of the revelation, with regard to both their organization and the method of operation, together with other objects and advantages, will be better understood with the detailed description when considered in connection with the attached figures. It should be expressly understood, however, that each of the figures is presented for the purpose of exemplification and description only and is not intended to be a definition of the limits of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
    [009] For a more complete understanding of the present disclosure, reference is now made to the following description, taken in conjunction with the accompanying drawings.
    [0010] Figure 1 is a cross-sectional view showing a conventional semiconductor matrix.
    [0011] Figure 2 is a flow chart showing an exemplary process for manufacturing interconnected integrated circuits on two sides according to a modality.
    [0012] Figures 3A-G are seen in cross-section showing an exemplary process for manufacturing interconnected integrated circuits on two sides according to a modality.
    [0013] Figure 4 is a block diagram showing an exemplary wireless communication system in which a modality can be advantageously used.
    [0014] Figure 5 is a block diagram showing a projected workstation used in circuit design, layout and logic of a semiconductor component according to a modality. DETAILED DESCRIPTION
    [0015] The height reduction of stacked integrated circuits (ICs) can be carried out with interconnected integrated circuits on two sides. According to one modality, a combination of regular and extended contacts is etched into an integrated circuit. Regular contacts allow coupling to the front and rear sides of the integrated circuit. Double-sided integrated circuits allow the construction of ultra-thin stacked integrated circuits. In addition, level connections for very high density levels in the stacked IC are made possible.
    [0016] Figure 1 is a cross-sectional view showing a conventional semiconductor matrix. The crude semiconductor layer 102, of silicon, for example, includes a source region 104 and a drain region 106. Hollow isolation regions 108 isolate regions 104, 106 from other regions in crude semiconductor layer 102. A structure of port 112 is formed between regions 104, 106 and over crude semiconductor layer 102. A dielectric layer 110 is deposited over crude semiconductor layer 102 and port structure 112. Contacts 114, 116 extend across the layer dielectric 110 to regions 104, 106, respectively. The contacts 114, 116 also couple with metal layers 122 in back end layers (BEOL) 120. The BEOL 120 layers can also include a dielectric layer 124. A dielectric layer 130 is deposited on the BEOL layers 120 and a structure of packaging 132, such as a reversible chip protrusion, for example, attaches to the metal layers 122.
    [0017] Figure 2 is a flowchart showing an exemplary process for manufacturing interconnected integrated circuits on two sides according to one modality. An exemplary process 200 is shown with cross-sectional views of Figures 3A-3G according to an embodiment.
    [0018] Exemplary process 200 begins at block 205 with the receipt of a first leveled blade 300. The first leveled blade 300 may have a completed front end processing (FEOL). The exemplary process 200 continues to block 210 with the front side mounting of the first level blade 300 on a carrier blade 340. Figure 3A is a cross-sectional view showing a first level blade mounted on the carrier blade 340 according to a modality. The first leveled blade 300 includes a crude semiconductor layer 302, which has a source region 304 and a drain region 306. Hollow insulation regions 308 isolate regions 304, 306 from other regions in the crude semiconductor layer 302. A structure of gate 312 is formed between regions 304, 306 and on the raw semiconductor layer 302. A dielectric layer 310 is deposited on the raw semiconductor layer 302 and on the gate structure 312. An extended contact 314 and a contact 316 extend through the dielectric layer 310 to regions 304, 306, respectively, forming junctions. According to one modality, contacts 314, 316 are taken from tungsten. Contacts 314, 316 are also coupled to metal layers 322 in BEOL 320 layers. In some embodiments, the extended contact 314 is formed after the formation of regions 304, 306 and door frame 312. According to one embodiment, the extended contact 314 extends through at least one of regions 304, 306. Although not shown in Figure 3A, the junction can be a diode.
    [0019] In addition, a barrier layer (not shown) may be present between extended contact 314 and regions 304, 306. The barrier layer reduces metal contamination between extended contact 314 and regions 304, 306. The BEOL 320 layers may also include a dielectric layer 326. Dielectric layer 330 is deposited on BEOL 320 layers, and a housing structure 332, such as, for example, a reversible chip protrusion, attaches to metal layers 322 The carrier blade 340 is mounted on the first level blade 300. The carrier blade 340 provides support for the first level blade 300 during further processing.
    [0020] The exemplary process 200 continues until block 212 with the thinning of the first leveled blade 300. Figure 3B is a cross-sectional view showing a first leveled blade after thinning according to an embodiment. The raw semiconductor layer 302 of the first leveled blade 300 is thinned so as to expose region 304, region 306 and extended contact 314. According to one embodiment, the thinning includes a recessed engraving.
    [0021] The exemplary process 200 continues until block 214 with the deposition of a dielectric layer 342 on the first leveled blade 300. Figure 3C is a cross-sectional view showing a first leveled blade after the deposition of the dielectric according to a modality. The dielectric layer 342 is deposited on the first leveled blade 300. The dielectric layer 342 can be of silicon dioxide, for example. According to one embodiment, a conformal dielectric layer 342 is deposited in order to cover the extended contact 314. In this embodiment, a chemical-mechanical polishing (CMP) causes the dielectric layer 342 in order to expose the extended contact 314 and in order to leaving the dielectric layer 342 at a level substantially similar to that of the extended contact 314.
    [0022] The exemplary process 200 continues until block 216 with posterior lateral BEOL processing. Figure 3D is a cross-sectional view showing a first level blade after BEOL processing according to an embodiment. During BEOL processing, the BEOL 350 layers, which include a dielectric layer 354, the metal layers 352 and the contact attenuator 356, are deposited on the first level blade 300. According to one embodiment, micro-kneading is also performed on the first leveled blade 300 as part of the BEOL processing. The first leveled blade 300 has two sides because the BEOL layers 320, 350 are located on the front and rear sides of the first leveled blade 300, respectively.
    [0023] The exemplary process 200 continues until block 218 with the connection of a second level blade 360 to the first level blade 300. Figure 3E is a cross-sectional view showing a first level blade connected to a second level blade according to with a modality. The second leveled blade 360 includes a crude semiconductor layer 362, which has a source region 364 and a drain region 366. A port structure 372 is located on crude semiconductor layer 362 between regions 364, 366. Regions of dug insulation 368 separates regions 364, 366 from other source and drain regions (not shown) in the raw semiconductor layer 362. A dielectric layer 384 is deposited on the raw semiconductor layer 362 and on the port structure 372. One contact extended 374 and regular contact 376 extend through dielectric layer 384 to regions 364, 366, respectively. The BEOL 380 layers include the metal layers 382 and a dielectric layer 386. In addition, a contact attenuator 388 is coupled to the metal layers 382.
    [0024] The second leveled blade 360 is coupled to the first leveled blade 300 through the contact attenuator 388 of the second leveled blade 360 and the contact attenuator 356 of the first leveled blade 300. According to one embodiment, the first leveled blade 300 is coupled to the second leveled blade 360 through a copper-copper connection.
    [0025] The exemplary process 200 continues until block 220 with the thinning of the second leveled blade 360. Figure 3F is a cross-sectional view showing a stacked integrated circuit after the thinning of the second leveled blade according to a modality. The raw semiconductor layer 362 of the second level blade 360 is thinned so as to expose the extended contact 374.
    [0026] After the thinning of the second leveled blade 360 in block 220, the exemplary process continues up to block 232 to perform the BEOL processing on the second leveled blade 360. Again with reference to Figure 3E, the BEOL 390 layers are deposited on the second level blade 360, including a dielectric layer 394 and metal layers 392, and a contact attenuator 396 is coupled to the metal layers 392. According to one embodiment, the BEOL 390 layers and the contact attenuator 396 are not deposited on the second leveled blade 360 if no additional levels are stacked on the second leveled blade 360.
    [0027] The exemplary process 200 continues until decision block 230 in order to determine whether additional levels will be stacked in the stacked CI. If additional levels exist, the exemplary process 200 continues up to block 218 for the umpteenth level (third level, for example). If no additional levels exist, the exemplary process 200 continues to block 222.
    [0028] In block 222 of the exemplary process 200, the first leveled blade 300 is disassembled from the carrier blade 340. Figure 3G is a cross-sectional view showing a stacked integrated circuit after disassembling the carrier blade according to one embodiment. After disassembly, the packaging structure 332 is exposed for further processing.
    [0029] Although the 200 exemplary process is shown with slides, the 200 exemplary process can also be performed when matrices are stacked. For example, after a first leveled blade is attached to a carrier blade, the second, third or umpteenth blade can be a blade or a matrix.
    [0030] The exemplary process for stacking integrated circuits described above includes two-sided interconnections to reduce the height of the stacked IC. The process can be applied to stacked CIs that have identical blades or heterogeneous blades with different functions. For example, a stacked IC manufactured using the exemplary process may include an application-specific integrated circuit (ASIC) on the first leveled blade and a memory on the second leveled blade. The formation of extended contacts on the blades costs less than through silicon pathways (TSV), and the extended contacts can be manufactured in sub-micron sizes that reduce the parasitic capacitance of the contact. For example, extended contacts can be 50-100 nanometers in diameter at 45-65 nanometer process nodes.
    [0031] Another advantage of two-sided integrated circuits is the placement of BEOL layers on the front and back sides of the blade. Two sets of BEOL layers allow for improved spinning efficiency compared to a single set of BEOL layers. In addition, high density level connections are possible at a transistor level or at a macro level and may include power and ground connections. For example, level connections with a level of 104-105 connections / square millimeters are possible.
    [0032] Figure 4 shows a wireless communication system 400 in which a disclosure modality can be used to advantage. For purposes of illustration, Figure 4 shows three remote units 420, 430 and 450 and two base stations 440. It should be recognized that wireless communication systems can have many more remote units and base stations. Remote units 420, 430 and 450 include stacked ICs 425 A, 425 C and 425B, respectively, which are the modalities discussed above. Figure 4 shows direct link signals 480 from base stations 440 and remote units 420, 430 and 450 and reverse link signals 450 from remote units 420, 430 and 450 to base stations 440.
    [0033] In Figure 4, the remote unit 420 is shown as a mobile phone, the remote unit 430 is shown as a portable computer and the remote unit 450 is shown as a computer in a wireless local loop system. For example, remote units can be cell phones, mobile phones, computers, set-top box converters, music players, video devices, entertainment units, personnelless communication system units (PCS), portable data units such as such as personal data assistants or fixed location data units, such as metric reading equipment. Although Figure 4 shows remote units according to the teachings of the revelation, the revelation is not limited to these exemplary shown units. The revelation can be used appropriately on any device that includes stacked CIs.
    [0034] Figure 5 is a block diagram showing a workstation designed for circuit, layout and logic design of a semiconductor component, as shown below. A designed workstation 500 includes a 501 hard drive, which contains operating system software, support files, and designed software, such as Cadence or OrCAD. The designed workstation 500 also includes a monitor to facilitate the design of a circuit 510 or semiconductor component 512, such as a blade or matrix. A storage medium 504 is installed to tangibly store circuit design 510 or semiconductor component 512. Circuit design 510 or semiconductor component 512 can be stored on storage medium 504 in a file format such as GDSII or GERBER. The storage medium 504 can be a CD-ROM, a DVD, a hard disk, a flash memory or other appropriate device. In addition, workstation 500 includes drive equipment 503 to receive input from or record output to storage medium 504.
    [0035] The data recorded on the storage medium 504 can specify logic circuit configurations, standardized data for photolithography masks or standardized mask data for serial recording tools, such as electron beam lithography. The data may also include logic check data such as timing diagrams or network circuits associated with logic simulations. Providing data in storage medium 504 facilitates the design of circuit design 510 or semiconductor component 512 by decreasing the number of processes for designing semiconductor sheets.
    [0036] The methodologies described here For example, these techniques can be implemented by several components depending on the application. For example, these methodologies can be implemented in hardware, firmware, software or any combination of them. For a hardware implementation, processing units can be implemented within one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs) ), field programmable port arrangements (FPGAs), processors, controllers, microcontrollers, microprocessors, electronic devices, other electronic units designed to perform the functions described here or a combination of them.
    [0037] For an implementation in firmware and / or software, the methodologies can be implemented with modules (such as, for example, procedures, functions and so on) that perform the functions described here. Any machine-readable medium that embodies instructions in a tangible way can be used in the implementation of the methodologies described here. For example, software codes can be stored in memory (memory 182 in Figure 1, for example) and executed by a processor unit. The memory can be implemented inside the processor unit or outside the processor unit. As used herein, the term “memory” refers to any type of long-term, short-term, volatile, non-volatile or other memory and should not be limited to any specific type of memory or number of memories or type of medium in which the memory is stored.
    [0038] If implemented in firmware and / or software, the functions can be stored as one or more instructions or codes in a medium that can be read by a computer. Examples include computer-readable media encoded with a data structure and computer-readable media encoded with a computer program. Computer-readable media includes physical computer storage media. A storage medium can be any available medium that can be accessed by a computer. By way of example, and not by way of limitation, such a computer-readable medium may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices or any other medium that can be used to store desired program codes in the form of instructions or data structures and can be accessed by a computer; the term disc (DISK and DISC), as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disc and blu-ray disc, in which discs (DISKS) usually reproduce magnetically, while discs (DISCS) reproduce data optically with lasers. Combinations of them must also be included within the range of the computer readable media.
    [0039] In addition to storage in a medium that can be read by a computer, instructions and / or data can be provided as signals in means of transmission included in a communication equipment. For example, a communication device may include a transceiver that has signals that indicate instructions and data. Instructions and data are configured to have one or more processors implement the functions outlined in the claims.
    [0040] Although the terminology “via silicon path” includes the word silicon, it should be noted that silicon pathways are not necessarily built on silicon. Instead, the material can be any apparatus substrate material.
    [0041] Although the present disclosure and its advantages have been described in detail, it should be understood that several changes, substitutions and modifications can be made here without abandoning the disclosure technology defined by the attached claims. Furthermore, the scope of this application is not intended to be limited to the specific modalities of the process, machine, manufacture, composition of substances, devices, methods and steps described in the report. As will be readily understood by those skilled in the art from the disclosure, the processes, machines, manufacturing, compositions of substances, devices, methods or steps, which currently exist or will be further developed to perform substantially the same function or obtain substantially the same result the corresponding modalities described herein can be used in accordance with the present disclosure. Accordingly, the appended claims are intended to include, within its scope, such processes, machines, manufacture, compositions of substances, devices, methods or steps.
    权利要求:
    Claims (14)
    [0001]
    1. Stacked integrated circuit, characterized by the fact that it comprises: a first leveled blade (300; a first extended contact (314) that extends across opposite surfaces of a region of origin or a drain region in the first leveled blade (300 ) to provide electrical connectivity through the first leveled blade (300), a second leveled blade (360) attached to the first leveled blade (300), the second leveled blade including an electrical component (364, 366, 372) electrically coupled to the first contact extended (314); a first rear end layer (320) on the front side of the first level blade (300); a second rear end layer (350) on the back side of the first level blade (300), where the first contact extended (314) couples the first rear end layer (320) to the second rear end layer (350); a first contact attenuator (356) on the rear side of the first level blade ( 300) coupled to the second rear end layer (350); a third rear end layer (380) coupled to the electrical component (364, 366, 372) on an anterior side of the second level blade (360); and a second contact attenuator (388) on the front side of the second level blade (360) coupled between the third rear end layer (380) and the first contact attenuator (356), the first extended contact (314) coupling the third rear end layer (380) to the first rear end layer (320).
    [0002]
    2. Stacked integrated circuit according to claim 1, characterized in that it additionally comprises: a fourth rear end layer (390) on a rear side of the second level blade (360); a third contact attenuator (396) on the rear side of the second level blade (360) coupled to the fourth rear end layer (390); a second extended contact (374) on the second level blade (360) that couples the third rear end layer (380) to the fourth rear end layer (390); a third level blade having a fifth rear end layer on an anterior side of the third level blade; and a fourth contact attenuator coupled to the fifth rear end layer and coupled to the third contact attenuator, the first extended contact (314) and the second extended contact (374) coupling the fifth posterior end layer to the first posterior end layer ( 320.
    [0003]
    Stacked integrated circuit according to claim 1, characterized in that it additionally comprises a packaging structure (332) on the front side of the first level blade (300) coupled to the third rear end layer (380) through the first extended contact (314).
    [0004]
    4. Stacked integrated circuit according to claim 1, characterized in that a junction includes at least one of a region of origin (304) and a drain region (306) of the first level blade (300).
    [0005]
    5. Stacked integrated circuit according to claim 1, characterized in that the first extended contact (314) comprises a tungsten socket.
    [0006]
    6. Stacked integrated circuit, according to claim 1, characterized by the fact that it is integrated in at least one of a mobile phone (425A), a set-top box converter, a music player, a video device, a entertainment unit, a navigation device, a computer (425C), a personal communication system unit, PCS, handheld, a portable data unit and a fixed location data unit.
    [0007]
    7. Method (200) for making a stacked integrated circuit, characterized by the fact that it comprises: fine-tuning (212) a first level blade (300) in order to expose an extended contact (314) that extends across opposite surfaces of a region of origin and a drain region of the first leveled blade (300), the extended contact (314) coupled to end layers on the front side (320); depositing (214) a dielectric (342) on the first leveled blade (300) after the first leveled blade has been thinned (300); depositing (216) layers of the posterior end (350) of the posterior side on the dielectric (342), the layers of posterior end (240) of the posterior side coupling to the extended contact (314); forming a first contact attenuator (356) on the rear side of the first level blade (300) coupled to the second front end layer (350); depositing a third rear end layer (380) coupled to an electrical component (364, 366, 372) on an anterior side of a second level blade (360); connect (218) the second level blade (360) to the first level blade (300) after depositing the rear end layers (350) on the rear side by forming a second contact attenuator (388) on the front side of the second level blade (360) ) coupled between the third rear end layer (380) and the first contact attenuator (356) so that the circuitry (364, 366, 372) on the second level blade (360) is coupled to the rear end layers ( 320) from the front side through the extended contact (314).
    [0008]
    8. Method according to claim 7, characterized in that it additionally comprises: mounting (210) the first level blade (300) on a carrier blade (340) before thinning; and disassemble (222) the first level blade (300) from the carrier blade (340) after connecting the second level blade (360).
    [0009]
    Method according to claim 7, characterized in that it additionally comprises performing front end processing on the first level blade (300) prior to assembly (210) of the first level blade (300) on the carrier blade (340).
    [0010]
    10. Method according to claim 7, characterized by the fact that it further comprises fine-tuning (220) the second level blade (360) after the connection of the second level blade (360) with the first level blade (300) before disassembly (222) of the first level blade (300) of the carrier blade (340).
    [0011]
    11. Method according to claim 10, characterized in that the thinning (222) of the second level blade (360) exposes a second extended contact (374), the method further comprising: depositing (232) layers of the posterior end ( 390) on the second leveled blade (360) coupled to the second extended contact (374) after thinning (222) of the second leveled blade (360); and connecting (218) a third leveled blade to the second leveled blade (360) after deposition (232) of rear end layers (390) on the second leveled blade (360).
    [0012]
    Method according to claim 7, characterized in that the thinning (212) of the first leveled blade (300) comprises performing a recess etching on the first leveled blade (300).
    [0013]
    13. Method according to claim 7, characterized in that it deposits (214) the dielectric (342) on the first leveled blade (300) comprises: depositing conformally (214) the dielectric (342) on the first blade level (300); and perform chemical-mechanical polishing on the dielectric (342).
    [0014]
    14. Method, according to claim 7, characterized by the fact that it additionally comprises integrating the stacked integrated circuit to at least one of a mobile phone (425A), a set-top box converter, a music player, an audio device video, an entertainment unit, a navigation device, a computer (425C), a personal communication system unit, PCS, handheld, a portable data unit and a fixed location data unit.
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    法律状态:
    2018-12-26| B06F| Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]|
    2019-08-20| B06U| Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]|
    2020-03-31| B07A| Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]|
    2020-10-27| B09A| Decision: intention to grant [chapter 9.1 patent gazette]|
    2021-01-19| B16A| Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 06/04/2011, OBSERVADAS AS CONDICOES LEGAIS. |
    优先权:
    申请号 | 申请日 | 专利标题
    US12/758,164|US8525342B2|2010-04-12|2010-04-12|Dual-side interconnected CMOS for stacked integrated circuits|
    US12/758,164|2010-04-12|
    PCT/US2011/031386|WO2011130078A1|2010-04-12|2011-04-06|Dual-side interconnected cmos for stacked integrated circuits|
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