memory system with multiple instruction streams

专利摘要:
MEMORY SYSTEM WITH MULTIPLE INSTRUCTION FLOWS This is a system comprising a processor that processes two strings, a memory device in communication with the processor, the memory device receiving an input address signal and comprising a plurality of groups of memory cells, each group of memory cells including two non-volatile memory cells that have the same input address, each memory cell including a resistive memory element and associated with a corresponding string.
公开号:BR112012023650B1
申请号:R112012023650-4
申请日:2011-03-22
公开日:2020-12-01
发明作者:Hari M. Rao；Jung Pill Kim；Siamack Haghighi
申请人:Qualcomm Incorporated；
IPC主号:

专利说明:

Field of the Invention
[001] The present description is generally related to a memory cell that includes multiple non-volatile Description memories. Prior Art
[002] Advances in technology have resulted in smaller and more powerful computing devices. For example, there are currently a number of portable personal computing devices, which include wireless computing devices, such as cordless phones, personal digital assistants (PDAs) and paging devices that are small, light and easily ported by users. More specifically, cordless phones, such as cell phones and Internet Protocol (IP) phones, can communicate voice and data packets over wireless networks. In addition, many cordless phones include other types of devices that are incorporated into them. For example, a cordless phone can also include a fixed digital camera, a digital video camera, a digital recorder and an audio file device. In addition, such cordless phones can process executable instructions, including software applications, such as a Web browser application that can be used to access the Internet. As such, these cordless phones can include significant computing capabilities.
[003] The computing capacities of a processor can be increased by using the Simultaneous Multi-Thread (SMT). SMT provides higher instructions per cycle (IPC) enabling the issuing of multiple instructions from multiple execution chains in a cycle. Register files associated with an SMT processor are used to store the architectural “states” associated with each chain and can also support multiple read and write ports for execution. In a central processing unit (CPU), for example, multiple agents can attempt to access a common location in a register file on the same clock cycle as the processor. With multiple ports, a first agent does not have to wait for a second agent to complete a read / write operation before the first agent is able to perform the read / write operation. Enabling both agents to access the common register through different ports increases the memory bandwidth for read and write operations.
[004] The multi-port addition to each memory cell of a RAM device increases the size of each memory cell. The increase in the size of the memory cell due to the addition of additional ports may depend on the type of the memory device. For example, adding an additional recording port to a single port static random access memory (SRAM) cell to form a two-port SRAM cell typically involves an additional circuitry. A larger memory cell tends to increase the delay and the use of energy, which is disadvantageous in many electronic devices. Summary of the Invention
[005] In a specific embodiment, an SMT cell (that is, a multi-port memory cell and multiple strings) with multiple non-volatile memories is introduced. A multi-chain, multi-port random access magnet (MRAM) device is described that is smaller in size than a corresponding standard SRAM. In addition, the non-volatile MRAM device includes a non-volatile memory that allows the use of an instant architecture.
[006] In a specific embodiment, a memory device is described that includes a plurality of memory cells, wherein at least one of the memory cells comprises a first non-volatile memory element that includes a first resistive memory element and a second non-volatile memory element that includes a second resistive memory element.
[007] In a specific embodiment, a system is described that includes a processor and a series of memory cells accessible to the processor, in which at least one of the memory cells comprises a first multi-port non-volatile memory element that includes a first resistive memory element and a second non-volatile multi-port memory element that includes a second resistive memory element.
[008] In a specific embodiment, a method is described that includes receiving first data and receiving second data in a single memory cell comprising a first non-volatile memory element and a second non-volatile memory element. The method also includes storing the first data in a first resistive memory element of the first non-volatile memory and storing the second data in a second resistive memory element of the second non-volatile memory element.
[009] Other aspects, advantages and characteristics of the present description will become evident upon examination of the entire application, which includes the following sections: Brief Description of the Drawings, Detailed Description of the Invention and Claims. Brief Description of Drawings
[0010] Figure 1 is a block diagram of an illustrative modality specific to a system with a cell that includes multiple non-volatile memories;
[0011] Figure 2 is a diagram of a second illustrative embodiment of a system with a cell that includes multiple resistive elements;
[0012] Figure 3 is a diagram of a third modality illustrating a system with a cell that includes multiple resistive elements;
[0013] Figure 4 is a block diagram of a fourth illustrative embodiment of a system with a cell that includes multiple non-volatile memories;
[0014] Figure 5 is a flowchart of an illustrative modality specific to a method for driving a cell that includes multiple non-volatile memories;
[0015] Figure 6 is a block diagram of a specific modality of a wireless communication device that includes a cell with multiple multi-port non-volatile memories; and
[0016] Figure 7 is a data flow diagram illustrating a manufacturing process for use with a device that includes a cell that includes multiple multi-port non-volatile memories. Detailed Description of the Invention
[0017] Figure 1 is a diagram of a first embodiment of a system with a cell that includes multiple non-volatile memories and is generally designated as 100. System 100 includes a memory device 101, which includes a port data selector. 130 coupled to a plurality of memory cells 104, which includes a memory cell 106. The memory cell 106 includes a first non-volatile memory element 108, which includes a first resistive memory element 110, a second non-memory element volatile 112, which includes a second resistive memory element 114, with a nth (N) non-volatile memory 116, which includes a nth (N) resistive memory element 118.
[0018] In a specific embodiment, memory cell 106 is responsive to a write operation and is responsive to the first data 139 and the second data 140 received from port data selector 130. As part of the write operation, the cell memory 106 can be configured to store the first data 139 in the first non-volatile memory 108 and the second data 140 in the second non-volatile memory element 112. For example, the first non-volatile memory 108 can store the first data 139 by establishing a first resistance value of the first resistive memory element 110 so that it corresponds to a value of logical "0" or logical "1", and the second non-volatile memory element 112 can store the second data 140 establishing a second resistance value of the second resistive memory element 114.
[0019] In a specific embodiment, memory cell 106 is responsive to a read operation in order to generate output data 122. Output data 122 can correspond to a resistive element 110, 114, 118 specific to the memory cell 106. For example, output data 122 can be based on the first resistance value of the first resistive memory element 110. As another example, output data 122 can be based on the second resistance value of the second resistive memory element 114 .
[0020] In a specific embodiment, the port data selector 130 is responsive to the first instruction stream 124 in order to generate the first data 139. The port data selector 130 can be configured to provide the first data 139 to the cell memory 106. The port data selector 130 is also responsive to the second instruction stream 126 in order to generate the second data 140, and the port data selector 130 can be configured to provide the second data 140 to the memory cell. 106.
[0021] In a specific embodiment, memory device 101 is configured to implement SMT. For example, each non-volatile memory 108, 112, 116 can be configured to correspond to a specific instruction flow. For example, the first non-volatile memory 108 can be configured to be associated with the first instruction stream 124, and the second non-volatile memory element 112 can be configured to be associated with the second instruction stream 126. Each instruction stream 124, 126 can correspond to one or more strings of a plurality of strings being processed by a processor (not shown). For example, the first instruction stream 124 may consist of instructions associated with a first string that is processed by the processor, and the second instruction stream 126 may consist of instructions associated with a second string that is processed by the processor.
[0022] In a specific modality, the memory device 101 is a magneto-resistive random access memory (MRAM) that is configured to record data using spin torque transfer (STT). The memory device 101 can be a single register file, and the first non-volatile memory 108 and the second non-volatile memory element 112 can each correspond to a common register. For example, the first non-volatile memory 108 can be configured to store the first state information that corresponds to the first instruction stream 124, and the second non-volatile memory element 112 can be configured to store the second state information that corresponds to the second instruction flow 126.
[0023] During operation, memory cell 106 is responsive to read and write operations. For example, memory cell 106 can receive the first data 139 from port data selector 130 to be stored in the first non-volatile memory 108. In response to receiving the first data 139, the first non-volatile memory 108 can store the first data 139 fixing the first resistance value of the first resistive memory element 110. During a read operation of the first non-volatile memory 108, the memory cell 106 can generate the output data 122 based on the first resistance value of the first element resistive memory 110. In a specific embodiment, the first data 139 corresponds to the first instruction stream 124 and the output data 122 which are generated based on the first resistive memory element 110.
[0024] In a specific embodiment, memory cell 106 receives second data 140 from port data selector 130 to be stored in the second non-volatile memory element 112. In response to receiving second data 140, the second data element non-volatile memory 112 can store the second data 140 as the second resistance value of the second resistive memory element 114. During the read operation of the second non-volatile memory element 112, the memory cell 106 can generate the output data 122 based on the second resistance value of the second resistive memory element 114. In a specific embodiment, the second data 140 corresponds to the second instruction stream 126. For example, the output data 122 generated based on the second resistive memory element 114 may correspond to the second instruction stream 126.
[0025] In a specific embodiment, memory device 101 is used as RAM for a processor. Storing state information (e.g., first data 139 and second data 140) in non-volatile memories 108, 112, 116 of memory device 101 allows the processor to implement an instantaneous architecture. With an instant architecture, the processor has immediate access to status information in RAM without having to load status information into RAM. Non-volatile memories allow the memory device 101 to be turned off without losing the stored status information. The connection of the memory device 101 with an instantaneous architecture allows the processor to access the stored state information without having to load the state information from an external device that functions as non-volatile memory, thus reducing the starting time of a system that uses processor and memory device 101.
[0026] With reference to Figure 2, a diagram of a second modality of a system with a cell that includes multiple resistive elements is illustrated and generically designated by 200, each resistive element accessible through multiple doors. System 200 includes a memory cell 206 coupled to a decoder 202 and includes a port data selector 230. In a specific embodiment, memory cell 206 is memory cell 106 of Figure 1 and the port data selector 230 is the port data selector 130 of Figure 1.
[0027] In a specific embodiment, decoder 202 is configured to provide control signals by means of lines of text to allow reading and writing of data from memory cell 206. Decoder 202 can be configured to receive an email address. input directed to a specific port of memory cell 206. For example, the input address can be a signal of wp_address 240, which is directed to a zero port 213 of memory cell 206. As another example, the input address can be a signal from wp_address 241, which is directed to a first port 211 of memory cell 206. The decoder 202 can be configured to receive a signal (for example, the signal of the string w / 250) that indicates a specific chain that corresponds to to the input address. For example, the signal of string_r / w 250 may indicate that a string zero corresponds to the signal ofwp_address 241. As another example, the signal of string_r / w 250 can indicate that a first string corresponds to signal ofwaddress0 240.
[0028] In a specific embodiment, decoder 202 includes a set of circuits configured to process the input address based on the port and the string that corresponds to the input address. For example, the signal of chain_r / w 250 that corresponds to a specific chain and the signal of address_p0 240 that corresponds to port zero 213 can be received by a decoder 202. The signal of address_wp0 240 can be received on a flop of address P0 252 coupled to a pre-decoder P0 258, and the signal chain_r / w 250 can be received on a control flop 254. The output of control flop 254 can be coupled to a decoder P1_T1 266 and a decoder P0_T1 268. The reverse of the output of the control flop 254 can be coupled to a decoder P1_T0 262 and to a decoder P0_T0 264. The output of the control flop 254 can be inverted by an inverter 265 that transmits a voltage that represents the logic level opposite to its input. For example, inverter output 265 may be a logical “1” in response to receiving a logic “0” input from control flop output 254.
[0029] In a specific modality, the pre-decoder P0 258 is an AND gate that is configured to transmit a high signal in response to the receipt of two high signals as input of the address flop P0 252. The output of pre-decoder 258 can be transmitted to the decoder P0_T0 264 and to the decoder P0_T1 268. The decoder P0_T0 264 can be configured to transmit a signal on a text line (for example, WWL_P0_T0 244) in response to receiving a high signal from the inverter output 265 and the P0 258 pre-decoder output. The P0_T1 decoder 268 can be configured to transmit a signal on a text line (for example, WWL_P0_T1 248) in response to receiving a high signal from the control flop 254 and of the P0 258 pre-decoder output.
[0030] As another example, the decoder 202 can receive the signal of string_r / w 250 that corresponds to a specific chain and a signal ofwp_address 241 which corresponds to the first port 211. The signal ofwad_address1 241 can be received on a flop of address P1 256 coupled to a pre-decoder P1 260, and the string signal w / w 250 can be received on control flop 254. In a specific embodiment, the pre-decoder P1 260 is an AND gate that is configured to transmit a high signal in response to receiving two high signals as input from the address flop P1 256. The output of the pre-decoder P1 260 can be transmitted to the decoder P1_T0 262 and to the decoder P1_T1 266. The decoder P1_T1 262 can be configured to transmit a signal on a text line (for example, WWL_P1_T0 242) in response to receiving a high signal from the output of inverter 265 and the output of pre-decoder P1 260. The decoder P1_T1 266 can be configured to transmit a signal on a text line (for example, WWL_P1_T1 246) in response to receiving a high signal from the output of the control flop 254 and the output of the pre-decoder P1 260.
[0031] In a specific embodiment, the port data selector 230 is configured to receive a read / write control signal 236. The control signal w / r 236 can indicate whether memory cell 206 will perform an operation read or write operation on a specific port. For example, the control signal w / r 236 may indicate that the read operation will be performed on a first port 211 of memory cell 206. As another example, the control signal w / r 236 may indicate that the write operation will be performed on port zero 213 of memory cell 206. The port data selector 230 can be configured to receive input data to write data to the ports of memory cell 206 during the write operation. In a specific mode, the input data also indicates a value to be stored. For example, the input data may consist of a Dataw_P1 signal 238, which indicates that the first port 211 will be used to write a data value that represents a logical value of one. As another example, the input data can consist of a Dataw_P0 signal 239, which indicates that port zero 213 will be used to write a data value that represents a logical value of zero.
[0032] In a specific embodiment, the port data selector 230 includes a circuitry configured to process the read / write control signal 236 and, during the write operation, to process the input data (for example, the Dataw_P1 238 signal and the Dataw_P0 239 signal). The port data selector circuitry 230 may include a bit line multiplexer (BL) 290, a sense line multiplexer (SL) 291, a BL293 recording voltage multiplexer and an SL294 recording voltage multiplexer . While Figure 2 shows the circuitry for processing the first port 211 of memory cell 206 for easy explanation, port data selector 230 may also include a BL multiplexer, an SL multiplexer, a BL write voltage multiplexer and a corresponding SL write voltage multiplexer for each memory cell port 206.
[0033] Both the BL 290 multiplexer and the SL 291 multiplexer can be configured to receive the read / write control signal 236. The read / write control signal 236 can determine whether the BL 290 multiplexer and the SL 291 multiplexer will be used in the read operation or the write operation. The output of the BL 290 multiplexer is connected to a bit line (for example, BL_P1 270) which corresponds to the first port 211, and the output of the SL 291 multiplexer is connected to a sense line (for example, SL_P1 276) which corresponds to to the first port 211.
[0034] In response to receiving the read / write control signal 236, which indicates a read operation, the multiplexer BL 290 can be configured to transmit a voltage of 0.2 V on the BL_P1 270, and the multiplexer SL 291 can be configured to transmit a voltage of 0 V on the SL_P1 276. In response to the read / write control signal 236, which indicates a write operation, the BL 290 multiplexer can be configured to transmit a voltage to the BL_P1 270 based on the recording voltage multiplexer BL 293. In a specific embodiment, the output of recording voltage multiplexer BL 293 is based on the input data of port data selector 230. For example, the Data signal w_P1 238 may indicate that a value 1.2 V data will be stored in memory cell 206 via the first port 211. The BL293 recording voltage multiplexer can be configured to transmit 1.2 V to the BL 290 multiplexer, and the recording voltage multiplexer The SL 294 can be configured to transmit 0 V to the SL 291. multiplexer. In a specific mode, an output of 1.2 V on the BL_P1 270 and 0 V on the SL_P1 270 results in the storage of a 1.2 V representation in one of the resistive elements of memory cell 206. Although specific numerical values are described in the present description as illustrative examples, it should be understood that the present description is not limited to the specific values described and that other values can be used instead.
[0035] Alternatively, the Dataw_P1 signal 238 may indicate that a data value of 0 V will be stored in memory cell 206 via the first port 211. The recording voltage multiplexer BL 293 can be configured to transmit 0 V to the BL 290 multiplexer, and the SL 294 recording voltage multiplexer can be configured to transmit 1.2 V to the SL 291 multiplexer. In a specific mode, an output of 0 V on the BL_P1 270 and 1.2 V on the SL_P1 276 results in the storage of a 0 V representation in one of the resistive elements of the memory cell 206.
[0036] In a specific embodiment, memory cell 206 is an SMT cell that is configured to store data in resistive elements. For example, memory cell 206 may include a first resistive element 210 configured to store a first data representation and a second resistive element 214 configured to store a second data representation. The memory cell 206 can be configured to allow the first data representation to be read from the first resistive element 210 and the second data representation to be read from the second resistive element 214.
[0037] In a specific embodiment, memory cell 206 includes a set of circuits for storing and reading data stored in resistive elements (for example, the first resistive element 210 and the second resistive element 214). Memory cell 206 may include access transistors that control access to resistive elements. Access transistors can be bipolar transistors or field effect transistors and can be configured as type n or type p. For example, the first resistive element 210 can be accessed through the first port 211 or through the zero port 213. The access of the first resistive element 210 through the first port 211 is controlled by an access transistor BL_P1_T0 280 and an access transistor SL_P1_T0 282 The access of the first resistive element 210 through the zero port 213 is controlled by an access transistor BL_P0_T0 281 and an access transistor SL_P1_T0 283. The access of the second resistive element 214 through the first port 211 is controlled by an access transistor BL_P1_T1 284 and an access transistor SL_P1_T1 286. The access of the second resistive element 214 through port zero 213 is controlled by an access transistor BL_P0_T1 285 and an access transistor SL_P1_T1 287.
[0038] Memory cell access transistors 206 are connected to the text lines of decoder 202 (for example, WWL_P1_T0 242, WWL_P0_T0 244, WWL_P1_T1 246 and WWL_P0_T1 248), to bit lines (for example, the BL_P1 270 and a BL_P0 272) and the direction lines (for example, an SL_P0 274 and SL_P1 276). For example, the access transistor BL_P1_T0 280 can receive a signal from WWL_P1_T0 242 and BL_P1 270. In a specific embodiment, the access transistor BL_P1_T0 280 can be a type n JFET that includes a source, a port and a drain. The access transistor BL_P1_T0 280 can receive the signal from WWL_P1_T0 242 at the port and the signal from BL_P1 270 at the source. The drain of the BL_P1_T0 280 access terminal can be connected to the first resistive element 210.
[0039] In a specific modality, the source of the access transistor SL_P1_T0 282 is connected to the first resistive element 210, the port to WWL_P1_T0 242 and the drain to SL_P1 276. The source of the access transistor BL_P0_T0 281 is connected to the bit line BL_P0 272, the door to WWL_P0_T0 244 and the drain to the first resistive element 210. The source of the access transistor SL_P1_T0 283 is connected to the first resistive element 210, the door to WWL_P0_T0 244 and the drain to SL_P0 274.
[0040] In a specific modality, the source of the access transistor BL_P1_T1 284 is connected to BL_P1 270, the port to WWL_P1_T1 246 and the drain to the second resistive element 214. The source of the access transistor SL_P1_T1 286 is connected to the second resistive element 214, the port at WWL_P1_T1 246 and the drain at SL_P1 276. The source of the BL_P0_T1 285 access transistor is connected to bit line BL_P0 272, the port at WWL_P0_T1 248 and the drain to the second resistive element 214. The source of the transistor from 214. access SL_P1_T1 287 is connected to the second resistive element 214, the door to WWL_P0_T1 248 and the drain to SL_P0 274.
[0041] In a specific embodiment, the access transistors control access to the resistive elements of memory cell 206. For example, access to the first resistive element 210 through the first port 211 is enabled by connecting both the access transistor BL_P1_T0 280 and the access transistor SL_P1_T0 282. The access transistor BL_P1_T0 280 is configured to be connected by receiving a signal from the decoder 202 via WWL_P1_T0 242. The access transistor SL_P1_T0 282 is configured to be connected by receiving a signal via WWL_P1_T0 242. Connecting the access transistor BL_P1_T0 280 and the access transistor SL_P1_T0 282 can allow current to flow through the first resistive element 210 through the first port 211 of memory cell 206.
[0042] As another example, access to the first resistive element 210 through port zero 213 is enabled by connecting the access transistor BL_P0_T0 281 and the access transistor SL_P0_T0 283. The access transistor BL_P0_T0 281 is configured to be connected by receiving a signal from decoder 202 via WWL_P0_T0 244. The access transistor SL_P0_T0 283 is configured to be connected by receiving a signal via WWL_P0_T0 244. The connection of access transistor BL_P0_T0 281 and the access transistor SL_P0_T0 283 it can allow current to flow through the first resistive element 210 through the zero port 213 of memory cell 206.
[0043] In a specific modality, access to the second resistive element 214 through the first port 211 is enabled by connecting the access transistor BL_P1_T1 284 and the access transistor SL_P1_T1 286. The access transistor BL_P1_T1 284 is configured to be connected by receiving a signal from decoder 202 via WWL_P1_T1 246. The access transistor SL_P1_T1 286 is configured to be connected by receiving a signal via WWL_P1_T1 246. The connection of the access transistor BL_P1_T1 284 and the access transistor SL_P1_T1 286 may allow current to flow through the second resistive element 214 through the first port 211 of memory cell 206.
[0044] As another example, access to the second resistive element 214 through port zero 213 is enabled by connecting the access transistor BL_P0_T1 285 and the access transistor SL_P0_T1 287. The access transistor BL_P0_T1 285 is configured to be connected by receiving a signal from decoder 202 via WWL_P0_T1 248. The access transistor SL_P0_T1 287 is configured to be connected by receiving a signal via WWL_P0_T1 248. The connection of access transistor BL_P0_T1 285 and the access transistor SL_P0_T1 287 it can allow current to flow through the second resistive element 214 through port zero 213 of memory cell 206.
[0045] During the recording operation, decoder 202 can generate an output signal in response to receipt of the input address and the string signal w / 250 250. The output signal can be directed to a specific line of text based on on a specific port indicated by the input address and on a chain indicated by the signal of string_r / w 250. For example, decoder 202 can receive signal from web_p1 address 241 on address flop P1 256, and control flop 254 can receive the chain_r / w signal 250, which indicates the zero chain. A low signal such as the chain / w signal 250 may indicate the zero chain and a high signal may indicate the first chain.
[0046] In a specific mode, the output of the address flop P1 256 generates an output in the pre-decoder P1 260, which is provided to the decoder P1_T0 262 and to the decoder P1_T1 266. For example, the output of the address flop P1 256 it can be a high signal and the inverter output 265 can be zero. The decoder P1_T1 266 can receive a low signal from the output of the inverter 265 and a high signal from the output of the pre-decoder P1 260. The decoder P1_T1 266, which functions as an AND gate, does not receive two high signals and therefore does not generate a high signal at WWL_P1_T1 246. In response to receiving a high signal from the inverter output 265 and a high signal from the pre-decoder output P1 260, the P1_T0 decoder 262 can generate a high signal at WWL_P1_T0 242. A high signal on WWL_P1_T0 242 it can be received by the access transistor BL_P1_T0 280 and the access transistor SL_P1_T0 282.
[0047] In a specific mode, the read / write control signal 236 received by the port data selector 230 indicates that the write operation will be performed by the memory cell 206. The port data selector 230 can receive the data input to be recorded during the recording operation. In response to the read / write control signal 236 of the write operation, the BL 290 multiplexer can be configured to transmit a voltage to the BL 232 bit line based on the BL 293 write voltage multiplexer. a specific modality, the output of the recording voltage multiplexer BL 293 is based on the input data of the port data selector 230. For example, the Data signal w_P1 238 may indicate that a data value of 1.2 V will be stored in memory cell 206 via the first port 211. The BL 293 recording voltage multiplexer can transmit 1.2 V to the BL 290 multiplexer and the SL 294 recording voltage multiplexer can transmit 0 V to the SL 291 multiplexer.
[0048] In a specific modality, an output of 1.2 V in the BL_P1 270 and 0 V in the SL_P1 276 results in the storage of a representation of 1.2 V in one of the resistive elements of the memory cell 206. Alternatively, the Data signalw_P1 238 can indicate that a representation of 0 V will be stored in memory cell 206 through the first port 211. The recording voltage multiplexer BL 293 can be configured to transmit 0 V to the BL 290 multiplexer and the recording voltage SL 294 can be configured to transmit 1.2 V to the SL 291. multiplexer. A 0 V output on the BL_P1 270 and a 1.2 V output on the SL_P1 276 can result in the storage of a 0 V representation in one of the resistive elements of memory cell 206.
[0049] In a specific embodiment, the resistance values of the resistive elements indicate a representation of the data to be stored by the memory cell 206. For example, the first resistive element 210 may be a magnetic tunneling junction (MTJ) that includes layers aligned in a specific magnetic orientation. As the current passes through the layers, the orientation of the layers increases or decreases the resistance of MTJ.
[0050] In a specific modality, BL_P1 270 has a first voltage and SL_P1 276 can have a second voltage during the recording operation on the first port 211. If the first voltage is higher than the second voltage it can be based on the value resistor to be written to the first resistive element 210. For example, the port data selector 230 can provide BL_P1 270 with a voltage of 1.2 V and SL_P1 276 with a voltage of 0 V. Current would flow from the bit line BL_P1 270 through the first resistive element 210 to SL_P1 276, aligning the magnetic moments of the MTJ layers in a specific direction. Alternatively, if the BL_P1 270 voltage is 0 V and the SL_P1 276 voltage is 1.2 V, then the current can flow from the SL_P1 276 through the first resistive element 210 to the BL_P0 272 bit line, aligning the magnetic moments of the layers of the first resistive element 210 in the opposite direction. If the magnetic moments of the MTJ layers are in a parallel orientation, then the resistance value of the MTJ is less than if the magnetic moments were in an anti-parallel orientation. A small resistance value of the MTJ (for example, the first resistive element 210) can correspond to a first data representation, and a large resistance value can correspond to a second data representation.
[0051] During the read operation, the decoder 202 can generate an output signal in response to receipt of the input address and the string signal w / 250 250. The output signal can be directed to a specific line of text based on on a specific port indicated by the input address and on a specific chain indicated by the signal of string_r / w 250. For example, decoder 202 can receive signal from web_p1 address 241 on address flop P1 256 and control flop 254 can receive the chain_r / w signal 250 which indicates the zero chain. In a specific embodiment, a low signal such as the chain_r / w signal 250 indicates the zero chain and a high signal can indicate the first chain. The output of the address flop P1 256 can generate an output in the pre-decoder P1 260, which is provided to the decoder P1_T0 262 and to the decoder P1_T1 266. For example, the output of the address flop P1 256 can be a high signal and the inverter output 265 can be zero.
[0052] In a specific mode, the decoder P1_T1 266 receives a low signal from the output of the inverter 265 and a high signal from the output of the pre-decoder P1 260. The decoder P1_T1 266, which functions as an AND gate, does not receive two signals high and therefore does not generate a high signal at WWL_P1_T1 246. In response to receiving a high signal from the output of the inverter 265 and a high signal from the output of the pre-decoder P1 260, the decoder P1_T0 262 can generate a high signal at WWL_P1_T0 242. A high signal at WWL_P1_T0 242 can be received by the access transistor BL_P1_T0 280 and the access transistor SL_P1_T0 282.
[0053] In a specific mode, the read / write control signal 236 received by the data selector port 230 indicates that the read operation will be performed by the memory cell 206. In response to the indication, by the read control signal / write 236, of the read operation, the BL 290 multiplexer can be configured to transmit a voltage of 0.2 V on the BL_P1 270, and the SL 291 multiplexer can be configured to transmit a voltage of 0 V on the SL_P1 276. In a specific modality, BL_P1 270 provides the access transistor BL_P1_T0 280 0.2 V and the access transistor SL_P1_T0 282 0 V. Current can flow from BL_P1 270 through the first resistive element 210 to SL_P1 276.
[0054] In a specific embodiment, a set of sensor circuits connected to the SL_P1 276 compares the current in the SL_P1 276 with a reference current in order to determine the resistance value of the first resistive element 210. For example, a high current can indicate a small resistance value, and a low current can indicate a large resistance value. The resistance value of the first resistive element 210 can serve as an indication of the logical value of the stored element of the first resistive element. If the magnetic moments of the MTJ layers (for example, the first resistive element 210) were in a parallel orientation, then the detected resistance would be less than if the magnetic elements are in an antiparallel orientation. For example, a large resistance value can represent a logical value of zero and a small resistance value can represent a logical value of one.
[0055] In a specific embodiment, memory cell 206 is used as a RAM cell for a processor. Storing state information (e.g., Dataw_P1 signal 238 and Dataw_P0 signal 239) as a resistance value in resistive memory element 210, 214 of memory cell 206 allows a processor to implement an instantaneous architecture. With an instant architecture, the processor has immediate access to status information in RAM without having to load status information into RAM. The resistive element of the memory allows the memory cell 206 to be turned off without losing the resistive value that represents the status information. Powering the memory cell 206 allows the processor to access the stored status information without having to load the status information into the RAM of an external device that functions as a non-volatile memory, thus reducing the system startup time using memory cell 206.
[0056] With reference to Figure 3, a diagram of a third embodiment of a system with a cell that includes multiple non-volatile memories is illustrated and generally designated by 300. System 300 includes a memory cell 306 coupled to a decoder 302 and a selector 330. The memory cell 306 has a single port, in contrast to the multi-port memory cell 206 of Figure 2.
[0057] In a specific embodiment, decoder 302 is configured to provide control signals by means of text lines to allow reading and writing of data from memory cell 306. Decoder 302 can be configured to receive a signal ( for example, a string signal (w / 350) indicating a specific string that corresponds to an input address. For example, the sign of string_r / w 350 may indicate that a string zero corresponds to a first sign of address 240. As another example, the sign of string_r / w 350 can indicate that a first string corresponds to a second sign of address 241 Decoder 302 can be configured to generate a first control signal via a first text line 344 and a second control signal via a second text line 348.
[0058] In a specific mode, selector 330 is configured to receive a read / write control signal 236. The control signal w / r 236 can indicate whether memory cell 306 will perform a read operation or an operation recording. Selector 330 can be configured to receive input data 338 to write data to one or more of resistive elements 310, 314 of memory cell 306. In a specific embodiment, input data 338 also indicates a value to be stored. For example, input data 338 may indicate that a data value, representing a logical value of one, will be written to the first resistive element 310. As another example, input data 338 may indicate that a data value, representing a logical value of zero will be written to the second resistive element 314.
[0059] In a specific embodiment, memory cell 306 is configured to store data on resistive elements 310, 314. For example, the first resistive element 310 can be configured to store a first representation of data, and the second resistive element 314 can be configured to store a second data representation. The memory cell 306 can be configured to allow the first data representation to be read from the first resistive element 310 and the second data representation to be read from the second resistive element 314.
[0060] In a specific embodiment, memory cell 306 includes a set of circuits for storing and reading data stored in resistive elements 310, 314. Memory cell 306 can include access transistors that control access to resistive elements. Access transistors can be bipolar transistors or field effect transistors and can be configured as either type n or type p. Access to the first resistive element 310 is controlled by a first access transistor 383. Access to the second resistive element 314 is controlled by a second access transistor 387.
[0061] Memory cell access transistors 306 are connected to the decoder 302 text lines (for example, the first text line 344 and the second text line 348), resistive elements 310, 314 and the (SL) 374. For example, the first access transistor 383 can receive a signal from the first text line 344 to allow access to the first resistive element 310. As another example, the second access transistor 387 can receive a signal from the second line of text 348 to allow access to the second resistive element 314. In a specific embodiment, the powered transistors 383, 387 can be type FETs that each include a source, a port and a drain. For example, the first access transistor 383 can receive the signal from the first text line 344 at the gate and a signal from the first resistive element 310 at the source. The drain of the first access transistor 383 can be connected to SL 374. As another example, the port of the second access transistor 387 can be connected to the second text line 348, the source to the second resistive element 314 and the drain to the direction 374.
[0062] In a specific embodiment, the on-load transistors 383, 387 control access to resistive elements 310, 314 of memory cell 306. For example, access to the first resistive element 310 is enabled by turning on the first access transistor 383. The first access transistor 383 is configured to be connected by receiving a signal from decoder 302 via the first text line 344. Connecting the first access transistor 383 can allow current to flow through the first resistive element 310 memory cell 306. As another example, access to the second resistive element 314 is enabled by turning on the second access transistor 387. The second access transistor 387 is configured to be turned on by receiving a signal from decoder 302 via of the second text line 348. The connection of the second access transistor 387 can allow current to flow through the second resistive element 314 of the memory cell 306 .
[0063] During the recording operation, the decoder 302 can generate an output signal in response to the receipt of the input address and the string signal w / 350 350. The output signal can be directed to a specific line of text indicated by input address and for a specific string indicated by the string signal w / 350 350.
[0064] In a specific embodiment, the resistance values of the resistive elements indicate a representation of the data to be stored by the memory cell 306. For example, the first resistive element 310 can be a magnetic tunneling junction (MTJ) that includes layers aligned in a specific magnetic orientation. As the current passes through the layers, the orientation of the layers increases or decreases the resistance of MTJ. If the magnetic moments of the MTJ layers are in a parallel orientation, then the resistance value of the MTJ is less than if the magnetic moments were in an anti-parallel orientation. A small resistance value of the MTJ (for example, the first resistive element 310) can correspond to a first data representation, and a higher resistance value can correspond to a second data representation.
[0065] During the read operation, the decoder 302 can generate an output signal in response to the receipt of the input address and the string signal w / 350 350. The output signal can be directed to a specific line of text based on at the input address and in a specific string indicated by the string signal w / 350 350. The read / write control signal 236 received by selector 330 may indicate that the read operation will be performed by memory cell 306.
[0066] In a specific embodiment, a set of sensor circuits (not shown) connected to the sense line 374 compares the current in the sense line 374 with a reference current in order to determine the resistance value of the first resistive element 310 For example, a high current may indicate a small resistance value, and a low current may indicate a large resistance value. For example, The resistance value of the first resistive element 310 can serve as an indication of the logical value of the element stored in the first resistive element 310. If the magnetic moments of the MTJ layers (for example, the first resistive element 310) are in a parallel orientation, then the detected resistance would be less than if the magnetic moments were in an antiparallel orientation. For example, a large resistance value can represent a logical value of zero and a small resistance value can represent a logical value of one.
[0067] In a specific embodiment, memory cell 306 is used as a RAM cell for a processor. Storing state information (e.g., input data 338) as resistance values in resistive elements 310, 314 of memory cell 306 allows a processor to implement an instantaneous architecture. With an instant architecture, the processor has immediate access to status information in RAM without having to load status information into RAM. The resistive element allows the memory cell 306 to be turned off without losing the resistive value that represents the status information. Connecting memory cell 306 allows the processor to access stored status information without having to load status information into the RAM of an external device that functions as a non-volatile memory, thus reducing the time to start a system that uses memory cell 306.
[0068] With reference to Figure 4, a diagram of a modality of a system with an SMT cell that includes multiple non-volatile multi-port memories is shown and generically designated by 400. System 400 includes a processor core 404, an instruction decoder 408, a programmer 410, an instruction cache 409 and a register file 406 that includes at least one cell with multiple non-volatile multi-port memories 412. The processor 404 is coupled to register file 406 and programmer 410. Programmer 410 is attached to instruction decoder 408, which is attached to instruction cache 409.
[0069] In a specific embodiment, instruction decoder 408 receives instructions 422 from instruction cache 409. Instruction decoder 408 can decode instructions 422 and generate string instructions 413 and one or more control signals 420 to be sent to the 410 programmer.
[0070] Programmer 410 can receive chain instructions 413 and control signals 420. Programmer 410 can be configured to program execution chains 414 to run on processor core 404. In a specific embodiment, programmer 410 is configured to program at least two instruction chains (for example, the programmed execution chains 414) to be processed substantially concurrently.
[0071] In a specific embodiment, processor core 404 is configured to retrieve operands 430 from register file 406 in response to receipt of programmed execution chains 414 and one or more control signals 421 from programmer 410. For example, operands 430 can include data from a register that includes the cell with multiple non-volatile multi-port memories 412. The processor core 404 can generate data based on the execution of execution chains 414 programmed with operands 430. The processor core 404 can record back 431 the data generated in register file 406.
[0072] In a specific embodiment, the cell with multiple multi-port non-volatile memories 412 may be memory cell 106 in Figure 1 or memory cell 206 in Figure 2. For example, the first non-volatile memory 108 may correspond to a first programmed thread 414 and the second non-volatile memory element 112 may correspond to a second programmed thread 414. In a specific embodiment, the multi-port non-volatile multi-memory cell 412 stores a bit from a register for each sequence. For example, a bit of an operand can be stored in the multi-port non-volatile multi-memory cell 412. During a read operation, register file 406 can transmit operands (for example, operands 430) that match strings. execution 414 scheduled. During rewrite 431, register file 406 can store data received from processor core 404.
[0073] In a specific embodiment, register file 406 is used as RAM for the processor core 404. The storage of state information (for example, data received during rewriting 431) in the cell with multiple multi-volatile non-volatile memories port 412 of register file 406 allows an instant architecture to be implemented in register file 406. Non-volatile memories allow register file 406 to be turned off without losing stored state information. Linking register file 406 allows processor core 404 to access stored state information without having to load state information into register file 406 of an external device that functions as non-volatile memory, thereby reducing time system 400 starting using processor core 404 and register file 406.
[0074] Figure 5 is a flow diagram of a first modality of a method 500 for driving a cell that includes multiple non-volatile multi-port memories. In a specific embodiment, method 500 is performed by any of the systems in Figures 1-4 or any combination of them. Method 500 includes receiving first data and receiving second data in a single memory cell that includes a first non-volatile memory element and a second non-volatile memory element, at 502. For example, memory cell 106 in Figure 1 can receiving the first data 139 in the single memory cell 106 which includes the first non-volatile memory 108 and the second non-volatile memory element 112. In a specific embodiment, the first non-volatile memory is a first multi-port non-volatile memory element and the second non-volatile memory element is a second multi-port non-volatile memory element. Method 500 also includes storing the first data in a first resistive memory element of the first non-volatile memory, at 504. For example, the memory cell 106 of Figure 1 can store the first data 139 in the first resistive memory element 110 of the first non-volatile memory 108. Method 500 also includes storing the second data in a second resistive memory element of the second non-volatile memory element, at 506. For example, memory cell 106 in Figure 1 can store the second data 140 in the second resistive memory element 114 of the second non-volatile memory element 112.
[0075] In a specific modality, method 500 optionally includes generating a first output signal that corresponds to a data value in the first non-volatile memory, where the first output signal responds to a read / write control signal, in 508. For example, memory cell 106 of Figure 1 can generate the first output signal (i.e., output data 122) which corresponds to a data value stored in the first non-volatile memory 108, where the first The output (i.e., the output data 122) is responsive to the read / write control signal (the read / write control signal 236 of Figure 2).
[0076] The method of Figure 5 can be performed on a processor integrated in an electronic device. For example, as will be described with reference to Figure 6, the first data and the second data can be received and stored by a computer or other electronic device. Alternatively, or in addition, those skilled in the art will recognize that method 500 in Figure 5 can be implemented or initiated by a field programmable port arrangement (FPGA), an application specific integrated circuit (ASIC), a central processing unit (CPU), a digital signal processor (DSP), a controller, another hardware device, or any combination of them.
[0077] Figure 6 is a block diagram of a modality of a wireless communication device 600, which has a cell with multiple non-volatile multi-port memories 664. The wireless communication device 600 can be implemented as a device portable wireless electronic device that includes a 610 processor, such as a digital signal processor (DSP), coupled with a 632 memory.
[0078] Memory 632 may include a computer-readable medium that stores instructions (for example, software 634) that are executed by a processor, such as processor 610. For example, software 634 may include instructions that are executable by a computer to receive the first data and receive the second data in a single memory cell, such as the cell with multiple non-volatile multi-port memories 664, which includes a first element of non-volatile multi-port memory and a second element of multi-port non-volatile memory. The 634 software may also include instructions that are executable by the computer to store the first data in a first resistive memory element of the first multi-port non-volatile memory. The 634 software may also include instructions that are executable by the computer to store the second data in a second resistive memory element of the second non-volatile multi-port memory element.
[0079] In an illustrative example, the cell with multiple non-volatile multi-port memories 664 includes one or more of the modules or equipment of Figures 1-4, works according to Figure 5 or any combination of them. The cell with multiple non-volatile multiport memories 664 can be on processor 610 or it can be on a separate device.
[0080] In a specific embodiment, a display controller 626 is coupled to processor 610 and a display device 628. An encoder / decoder (CODEC) 634 can also be coupled to processor 610. A speaker 636 and a microphone 638 can be attached to CODEC 634. A wireless controller 640 can be attached to processor 610 and a wireless antenna 642. The cell with multiple non-volatile multi-port memories 664 is attached to wireless controller 640, CODEC 634 and controller display 626. In a specific embodiment, the cell with multiple non-volatile multi-port memories 664 is configured to store data related to the display controller 626, CODEC 634 and wireless controller 640.
[0081] In a specific modality, the signal processor 610, the display controller 626, the memory 632, the CODEC 634 and the wireless controller 640 are included in a packaged system device or embedded system 622. In one mode a specific input device 630 and a power supply 644 are coupled to the built-in system device 622. Furthermore, in a specific embodiment, as shown in Figure 6, the display device 628, the input device 630, the speaker 636, microphone 638, wireless antenna 642 and power supply 644 are external to the built-in system device 622. However, each of display devices 628, input device 630, speaker 636, microphone 638, wireless antenna 642 and power supply 644 can be coupled to a component of the built-in system device 622, such as an interface or a controller.
[0082] The devices and functionalities described above can be designed and configured in computer files (for example, RTL, GDSII, GERBER, etc.) stored in a computer-readable medium. Some or all such files may be provided to manufacturing operators who manufacture devices based on such files. The resulting products include semiconductor plates that are then cut into a semiconductor wafer and packaged on a semiconductor chip. The chips are then used in devices described above.
[0083] Figure 7 shows a specific illustrative modality of an electronic device manufacturing process 700. Physical information about device 702 is received in the manufacturing process 700, such as in a research computer 706. Physical information about device 702 can include design information that represents at least one physical property of a semiconductor device, such as system 100 in Figure 1, system 200 in Figure 2, system 300 in Figure 3, system 400 in Figure 4 or any combination of them . For example, physical information about device 702 can include physical parameters, material characteristics, and structure information that is entered through a user interface 704 coupled to the research computer 706. The research computer 706 includes a 708 processor, such as as one or more processing cores, coupled to a computer-readable medium, such as a 710 memory. The 710 memory can store computer-readable instructions that are executable to make the 708 processor transform physical information about device 702 to conform to a file format and generate a 712 library file.
[0084] In a specific embodiment, the library file 712 includes at least one data file that includes the transformed design information. For example, library file 712 may include a semiconductor device library that includes a device that includes memory cell 106 in Figure 1 (for example, equipment 100 in Figure 1), a device that includes the memory cell 206 of Figure 2 (for example, equipment 200 of Figure 2), a device that includes memory cell 306 of Figure 3 (for example, equipment 300 of Figure 3), a device that includes the cell with multiple memories multi-port volatiles 412 of Figure 4 (for example, equipment 400 of Figure 4) or any combination thereof, which is provided for use with an electronic design automation tool (EDA) 720.
[0085] The library file 712 can be used in conjunction with the EDA tool 720 on a computer designed 714, which includes a processor 716, such as one or more processing cores, coupled with a memory 718. The tool EDA 720 can be stored as processor executable instructions in memory 718 to allow the user of the designed computer 714 to design a circuit that includes a device that includes memory cell 106 in Figure 1 (for example, equipment 100 in Figure 1), a device which includes memory cell 206 of Figure 2 (for example, equipment 200 of Figure 2), a device that includes memory cell 306 of Figure 3 (for example, equipment 300 of Figure 3), a device that includes the cell with multiple non-volatile multi-port memories 412 of Figure 4 (for example, the equipment 400 of Figure 4) or any combination of them, from library file 712. For example, the user of the designed computer 714 can i n input circuit design information 722 via a user interface 724 coupled to the designed computer 714. Circuit design information 722 may include design information that represents at least one physical property of a semiconductor device, such as a device which includes memory cell 106 of Figure 1 (for example, equipment 100 of Figure 1), a device that includes memory cell 206 of Figure 2 (for example, equipment 200 of Figure 2), a device that includes memory cell 306 of Figure 3 (for example, equipment 300 of Figure 3), a device that includes the cell with multiple non-volatile multi-port memories 412 of Figure 4 (for example, equipment 400 of Figure 4) or any combination of them. For purposes of illustration, the circuit design property may include the identification of specific circuits and relationships to other elements in a circuit design, positioning information, characteristic size information, interconnection information, or other information that represents a property physics of a semiconductor device.
[0086] The designed computer 714 can be configured to transform the design information, which includes the circuit design information 722, to conform to a file format. For illustration purposes, file formation may include a binary database file format that represents planar geometric conformations, text labels and other information about a circuit layout in a hierarchical format, such as a System file format of Graphical Data (GDSII). The designed computer 714 can be configured to generate a data file that includes transformed design information, such as a GDSII file 726 that includes information that describes memory cell 106 in Figure 1, memory cell 206 in Figure 2, the cell with multiple non-volatile multi-port memories 312 of Figure 3, the cell with multiple non-volatile multi-port memories 412 of Figure 4 or any combination of them, in addition to other circuits or information. For purposes of illustration, the data file may include information that corresponds to an embedded system (SOC), which includes memory cell 106 of Figure 1 and which also includes additional electronic circuits and components within the SOC.
[0087] The GDSII file 726 can be received in a manufacturing process 728 to manufacture memory cell 106 in Figure 1, memory cell 206 in Figure 2, memory cell 306 in Figure 3, the cell with multiple memories non-volatile multi-port 412 of Figure 4 or any combination of them, according to the information transformed in the GDSII 726 file. For example, a device manufacturing process may include providing the GDSII 726 file to a mask manufacturer 730 to create a or more masks, such as masks to be used with photolithography processing, shown as a representative 732 mask. Mask 732 can be used during the manufacturing process to generate one or more 734 plates, which can be tested and separated into tablets, as a representative chip 736. The chip 736 includes a circuit that includes a device that includes memory cell 106 of Figure 1 (for example, equipment 100 of Figure 1), a device device that includes memory cell 206 of Figure 2 (for example, equipment 200 of Figure 2), a device that includes memory cell 306 of Figure 3 (for example, equipment 300 of Figure 3), a device that includes the cell with multiple non-volatile multi-port memories 412 of Figure 4 (for example, the equipment 400 of Figure 4) or any combination thereof.
[0088] The tablet 736 can be provided for a packaging process 738, where the tablet 736 is incorporated into a representative package 740. For example, the package 740 can include the single tablet 736 or multiple tablets, such as a packaged system (SiP) arrangement. The 740 package can be configured to conform to one or more standards or specifications, such as the standards of the Joint Electronic Devices Engineering Council (JEDEC).
[0089] Information regarding the 740 package can be distributed to multiple product designers, such as through a component library stored on a 746 computer. The 746 computer can include a 748 processor, such as one or more processing cores. , coupled to a 750 memory. A printed circuit board (PCB) tool can be stored as a processor executable instruction in memory 750 to process PCB 742 design information received from the computer 746 user via a 744 user interface. PCB design information 742 may include physical positioning information for a semiconductor device packaged on a circuit board, the packaged semiconductor device corresponding to package 740 that includes memory cell 106 in Figure 1, the memory cell 206 of Figure 2, memory cell 306 of Figure 3, the cell with multiple non-volatile multi-port memories 412 of Figure 4 or any combination of them.
[0090] Computer 746 can be configured to transform PCB 742 design information in order to generate a data file, such as a GERBER 752 file with data that includes physical position information for a semiconductor device housed in a plate circuit, as well as the layout of electrical connections such as tracks and tracks, in which the packaged semiconductor device corresponds to package 740 that includes memory cell 106 in Figure 1, memory cell 206 in Figure 2, the memory cell 306 of Figure 3, the multi-port non-volatile multi-memory cell 412 of Figure 4 or any combination thereof. In other embodiments, the data file generated by the transformed PCB design information can have a format other than a GERBER format.
[0091] The GERBER 752 file can be received in a 754 plate assembly process and used to create PCBs, such as a representative 756 PCB, manufactured according to design information stored within the GERBER 752 file. For example, the file GERBER 752 can be loaded on one or more machines to perform several steps in a PCB production process. PCB 756 can be filled with electronic components that include package 740 to form a representative printed circuit board (PCA) 758.
[0092] PCA 758 can be received in a 760 product manufacturing process and integrated with one or more electronic devices, such as a first representative electronic device 762 and a second representative electronic device 764. As an illustrative, non-limiting example, the first representative electronic device 762, the second representative electronic device 764, or both, can be selected from the group of “set top box” converters, a music player, a video player, an entertainment unit, an audio device navigation, a communication device, a personal digital assistant (PDA), a fixed location data unit and a computer, in which at least one controllable power consumption module is integrated. As another illustrative non-limiting example, one or more of the electronic devices 762 and 764 can be remote units, such as mobile phones, hand-held personal communication system (PCS) units, portable data units such as personal data assistants, devices enabled by the global positioning system (GPS), navigation devices, fixed location data units such as meter reading equipment or any other device that stores or retrieves data or computer instructions or any combination thereof. Although Figure 7 shows remote units according to the teachings of the description, the description is not limited to these exemplary units shown. The description modalities can be used appropriately in any device that includes a set of active integrated circuits that includes memory and a built-in circuit set.
[0093] A device that includes memory cell 106 of Figure 1 (for example, equipment 100 in Figure 1), a device that includes memory cell 206 of Figure 2 (for example, equipment 200 of Figure 2) , a device including memory cell 306 of Figure 3 (for example, equipment 300 of Figure 3), a device that includes cell with multiple non-volatile multi-port memories 412 of Figure 4 (for example, equipment 400 of Figure 4), or any combination of them can be manufactured, processed and incorporated into an electronic device, as described in illustrative process 700. One or more aspects of the modalities revealed with respect to Figures 1-4 can be included in several processing stages, such as within the library file 712, the GDSII file 726 and the GERBER 752 file, as well as stored in the computer's memory 710 search 706, in the memory 718 of the projected computer 714, in the memory 750 of the computer 746, in the memory of one or more other computers or processors (not shown) used in the various stages, such as in the process of assembling plates 754, and also incorporated into one or more other physical modalities, such as mask 732, tablet 736, package 740, PCA 758, other products such as prototypical circuits or devices (not shown) or any combination thereof. Although several production stages representative of a physical device project up to a final product are shown, in other modalities fewer stages may be used or additional stages may be included. Similarly, process 700 can be performed by a single entity or by one or more entities that perform multiple stages of process 700.
[0094] Those skilled in the art would also understand that the various logic blocks, configurations, modules, circuits and illustrative method steps described in connection with the modalities described here can be implemented as electronic hardware, computer software executed by a processing unit or combinations of both. Several components, blocks, configurations, modules, circuits and illustrative steps have been described above generally in terms of their functionality. Whether such functionality is implemented as executable hardware or processing instructions depends on the specific application and the design restrictions imposed on the system as a whole. Those skilled in the art can implement the functionality described in different ways for each specific application, but such implementation decisions should not be interpreted as causing a departure from the scope of this description.
[0095] A software module can reside in a random access memory (RAM), a magneto-resistive random access memory (MRAM), a spin torque transfer MRAM (STT-MRAM), flash memory, exclusive memory read (ROM), programmable read memory (PROM), exclusive erasable programmable memory (EPROM), exclusive electrically erasable programmable read memory (EEPROM), in registers, on a hard disk, a removable disk, an exclusive memory compact disc (CD-ROM) or any other form of storage media known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium can be integrated with the processor. The processor and storage medium can reside on an application-specific integrated circuit (ASIC). The ASIC can reside on a computing device or on a user terminal. Alternatively, the processor and storage medium can reside as discrete components in a computing device or user terminal.
[0096] The previous description of the disclosed modalities is provided to allow anyone skilled in the art to manufacture or use the described modalities. Several modifications to these modalities will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other modalities without abandoning the scope of the description. Thus, the present description is not intended to be limited to the modalities shown here, but should receive the widest possible scope compatible with the principles and unpublished aspects defined by the attached claims.

权利要求:
Claims (9)
[0001]
1. A memory device (101), comprising: a decoder (202); a plurality of memory cells (106), each of the memory cells comprising: a corresponding first non-volatile memory element (108) including a corresponding first resistive memory element (110) and associated with a first chain ; and a second corresponding non-volatile memory element (112) which includes a second resistive memory element (114) corresponding to and associated with a second chain, the device characterized by the fact that: each among the first non-volatile memory element (108 ) and the second non-volatile memory element (112) is a multi-port memory element, and the decoder is configured to receive, for each port (P0, P1) of the multi-port memory elements, a respective address entry port (240, 241) to select a corresponding cell from among the memory cells to be accessed with the port and receive a chain selection entry (250); where: if the chain selection input (250) is at a low level, the decoder (202) is configured to, for each port of the multi-port memory elements, select the first non-volatile memory element (108) of the corresponding memory cell selected to be accessed with the port, and if the string selection input (250) is at a high level, the decoder (202) is configured to, for each port of the multi-port memory elements, select the second non-volatile memory element (112) of the selected corresponding memory cell to be accessed with the door.
[0002]
2. Memory device according to claim 1, characterized by the fact that a bit line controller (230) coupled to at least one of the memory cells (106) is responsive to a read / write control input (236).
[0003]
3. Memory device, according to claim 1, characterized by the fact that the memory device is a Magnetic Resistive Random Access Memory, MRAM, which is preferably configured to record data using spin torque transfer, STT.
[0004]
4. Memory device according to claim 1, characterized by the fact that the first non-volatile memory element (108) and the second non-volatile memory element (112) each correspond to a common bit within a single register file, in which the first non-volatile memory element (108) stores information about the first state which corresponds to a first instruction stream (124) and the second non-volatile memory element (112) stores information about the second state which corresponds to a second flow of instructions (126).
[0005]
5. Memory device according to claim 1, characterized by the fact that it is integrated in at least one semiconductor chip (736).
[0006]
6. Memory device according to claim 1, characterized by the fact that it additionally comprises a device selected from a group consisting of a “set top box”, a music player, a video player, a unit entertainment device, a navigation device, a communication device, a personal digital assistant, PDA, a fixed location data unit and a computer, into which the memory device is integrated.
[0007]
7. System, characterized by the fact that it comprises: a processor (708); and a memory device as defined in claim 1.
[0008]
8. Method for operating a memory device (101) comprising a decoder (202) and a plurality of memory cells (106), each of the memory cells comprising a first non-volatile memory element (108) corresponding which includes a corresponding first resistive memory element (110) and associated with a first chain; and a corresponding second non-volatile memory element (112) that includes a corresponding second resistive memory element (114) and associated with a second chain; the method characterized by the fact that each between the first non-volatile memory element (108) and the second non-volatile memory element (112) is a multi-port memory element coupled to a first (213, P0) and second port (211, P1) and comprising: receiving, by the decoder, for each port (P0, P1) of the multi-port memory elements, a respective port address entry (240, 241) to select a corresponding cell among the cells memory to be accessed with the door; receiving, in the decoder, a chain selection input (250); select, if the chain selection input (250) is at a low level, for each port of the multi-port memory elements, the first non-volatile memory element (108) of the selected corresponding memory cell to be accessed with the door; select, if the chain selection input (250) is at a high level, for each port of the multi-port memory elements, the second non-volatile memory element (112) of the selected corresponding memory cell to be accessed with the door. receiving (502) first data (wData_P0) associated with the first port and receiving second data (wData_P1) associated with the second port; storing (504) the first data in a selected element of the first non-volatile memory element (108) and the second non-volatile memory element (112) of the selected corresponding memory cell to be accessed by the first port; and storing (506) the second data in the selected memory element of the first non-volatile memory element (108) and the second non-volatile memory element (112) of the selected corresponding memory cell to be accessed by the second port.
[0009]
9. Computer-readable memory, characterized by the fact that it contains the method as defined in claim 8.

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法律状态:
2019-01-08| B06F| Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]|

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2019-09-17| B06U| Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]|

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2020-07-28| B09A| Decision: intention to grant [chapter 9.1 patent gazette]|

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2020-12-01| B16A| Patent or certificate of addition of invention granted|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 22/03/2011, OBSERVADAS AS CONDICOES LEGAIS. |

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