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    • 专利摘要:
    A system and method for dynamically controlling a plurality of cores in a multi-core central processing unit based on temperature A method for controlling power within a multi-core central processing unit (cpu) is described. the method may include monitoring the temperature of a matrix, determining a degree of parallelism within a cpu workload, and turning one or more cpu cores on or off based on the degree of parallelism, the matrix temperature, or a combination of such.
    公开号:BR112012014306B1
    申请号:R112012014306-9
    申请日:2010-12-08
    公开日:2020-09-24
    发明作者:Sumit Sur；Bohuslav Rychlik；Thomson Steven S；Ali Iranli；Brian J. Salsbery
    申请人:Qualcomm Incorporated；
    IPC主号:
    专利说明:

    [0001] [0001] This patent application claims priority for US Provisional Patent Application Serial No. 61/287 011, entitled "SYSTEM AND METHOD OF DINAMICALLY CONTROLLING A PLURALITY OF CORES IN A MULTICORE CENTRAL PROCESSING UNIT", filed on December 16 2009. DESCRIPTION OF THE RELATED TECHNIQUE
    [0002] [0002] Portable computing devices (PDs) are ubiquitous. Such devices may include cell phones, personal data assistants (PDAs), handheld game consoles, "palmtop" computers and other portable electronic devices. In addition to the main function of such devices, several of them include peripheral functions. As an example, a cell phone may include the primary function of making phone calls and the peripheral functions of a camera, a video camera, navigation through the Global Positioning System (GPS), web browsing, sending and receiving e- mails, sending and receiving text messages, PTT-type features (push to talk / Push-To-Talk) and so on. As the functionality of such devices expands, the computing or processing power needed to support such functionality also grows. In addition, as computing power grows, there is an increasing demand for effective management of the processor or processors that provide computing power.
    [0003] [0003] Therefore, what is needed is an improved method to control the power / energy inside a multi-core CPU. BRIEF DESCRIPTION OF THE DRAWINGS
    [0004] [0004] In the figures, similar numerical references identify corresponding items in all the different views unless otherwise indicated.
    [0005] [0005] Figure 1 illustrates a front view in projection of a first embodiment of a portable computing device (PCD) in a closed position.
    [0006] [0006] Figure 2 illustrates a front view in projection of the first embodiment of a PCD in an open position.
    [0007] [0007] Figure 3 illustrates a block diagram of a second embodiment of a PCD.
    [0008] [0008] Figure 4 illustrates a block diagram of a processing system.
    [0009] [0009] Figure 5 illustrates a flow chart of a first embodiment of a method for controlling a central multicore / multicore processing unit based on temperature.
    [0010] [0010] Figure 6 illustrates a flowchart of a second embodiment of a method for controlling a central multi-core processing unit based on temperature.
    [0011] [0011] Figure 7 illustrates a flow chart of a first part of a third embodiment of a method for controlling a central multi-core processing unit based on temperature; and
    [0012] [0012] Figure 8 illustrates a flowchart of a second part of the third embodiment of a method for controlling a central multi-core processing unit based on temperature. DETAILED DESCRIPTION
    [0013] [0013] The term "exemplary" is used here exclusively with the meaning of "serving as an example, case or illustration". Any embodiment described herein as "exemplary" should not necessarily be regarded as preferred or advantageous over other embodiments.
    [0014] [0014] In the present description, the term "application" may also include files containing executable content, such as an object code, "scripts", a byte code, "markup" and "patches" language files or patches. In addition, an "application" mentioned here may also include files that are not executable in nature, such as documents that need to be opened, or other data files that must be accessed.
    [0015] [0015] The term "content" can also include files containing executable content, such as: an object code, "scripts", a byte code, "markup" and "patches" language files or corrections. In addition, the "content" referred to herein may also include files that are not executable in nature, such as documents that need to be opened, or other data files that must be accessed.
    [0016] [0016] As used in this description, the terms "component", "database", "module", "system" and the like refer to an entity related to computers, whether hardware, firmware, a combination of hardware and software, software, or running software. As an example, a component can be, but is not limited to, a process "running" on a processor, a processor, an object, an executable, a thread or chain of execution, a program and / or a computer. As an example, both an application running on a computing device and the computing device can be a component. One or more components can reside in a process and / or chain of execution, and a component can be located on a computer and / or distributed between two or more computers. In addition, such components can be executed from various means for reading by computer having several data structures stored therein. Components can communicate via local and / or remote processes, such as according to a signal having one or more data packets (for example, data from a component that interacts with another component on a local system, a distributed system, and / or over a network, such as the Internet, with other systems, through the signal).
    [0017] [0017] Referring initially to Figures 1 and 2, there is presented an exemplary portable computing device (PCD), generally referred to as 100. As shown, the PCD 100 may include a case, box, or housing 102 Case 102 may include an upper case portion 104 and a lower case portion 106. Figure 1 shows that the upper case portion 104 may include a display or display 108. In a specific embodiment, display 108 may be a touch screen. The upper case 104 may also include a trackball input / power device 110. In addition, as shown in Figure 1, the upper case 104 may include a button or power button 112 and a off button or key 114. As shown in Figure 1, the upper case portion 104 of the PCD 100 can include a plurality of indicator lights 116 and a speaker 118. Each indicator light 116 can be a light emitting diode ( LED).
    [0018] [0018] In a specific embodiment, as illustrated in Figure 2, the upper case part 104 is movable with respect to the lower case part 106. Specifically, the upper case part can slide relative to the lower case part 106. As shown in Figure 2, the lower case portion 106 may include a multi-key keyboard 120. In a specific embodiment, the multi-key keyboard 120 may be a standard QWERTY keyboard. The multi-key keyboard 120 can be discovered when the upper case part 104 is moved relative to the lower case part 106. Figure 2 further illustrates that the PCD 100 can include a reset key 122 in the lower case part 106.
    [0019] [0019] Referring to Figure 3, an exemplary non-limiting embodiment of a portable computing device (PCD) is generally designated as 320. As shown, the PCD 320 includes an "embedded" or online system chip 322 which includes a "multicore" or multicore CPU 324. Multicore CPU 324 may include a 0 325 core, a first core 326, and a core No. 327.
    [0020] [0020] As shown in Figure 3, a display controller 328 and a touchscreen / touchscreen controller "330 are coupled to the multicore CPU 324. In turn, a touchscreen or touchscreen 332 external to the on-chip system 322 is coupled to the display controller 328 and the touch screen controller 330.
    [0021] [0021] Figure 3 also indicates that a 334 video encoder, for example, a PAL (Phase Alternating Line) encoder, a SECAM encoder (Séquentiel Couleur A Memoire), or an NTSC encoder (National Television System Committee), is coupled multicore CPU 324. In addition, a video amplifier 336 is attached to the video encoder 334 and the touchscreen / touchscreen 332. In addition, a video port 338 is attached to the video amplifier 336. As shown in Figure 3, a universal serial bus (USB) controller 340 is attached to the multicore CPU 324. In addition, a USB port 342 is attached to the USB controller 340. A 344 memory and a SIM (Subscriber Identity Module) 346 card can also be coupled to the multicore processor 324. In addition, as shown in Figure 3, a digital camera 348 can be coupled to the multicore CPU 324. In an exemplary embodiment, the digital camera 348 is a C camera device CD (Charge-Coupled Device) or CMOS (complementary metal oxide semiconductor) camera.
    [0022] [0022] As further illustrated in Figure 3, a stereo audio CODEC 350 may be coupled to the multicore CPU 324. In addition, an audio amplifier 352 may be coupled to the stereo audio CODEC 350. In an exemplary embodiment, a first first stereo speaker 354 and a second stereo speaker 356 are coupled to the audio amplifier 352. Figure 3 shows that a microphone amplifier 358 can also be coupled to the stereo audio CODEC 350. In addition, a 360 microphone can be attached to the microphone amplifier 358. In a specific embodiment, a radio tuner for frequency modulation (FM) 362 can be coupled to the stereo audio CODEC 350. Additionally, an FM antenna 364 is coupled to the FM radio tuner 362. In addition in addition, stereo headphones 366 can be coupled to the stereo audio CODEC 350.
    [0023] [0023] Figure 3 further indicates that a radio frequency (RF) transceiver 368 can be coupled to the multicore CPU 324. An RF switch 370 can be coupled to the RF transceiver 368 and an RF antenna 372. As shown in Figure 3, a keyboard 374 can be attached to the multicore CPU 324. In addition, a mono headset with a microphone 376 can be attached to the multicore CPU 324. In addition, a vibrating device 378 can be attached to the multicore CPU 324. Figure 3 shows also that a power supply 380 can be coupled to the on-chip system 322. In a specific embodiment, power supply 380 is a direct current (DC / DC) power supply that supplies power to the various components of the PCD 320 that require energy. In addition, in a specific embodiment, the power source is a rechargeable direct current (DC) battery or a DC power source that is derived from an alternating current (AC) to DC transformer that is connected to a source of AC power.
    [0024] [0024] The PCD 320 can also include a temperature sensor 382 that can be used to detect a matrix temperature associated with the PCD 320. In other words, the temperature sensor 382 can act as a device to detect a temperature of the matrix. matrix associated with the 320 PCD.
    [0025] [0025] Figure 3 also indicates that PCD 320 can also include a 388 network card, which can be used to access a data network, for example, a local area network, a personal area network, or any other network. network. The 388 network card can be a Bluetooth network card, a WiFi network card, a personal area network (PAN), a PEANUT personal network card (Personal Area Network Ultra Low Power Technology), or any other network card well known to technicians in the field. In addition, network card 388 can be incorporated into a chip, that is, network card 388 can be a complete solution on a chip, and may not be a separate network card 388.
    [0026] [0026] As shown in Figure 3, the touch screen display 332, the video port 338, the USB port 342, the camera 348, the first stereo speaker 354, the second stereo speaker 356, the 360 microphone , the FM antenna 364, the stereo headphones 366, the RF switch 370, the RF antenna 372, the keyboard 374, the mono headset 376, the vibrator 378, and the power source 380 are external to the online system 322 chip.
    [0027] [0027] In a specific embodiment, one or more of the method steps described herein can be stored in memory 344 in the form of computer program instructions. Such instructions can be carried out by the multi-core CPU 324 in order to execute the methods described herein. In addition, the multicore CPU 324, memory 344, temperature sensor 382, or a combination thereof, can serve as a device for performing one or more of the steps described here, in order to control a central control unit. multi-core processing based on temperature.
    [0028] [0028] Referring to Figure 4, there is illustrated a processing system, generally referred to as 500. In a specific embodiment, the processing system 500 can be incorporated in the PCD 320 described above with reference to Figure 3. As illustrated, the processing system 500 may include a multicore central processing unit (CPU) 402 and a memory 404 connected to the multicore CPU 402. The multicore CPU 402 may include a core 410, a first core 412, and a core No. 414. Core 0 410 may include a zero dynamic clock and voltage scaling (DCVS) 416 algorithm being run on it. The first core 412 may include a first DCVS algorithm 417 executed therein. In addition, core No. 414 may include a No. DCVS algorithm executed therein. In a specific embodiment, each DCVS 416, 417, 418 algorithm can be independently run on a respective core 412, 414, 416.
    [0029] [0029] In addition, as illustrated, memory 404 may include an operating system 420 stored therein. Operating system 420 may include programmer 422 and programmer 422 may include a first run queue 424, a second run queue 426, and an In run queue 428. Memory 404 may also include a first application 430, a second application 432, and an application No. 434 stored there.
    [0030] [0030] In a specific embodiment, applications 430, 432, 434, can send one or more jobs 436 to operating system 420 to be processed in cores 410, 412, 414, in multicore processor 402. Jobs 436 can be processed, or executed, as single tasks, threads / chains, or a combination thereof. In addition, programmer 422 can schedule or program tasks, threads, or a combination of them, to run within the multicore CPU 402. Additionally, programmer 422 can position tasks, threads, or a combination of them, in the queues. execution 424, 426, 428. Cores 410, 412, 414 can retrieve tasks, threads, or a combination of them from execution queues 424, 426, 428, as instructed, for example by operating system 420, for processing , or execution, of those threads and tasks in cores 410, 412, 414.
    [0031] [0031] Figure 4 also shows that memory 404 may include a parallelism monitor 440 stored therein. Parallelism monitor 440 can be connected to operating system 420 and multicore CPU 402. Specifically, parallelism monitor 440 can be connected to scheduler 422 within operating system 420. As described here, parallelism monitor 440 can monitor the workload on cores 410, 412, 414, and the parallelism monitor 440 can control power to cores 410, 412, 414, as described below.
    [0032] [0032] In a specific embodiment, the parallelism monitor 440 can be a software program that controls execution queues 424, 426, 428, in programmer 422. Each execution queue 424, 426, 428, also known as queue "ready-to-run", or "ready to run", can include a list of tasks, threads, or a combination of these, which are available for programming / scheduling on one or more cores 410, 412, 414. Some systems multicore can only have a single "ready-to-run" row. Other multicore systems can have multiple ready-to-run queues. Regardless of this, the number of queues ready to run, at any point in time, the total number of tasks, threads, or a combination of these, waiting in such queues, plus a certain number of tasks, threads, or a combination of these really running, can be an approximation to the degree of parallelism in the workload.
    [0033] [0033] Referring to Figure 5, there is illustrated a first embodiment of a method for controlling a central multi-core processing unit based on temperature, which is generally referred to as 500. Method 500 can start at block 502, with a "TO-DO" link or to be made, in which, when the device is turned on, the following steps can be performed.
    [0034] [0034] In block 504, a matrix temperature can be monitored. In addition, in block 506, a power controller can determine a degree of parallelism in the workload associated with the cores.
    [0035] [0035] Moving to block 508, the power controller can independently turn the cores on and off based on the degree of parallelism in the workload, the matrix temperature, or a combination thereof. Then, in decision 510, the power controller can determine whether the device is turned off. If the device is turned off, the method may terminate. Otherwise, if the device remains on, method 500 can return to the block to return 504 and can continue as described.
    [0036] [0036] Referring to Figure 6, there is illustrated a second embodiment of a method to control a central multi-core / multicore processing unit based on the temperature generally called 600. Method 600 can start in the block 602 with a dynamic clock and voltage scaling (DCVS) running, or running, on all cores operating within a central multicore processing unit. Moving to block 604, a sampling delay can be performed. In a specific embodiment, the sampling delay can be a hundred milliseconds or less. In another embodiment, the sampling delay can be fifty milliseconds or less. The sampling delay can be introduced in order to avoid very rapid churning or churn in the system. In addition, it usually takes some time to activate another core and the sampling delay may be longer than the activation time.
    [0037] [0037] Passing decision 606, a core controller can determine if the matrix temperature is equal to one of a critical condition or condition. As an example, the critical state may be a threshold temperature above which the device's operation may begin to fail due to temperature problems.
    [0038] [0038] In decision 606, if the matrix temperature is not equal to a critical condition, method 600 can return to block 602 and method 600 can continue as described here. Otherwise, if the matrix temperature is equal to a critical condition, method 600 can pass decision 608 and the core controller can determine if a second core is at rest, for example the second core can be CPU 1 (the first core may be CPU 0).
    [0039] [0039] If the second core is not at rest, that is, CPU 1 is active and executing tasks and chains / threads, method 600 can pass to block 610. In block 610, the frequency of the first core, CPU 0, it can be adjusted, or otherwise modified, for the maximum reduction of the frequency of the first core in an increment / modification step to an ideal frequency, Fopt. In other words, the core controller can reduce the frequency of the second core by one step of increment without going below an ideal frequency, Fopt. The incremental step can be one hundred mega-hertz (100 MHz) or less. In addition, the incremental step can be 50 megahertz (50 MHz) or less. From block 610, method 600 may return to block 602 and method 600 may continue as described.
    [0040] [0040] Returning to decision 608, if CPU 1 is at rest, that is, CPU 1 is off, method 600 can pass to decision 612. In decision 612, a controller can determine whether a degree of parallelism meets a condition. Specifically, the controller can determine whether the degree of parallelism is greater than a predetermined limit, indicating that there is sufficient parallelism in the system to justify the operation of a second core, CPU 1.
    [0041] [0041] In decision 612, if the degree of parallelism does not meet the condition, the method can pass to block 614 and the frequency of the first core, CPU 0, can be defined, or otherwise modified, for the maximum reduction of the frequency of the first core in an incremental step and for an ideal frequency, Fopt. In other words, the core controller can reduce the frequency of the second core by one step of increment without going below an ideal frequency, Fopt. Thereafter, method 600 may return to block 602 and method 600 may continue as described herein.
    [0042] [0042] Returning to decision 612, if the degree of parallelism meets the condition, the method can proceed to block 616 and the second CPU, CPU 1, can be connected. Then, in block 618, the frequency of the second core, CPU 1, can be adjusted to an ideal frequency, Fopt. In addition, in block 618, the frequency of the first core, CPU 0, can be defined as the maximum of the current frequency of the first core minus the ideal frequency, Fopt, or for the ideal frequency, Fopt. As an example, if CPU 0 is operating at 1000 mega-hertz (1000 MHz) and CPU 1 is connected to an ideal frequency of 600 mega-hertz (600 MHz), the frequency of CPU 0 can be changed to 600 mega- hertz (600 MHz), since 1000 MHz minus 600 MHz is equal to 400 megahertz (400 MHz) and 600 MHz (the ideal frequency, Fopt) is greater than 400 MHz (the result of the subtraction operation).
    [0043] [0043] In another example, if CPU 0 is operating at 1000 mega-hertz (1400 MHz) and CPU 1 is connected to an ideal frequency of 600 mega-hertz (600 MHz), the frequency of CPU 0 can be changed to 800 mega-hertz (800 MHz) because 1400 MHz minus 600 MHz is equal to 800 mega-hertz (800 MHz) and 800 MHz (the result of the subtraction operation) is greater than 600 MHz (the ideal frequency, Fopt).
    [0044] [0044] By passing decision 620, the controller can determine whether there is sustained parallelism in the system. In other words, the controller can determine whether the degree of parallelism in the system meets a condition for at least a predetermined amount of time. The condition can be a limit value of parallelism and, if the parallelism in the system is greater than the limit value, the condition can be considered fulfilled. In decision 620, if the parallelism is sustained, method 600 can return to block 602 and method 600 can continue as described here.
    [0045] [0045] Returning to decision 620, if the parallelism is not sustained, method 600 can proceed to block 622 and the second core, CPU 1, can be turned off. Next, method 600 can return to block 602 and method 600 can continue as described herein.
    [0046] [0046] Referring now to Figures 7 and 8, there is illustrated a third embodiment of a method for controlling a central multi-core processing unit based on temperature, generally referred to as 700. Method 700 can be start at block 702 with a dynamic clock algorithm and voltage scaling (DCVS) in operation, or execution, in all cores operating within a central multicore processing unit. Moving to block 704, a sampling delay can be performed. In a specific embodiment, the sampling delay can be a hundred milliseconds or less. In another embodiment, the sampling delay can be fifty milliseconds or less. The sampling delay can be introduced in order to avoid very sudden agitation in the system. In addition, it usually takes some time to activate another core and the sample delay may be longer than the activation time.
    [0047] [0047] Moving to decision 706, a core controller can determine whether the matrix temperature is equal to a critical state or condition. As an example, the critical state may be a threshold temperature above which device operation may start to fail due to temperature problems.
    [0048] [0048] In decision 706, if the matrix temperature is not equal to a critical state, method 700 can return to block 702 and method 700 can continue as described here. Otherwise, if the matrix temperature is equal to a critical condition, method 700 can pass decision 708 and the core controller can determine whether a second core is at rest or "dormant", for example the second core can be a CPU 1 (the first core can be CPU 0). If the second core is not dormant, method 700 can pass decision 802 of Figure 8 and method 700 can continue as described here.
    [0049] [0049] Otherwise, if CPU 1 is not at rest, that is, CPU 1 is off, method 700 can pass decision 710. In decision 710, a controller can determine whether a degree of parallelism meets a condition . Specifically, the controller can determine whether the degree of parallelism is greater than a predetermined limit, indicating that there is sufficient parallelism in the system to justify the operation of a second core, CPU 1.
    [0050] [0050] In decision 710, if the degree of parallelism does not meet the condition, the method can pass to block 712 and the frequency of the first core, CPU 0, can be defined, or otherwise modified, for the maximum reduction of the frequency of the first core in an incremental step to an ideal frequency, Fopt. In other words, the core controller can reduce the frequency of the second core by an incremental step without going below an ideal frequency, Fopt. Thereafter, method 700 may return to block 702 and method 700 may continue as described herein.
    [0051] [0051] Returning to decision 710, if the degree of parallelism meets the condition, the method can proceed to block 714 and the second CPU, CPU 1, can be connected. Then, in block 716, the frequency of the second core, CPU 1, can be defined as an ideal frequency, Fopt. In addition, in block 716, the frequency of the first core, CPU 0, can be defined as the maximum of the current frequency of the first core minus the ideal frequency, Fopt, or as the ideal frequency, Fopt.
    [0052] [0052] Moving to decision 718, the controller can determine if there is sustained parallelism in the system. In other words, the controller can determine whether the degree of parallelism in the system meets a condition for at least a predetermined amount of time guaranteeing the continued functioning of both cores. The condition can be a limit value of parallelism and, if the parallelism in the system is greater than the limit value, the condition can be considered as fulfilled. In decision 718, if the parallelism is sustained, method 700 can return to block 702 and method 700 can continue as described here.
    [0053] [0053] Going back to decision 718, if the parallelism is not sustained, method 700 can pass to block 720 and the second core, CPU 1, can be turned off. Thereafter, method 700 may return to block 702 and method 700 may continue as described herein.
    [0054] [0054] Returning to decision 708, if the second core, CPU 1, is not at rest, method 700 can pass to decision 802. In decision 802, the core controller can determine whether a core No., CPU N is in rest. If the core number is not at rest, method 700 can pass to block 804. In block 804, the frequency of the first core, CPU 0, can be set, or otherwise modified, for maximum frequency reduction. first core on an incremental step and an ideal frequency, Fopt. In other words, the core controller can reduce the frequency of the second core by an incremental step without going below an ideal frequency, Fopt. In addition, the frequency of the second core, CPU 1, can be set, or otherwise modified to the maximum reduction of the frequency of the first core in an incremental step and an ideal frequency, Fopt. In addition, the frequency of the core No., CPU N, can be set, or otherwise modified to the maximum reduction in the frequency of the first core in an incremental step and an ideal frequency, Fopt. From block 804, method 700 can return to block 702 of Figure 7 and method 7 00 can continue as described here.
    [0055] [0055] Returning to decision 802, if CPU N is not at rest, that is, CPU 1 is active and executing tasks and threads, method 700 can proceed to decision 806. In decision 806, a controller can determine whether a degree of parallelism meets a condition. Specifically, the controller can determine if the degree of parallelism is greater than a predetermined limit, indicating that there is not enough parallelism in the system to justify the operation of a core No., CPU N.
    [0056] [0056] In decision 806, if the degree of parallelism does not meet the condition, the method can pass to block 808 and the frequency of the first core, CPU 0, can be defined, or otherwise modified, for the maximum reduction of the frequency of the first core in an incremental step and an ideal frequency, Fopt. In other words, the core controller can reduce the frequency of the second core by one step of increment without going below an ideal frequency, Fopt. In addition, in block 808, the frequency of the second core, CPU 2, can be defined, or otherwise modified, for the maximum reduction of the frequency of the first core in an incremental step and an ideal frequency, Fopt. Next, method 700 can return to block 702 of Figure 7 and method 700 can continue as described herein.
    [0057] [0057] Returning to decision 806, if the degree of parallelism meets the condition, the method can proceed to block 810 and the Na CPU, CPU N, can be turned on. Later, in block 812, the frequency of the core number, CPU N, can be defined as an ideal frequency, Fopt. In addition, in block 812, the frequency of the first core, CPU 0, and the second core, CPU 1, can be defined as the maximum current frequency of the first core minus the ideal frequency, Fopt, or as the ideal frequency, Fopt .
    [0058] [0058] Moving to decision 814, the controller can determine if there is sustained parallelism in the system. In other words, the controller can determine whether the degree of parallelism in the system meets a condition for at least a predetermined amount of time to guarantee the functioning of the N cores. The condition can be a limit value of parallelism and, if the parallelism in the system is greater than the limit value, the condition can be considered fulfilled. In decision 814, if the parallelism is sustained, method 700 can return to block 802 and method 700 can continue as described here.
    [0059] [0059] Returning to decision 814, if the parallelism is not sustained, method 700 can pass to block 822 and one or more cores can be disconnected. Next, method 700 can return to block 702 of Figure 7 and method 700 can continue as described herein.
    [0060] [0060] It should be clear that the method steps described here should not necessarily be carried out in the order as described. In addition, words like "next", "then", "next" and so on are not intended to limit the order of steps. These words are simply used to guide the reader through the description of the method steps. In addition, the methods described here are described as executable on a portable computing device (PCD). The PCD can be a mobile phone device, a portable digital assistant device, a smartbook computing device, a netbook type computing device, a laptop type computing device, a desktop computing device, or a combination of such.
    [0061] [0061] In a specific embodiment, it can be noted that the dynamic power in a system is proportional to V2f, where f is the clock frequency and V represents the voltage. The voltage is also directly proportional to the frequency. In other words, there is a minimum voltage for the CPU to operate at a given clock frequency. Therefore, the heat generated in the matrix is approximately proportional to f3. In certain embodiments, it may be possible that, when a particular device is assembled, the device may not be able to sufficiently dissipate the heat generated when a CPU core is operated at or near its highest frequency.
    [0062] [0062] The system and method described here provide a way to avoid overheating a device by taking advantage of the parallelism in the system, distributing the workload among multiple cores, thereby operating each core at a much lower frequency. Due to the cubic non-linearity in the generation of heat in relation to the clock frequency, the operation of two cores at lower frequencies will result in the generation of much less heat compared to when it is executed in a single core, without worsening the user.
    [0063] [0063] In a specific embodiment, the degree of parallelism in the workload can be dynamically inferred at the task / thread level by monitoring the state of the operating system. As an example, an operating system state that can be monitored is the length of all "ready-to-run" wires in the operating system programmer. The ready-to-run queue scheduler consists of a list of current thread / chain tasks that are available for scheduling / programming on the CPUs.
    [0064] [0064] By using a parallelism monitor, the system may be able to determine whether there is sufficient parallelism in the system at any point in time, and whether the parallelism is maintained over a period of time. This information can be used in the load balancing algorithm described here.
    [0065] [0065] The load balancing algorithm described here can periodically determine temperature measurements of the matrix as one of its inputs / feeds. In addition, the load balancing algorithm can compare the matrix temperature with a limit temperature, THS, which is the highest temperature still considered safe for the proper operation of an appliance. In a specific embodiment, THS can be found through testing.
    [0066] [0066] In a specific embodiment, for each core there will be a voltage and frequency value, Fopt, more efficient. Fopt may be close to the highest frequency level that the minimum operating voltage can sustain. For a homogeneous system based on a "dual-core" CPU, both cores running Fopt may not generate enough heat to raise the temperature beyond THS. During operation, the operating frequencies of the CPU can be changed incrementally and are often a handful of different values, typically in steps of 50 to 100 MHz.
    [0067] [0067] From any point in time, if the temperature sensor ever exceeds the THS temperature limit, a controller can check whether a core or both cores are operating. If only one core is operating, the controller checks whether there is sufficient parallelism in the system. If there is enough parallelism, the controller can activate the second core in Fopt, reducing the frequency of the first core by the same amount, unless this brings the frequency below Fopt. If lowering the frequency of the first core brings the frequency down to Fopt, the controller leaves the first core to Fopt. Again, it can be noted that the operation of the two cores running on Fopt, may not increase the temperature beyond THS. The distribution of work between two cores can cool the system, without loss of MIPS and detriment to the user experience.
    [0068] [0068] In one or more exemplary embodiments, the functions described here can be implemented in hardware, software, firmware, or any combination of these. If implemented in software, the functions can be stored in, or transmitted through, one or more instructions or code in a computer program product, such as a means for reading by machine, that is, a means for reading by computer. Computer-readable media includes media for computer storage and media for communication, including any media that facilitates the transfer of a computer program from one place to another. A storage medium can be any available medium that can be accessed by a computer. As an example, but not a limitation, such computer-readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, storage on magnetic disks, or any other storage devices that can be used to transport or store the desired program codes in the form of instructions or data structures that can be accessed by a computer. In addition, any connection is appropriately designated as a medium for computer reading. As an example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies, such as infrared, radio and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL or wireless technologies such as infrared, radio, microwave, are included in the definition of medium. Disc as used here, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray discs. Combinations of these should also be included in the scope of computer-readable media.
    [0069] [0069] Although selected embodiments have been illustrated and described in detail, it should be clear that various substitutions and changes can be made to them without constituting a departure from the spirit and scope of the present invention, as defined by the claims that follow.
    权利要求:
    Claims (13)
    [0001]
    Method for controlling power in a multi-core central processing unit (CPU), the method characterized by the fact that it comprises: monitoring the temperature of a matrix (504) and determining (606, 706) whether the temperature of the matrix is equal to a critical condition; determining (608, 708) whether a second core is at rest when the matrix temperature is equal to a critical condition; reducing (610, 804) a frequency of a first nucleus by an increment step without being below an ideal frequency in response to the determination that the second nucleus is not at rest; determining (506, 612, 710, 802) a degree of parallelism in a CPU workload in response to determining that the second core is at rest; determine whether the parallelism is greater than a predetermined limit; and energize (616, 714, 810) the second core at an ideal frequency when the degree of parallelism is greater than a predetermined limit.
    [0002]
    Method according to claim 1, characterized by the fact that it additionally comprises: reduce a frequency of the second core by an increment step without being below an ideal frequency when the second core is active.
    [0003]
    Method according to claim 1, characterized by the fact that it additionally comprises: reduce (618, 716, 812) a frequency of the first core to a value that is a maximum of a current operating frequency minus an ideal frequency and the ideal frequency when energizing the second core.
    [0004]
    Method, according to claim 3, characterized by the fact that it additionally comprises: determine (620, 718, 814) whether the degree of parallelism is sustained over a period of time.
    [0005]
    Method according to claim 4, characterized by the fact that it additionally comprises: de-energize (622, 720, 816) the second core when the degree of parallelism is not sustained.
    [0006]
    Wireless device characterized by the fact that it comprises: mechanisms for monitoring a matrix temperature; mechanisms for determining whether the matrix temperature is equal to a critical condition; mechanisms for determining whether a second nucleus is at rest; mechanisms for reducing a frequency of a first nucleus in an increment step without being below an ideal frequency in response to the determination that the second nucleus is not at rest; mechanisms for determining a degree of parallelism in a CPU workload in response to determining that the second core is at rest; mechanisms for determining whether the degree of parallelism is greater than a predetermined limit; and mechanisms to energize the second core at an ideal frequency when the degree of parallelism is greater than a predetermined limit.
    [0007]
    Wireless device according to claim 6, characterized by the fact that it additionally comprises: mechanisms for reducing a frequency of the second core in an increment step without being below an ideal frequency when the second core is active.
    [0008]
    Wireless device according to claim 6, characterized by the fact that it additionally comprises: mechanisms to energize a second core to an ideal frequency when the degree of parallelism is greater than a predetermined limit.
    [0009]
    Wireless device according to claim 8, characterized by the fact that it additionally comprises: mechanisms for reducing a frequency of the first core to a value that is a maximum of a current operating frequency minus an ideal frequency and the ideal frequency.
    [0010]
    Wireless device according to claim 9, characterized by the fact that it additionally comprises: mechanisms for determining whether the degree of parallelism is sustained over a period of time.
    [0011]
    Wireless device according to claim 10, characterized by the fact that it additionally comprises: mechanisms to de-energize the second core when the degree of parallelism is not sustained.
    [0012]
    Wireless device characterized by the fact that it comprises: a processor, wherein the processor is operable to perform the method as defined in any one of claims 1 to 5.
    [0013]
    Computer readable memory characterized by the fact that it comprises: at least one instruction stored therein for execution by a computer of the method as defined in any of claims 1 to 5.
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    法律状态:
    2019-01-08| B06F| Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]|
    2019-08-06| B06U| Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]|
    2020-05-05| B09A| Decision: intention to grant [chapter 9.1 patent gazette]|
    2020-09-24| B16A| Patent or certificate of addition of invention granted|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 08/12/2010, OBSERVADAS AS CONDICOES LEGAIS. |
    优先权:
    申请号 | 申请日 | 专利标题
    US28701109P| true| 2009-12-16|2009-12-16|
    US61/287,011|2009-12-16|
    US12/944,564|2010-11-11|
    US12/944,564|US8775830B2|2009-12-16|2010-11-11|System and method for dynamically controlling a plurality of cores in a multicore central processing unit based on temperature|
    PCT/US2010/059560|WO2011084335A1|2009-12-16|2010-12-08|System and method for dynamically controlling a plurality of cores in a multicore central processing unit based on temperature|
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