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  • 专利说明
  • 权利要求
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    • 专利摘要:
    Invention Patent: "APPARATUS AND THERMAL CONTROL METHODOLOGY". The present invention concerns several modalities of a methodology and a thermal control device. In one embodiment, an integrated circuit includes one or more thermal sensors, a comparison circuit and a control circuit. The comparison circuit is configured to receive temperature readings from one or more thermal sensors. The control circuit is configured to reduce a performance level of one or more controlled subsystems that respond to the comparison circuit, determining that at least one temperature reading from one or more thermal sensors exceeds one of one or more limit values. A software-based thermal control mechanism can also run simultaneously with the device.
    公开号:BR102013015444B1
    申请号:R102013015444-0
    申请日:2013-06-19
    公开日:2020-12-08
    发明作者:Jim J. Lin；Kiran B. Kattel
    申请人:Apple Inc.；
    IPC主号:
    专利说明:

    BACKGROUND Field of the Invention
    [0001] The present invention relates to electronic systems and, more particularly, to the thermal control of electronic systems. Description of the Related Art
    [0002] As the number of integrated circuits implemented by transistors (ICs) has increased, the management of temperature-related issues has increased in importance. In many ICs, a large number of transistors operating at the same time can produce a significant amount of heat. If not controlled, the amount of heat generated by the operation of an IC's transistors can cause erroneous operation or permanent damage.
    [0003] Temperature sensors are implemented in many different types of ICs. One or more temperature sensors can be placed in an IC matrix and can be used to determine a temperature in a respective location on it. Temperature sensors can measure and report temperature information to another circuit, such as one or more registers. In some ICs, such as various types of processors and systems on a chip (SOCs), software can be run, which monitors the registers. If a temperature exceeding a predefined limit is detected, the software can initiate actions to shut down one or more parts of the IC. SUMMARY
    [0004] Various modalities of a methodology and a thermal control device are disclosed. In one embodiment, an integrated circuit includes one or more thermal sensors, a comparison circuit and a control circuit. The comparison circuit is configured to receive temperature readings from one or more thermal sensors. The control circuit is configured to reduce the performance level of one or more controlled subsystems that respond to the comparison circuit, determining that at least one temperature reading from one or more sensors exceeds one of one or more limit values.
    [0005] In one embodiment, the comparison circuit and the control circuit can operate in parallel with a software temperature control routine performed on a processor. In this way, the system can include hardware and software thermal monitoring and control mechanisms. The hardware engine (including, for example, the comparison circuit) can monitor temperature readings received from one or more temperature sensors more frequently than the software engine. If the hardware mechanism determines that a temperature reading exceeds a temperature limit, then the hardware mechanism can cause a corresponding reduction in a performance level for at least one corresponding functional unit of the IC. This reduction in the performance level can allow the temperature in the report sensor to fall back below the temperature limit before being verified by the software engine.
    [0006] In one mode, multiple temperature limits can be used. For example, the control circuit can reduce the performance of a subsystem controlled by a first quantity that responds to the determination that a corresponding temperature value has exceeded a first limit or by a second quantity that responds to the determination that the corresponding temperature value exceeded a second limit. The second limit can be greater than the first limit. The software engine can shut down the controlled subsystem (as well as other portions of the integrated circuit, in some modes), if a corresponding temperature reading exceeds the second limit. In some embodiments, the software engine cannot take action with the determination that a temperature reading exceeds the first limit. In this way, the hardware mechanism can be afforded an opportunity to maintain the temperature of several integrated circuit subsystems within safe limits, without having to perform a complete shutdown. The software engine can perform a shutdown of one or more controlled subsystems, only after the hardware engine is no longer able to maintain the respective temperatures within safe limits.
    [0007] Various types of performance reductions can be made by the control circuit in modalities other than the hardware mechanism. For example, the frequency of a clock signal provided to a controlled subsystem can be reduced in response to a temperature reading that exceeds a limit in one mode. Other types of performance reductions can include reductions in operating voltage, bandwidth limitations, reallocating a workload to another subsystem (for example, from one processor core to another), and so on. BRIEF DESCRIPTION OF THE DRAWINGS
    [0008] The following detailed description refers to the attached drawings, which are now briefly described.
    [0009] Fig. 1 is a block diagram of an integrated circuit modality.
    [00010] Fig. 2 is a block diagram of a modality of a hardware-based thermal control device.
    [00011] Figs. 3A and 3B are synchronization diagrams illustrating hysteresis in the operation of a modality of a hardware-based thermal control device.
    [00012] Fig. 4 is a flow chart illustrating the combined operation of a modality of a hardware-based thermal control mechanism in conjunction with a modality of a software-based thermal control mechanism.
    [00013] Fig. 5 is a block diagram of a modality of a system.
    [00014] Although the invention is susceptible to several modifications and alternative forms, its specific modalities are shown by way of example in the drawings and will be described in detail here. It should be understood, however, that the drawings and the detailed description are not intended to limit the invention to the particular form disclosed, but, on the contrary, the intention is to cover all modifications, equivalents and alternatives that are within the spirit and scope of the present invention, as defined by the appended claims. The headings here are for organizational purposes only and does not mean that they should be used to limit the scope of the description. As used throughout this application, the word "(may)" is used in a permissive sense (that is, meaning to have the potential for), rather than in a mandatory sense (that is, meaning must). Similarly, the words "include", "including" and "includes" mean including, but not limited to.
    [00015] Various units, circuits or other components can be described as "configured to" perform a task or tasks. In these contexts, "configured for" is a broad recitation of structure, in general, meaning "having circuit that" performs the task or tasks during operation. As such, the circuit / unit / component can be configured to perform the task, even when they are not currently activated. In general, the circuit that forms the corresponding "configured for" structure may include hardware circuits and / or executable memory storage program instructions to implement the operation. The memory may include volatile memory, such as static or dynamic random access memory and / or non-volatile memory, such as optical or magnetic disk storage, flash memory, read-only programmable memories, etc. Similarly, several circuits / units / components can be described as performing a task or tasks, for convenience in the description. These descriptions should be interpreted as including the phrase "configured for". Quoting again a unit / circuit / component, which is configured to perform one or more tasks, it is expressly intended not to invoke the interpretation of 35 U.S.C. § 112, paragraph six for that unit / circuit / component. DETAILED DESCRIPTION OF MODALITIES
    [00016] Now returning to Fig. 1, a block diagram of an integrated circuit (IC) modality is shown. In the mode shown, IC 10 is a system on a chip (SoC), including processor cores 12 and 14, a graphics unit 16 and an on-chip memory 18. Memory 18 in the mode shown can be a read-only memory ( ROM), a flash memory, a random access memory or any other suitable type of memory. The IC 10 also includes several thermal control mechanisms to monitor and regulate its temperature during operation. In this example, the processor cores 12 and 14 and the graphics unit 16 each include a temperature sensor. Each of the temperature sensors is coupled to the trip point circuit 13, which is configured to compare temperature readings received from each of the thermal sensors with one or more limit values. IC 10 also includes a thermal control circuit 15 which is coupled to receive comparison information from the trip point circuit 13. In this particular embodiment, the thermal control circuit 15 can adjust performance levels of the various functional units (or subsystems) of IC 10 by changing the clock signal frequencies received, respectively. It is also possible and considered modalities in which the thermal control circuit 15 can carry out other control actions to adjust the respective levels of performance. This action may include, but is not limited to, voltage adjustments, payload allocation / reallocation bandwidth adjustments, and so on.
    [00017] Trip point circuit 13 and thermal control circuit 15 may comprise a hardware-based thermal control mechanism. That is, the hardware-based thermal control mechanism in the mode shown is implemented using IC 10 hardware circuits. The IC 10 in this mode is also configured to implement a software-based thermal control mechanism that can operate in parallel with the mechanism. hardware-based thermal control system and complement it. More particularly, instructions for implementing software-based thermal control mechanism (SWTCM) 19 are stored in memory 18 in this embodiment. The SWTCM 19 instructions can be accessed by the processor core 12, which can execute the instructions to perform a software-based thermal control routine. During the execution of SWTCM instructions 19, processor core 12 can access temperature comparison results from trip point circuit 13 and can undertake thermal control actions based on them.
    [00018] As noted above, trip point circuit 13 can compare received temperature readings with one or more temperature limits. These limits can be programmable or they can be connected to the trip point circuit 13. In both cases, the report of the comparison results with the thermal control circuit 15 can be performed at predefined intervals. Simultaneous with the operation of the hardware-based thermal control mechanism, SWTCM instructions 19 executed by processor 12 can access trip point circuit comparison results 13 at their own predefined intervals. In the mode shown, the intervals at which trip point circuit 13 reports comparison results for thermal control circuit 15 may be shorter in duration than the intervals at which SWTCM 19 accesses comparison information from the trip point circuit. trip 13. In this way, the thermal control circuit 15 can receive updated comparison information more frequently than the comparison information is received by the SWTCM instructions 19 executed by the processor core 12.
    [00019] The thermal control circuit 15 in the mode shown is coupled to receive three different clock signals CPU 1 Clk, CPU 2 Clk and Graphics Clock. Output clock signals Clk 1, Clk 2 and Clk 3 are provided from the thermal control unit 15 to processor core 12, processor core 14 and graphics unit 16, respectively. The input clock signals can essentially serve as full frequency reference signals for their corresponding output clock signals. The thermal control circuit 15 in this particular embodiment can reduce the performance of any of the processor cores 12 and 14 and graphics unit 16 by dividing the input clock signals to produce respective output clock signals at a reduced frequency. In this mode, the clock signals can be divided independently of each other so that some units can operate in a reduced performance mode while others can operate in a full (normal) performance mode.
    [00020] Since the hardware-based thermal control mechanism updates at more frequent intervals than the software-based thermal control mechanism, the hardware-based mechanism can provide finer grain thermal control functionality for IC 10. In Consequently, as noted above, the hardware-based thermal control mechanism can perform various types of performance adjustments on the IC 10 that respond to certain comparison results. For example, if a temperature reading exceeds a first temperature limit, thermal control circuit 15 can reduce, by a first amount, the performance of a functional unit associated with the reporting temperature sensor 11. If the temperature reading exceeds a second temperature limit, the thermal control circuit can reduce, by a second quantity, the performance of the functional unit associated with the reporting temperature sensor. Using the example of a clock frequency, thermal control circuit 15 can reduce the frequency of a corresponding clock signal by a first amount, if the first temperature limit is exceeded and can reduce the frequency of the corresponding clock signal by a second quantity, if the second temperature limit is exceeded. In this particular example, the thermal control action was performed with respect to only the functional unit associated with the reporting temperature sensor. However, it is possible and considered modalities in which performance reductions can be made for additional functional units that respond to a temperature reading that exceeds one of the limits. It is also noted that, in response to a temperature reading that falls below one of the limit values, performance can be restored to values from which they have previously been reduced.
    [00021] The hardware-based thermal control mechanism may include hysteresis in its operation. The thermal control circuit 15 may not immediately reduce the performance level of one or more functional units that respond to an initial indication of a temperature reading from a particular temperature sensor 11 that exceeds a threshold. In fact, the thermal control circuit 15 can wait for a predetermined time. If, after the predetermined time has elapsed, the temperature reading of the particular temperature sensor 11 is still above the limit, the thermal control circuit 15 can perform a thermal control action, such as reducing the clock frequency to at least the corresponding functional unit. If, on the other hand, the temperature reading of the particular temperature sensor 11 falls back below the threshold voltage before the predetermined time has elapsed, the thermal control circuit 15 can maintain the performance level of the corresponding functional unit in its current level.
    [00022] Hysteresis can also be used to increase performance levels when a temperature falls below a temperature limit. In the embodiment shown, the thermal control unit 15 can wait for another predetermined time to increase the performance of a corresponding functional unit, after a corresponding temperature reading has fallen below a given limit. If the predetermined time has elapsed, and the temperature remains below the limit, the thermal control circuit can increase the performance of a corresponding functional unit, for example, by increasing its clock frequency. On the other hand, if the temperature does not remain below the limit for the duration of the predetermined time, the thermal control unit 15 can keep the corresponding functional unit at a reduced performance level. It is noted that the predetermined times required to increase performance (when a temperature falls below a limit) and reducing performance (when a temperature is above the limit) may differ from one another. In addition, these predetermined times can be programmable.
    [00023] As previously noted, when its corresponding instructions are executed on processor core 12, SWTCM 19 can access temperature comparison results at intervals that are less frequent than the hardware-based thermal control mechanism. In addition, SWTCM 19 can take different actions that respond to temperature readings that exceed a limit. In this particular embodiment, responsive to a temperature reading from a particular temperature sensor 11 exceeding a maximum temperature limit, the processor core 12 can execute instructions for SWTCM 19 to shut down at least the corresponding functional unit. Typically, since the hardware-based thermal control mechanism updates more frequently, it can often be able to maintain temperatures within prescribed limits. A determination by SWTCM 19 that a temperature exceeds a maximum limit may indicate that the hardware-based thermal control mechanism has not been successful in keeping the temperature within prescribed limits, and thus shutdown can be performed to prevent potential damage to the IC circuit 10. The extent of the shutdown may vary based on the particular circumstances. For example, if a second term associated with just one functional unit is reporting a temperature higher than the upper limit, then only that functional unit can be turned off. In another example, if the thermal sensors associated with a number of functional units are reporting temperatures that exceed an upper limit, the entire IC 10 can be turned off. It is also noted that, if the processor core 12 has to be turned off in the mode shown, the processor core 14 can assume the role of executing instructions for SWTCM 19.
    [00024] In addition, up to a maximum temperature limit, the trip point circuit can compare received temperature readings with other limit values. Through the implementation of additional limit values, which are below the maximum value, the thermal output (and thus the temperature) of IC 10 and its respective functional units can be kept within limits while potentially preventing , shutdowns by SWTCM 19.
    [00025] Now returning to Fig. 2, a block diagram of a modality of a hardware-based thermal control device is shown. More particularly, Fig. 2 illustrates details for a modality of each of the trip point circuit 13 and the thermal control circuit 15. In this example embodiment, the hardware-based thermal control device is configured to monitor two temperature sensors. temperature 11 based on two different limits, for two different functional units (in this case, a processor core and a graphics unit). However, it is possible and considered modalities (including the modality illustrated in Fig. 1) in which temperatures reported by more than two temperature sensors 11 are monitored by more than two functional units. In addition, although comparisons are made against two different limits in this example, comparisons with more than two limits are also possible and considered for various modalities. Modes configured to monitor only a single temperature sensor 11, against only a single temperature limit and / or to control only a single functional unit are also possible and considered.
    [00026] In the mode shown, the trip point circuit 13 is coupled and includes four separate comparators 21A - 21D. Each comparator is coupled to receive temperature readings from one of the 11A or 11B temperature sensors. Trip point circuit 13 also includes limit recorders 22 and 23, which are configured to store first and second temperature limit values, respectively. In the mode shown, the temperature limit values are programmable. Instead of recorders, other storage devices that can store temperature limits can be implemented in other ways.
    [00027] Comparators 21A and 21C are coupled to limit register 22 in the mode shown, while comparators 21B and 21D are coupled to limit register 23. Comparators 21A and 21B are coupled to receive temperature readings from temperature sensor 11A , while comparators 21C and 21D are coupled to receive temperature readings from temperature sensor 11B. Comparators 21A and 21C in the mode shown are configured to compare temperature readings with the temperature limit value stored in limit register 22. Similarly, comparators 21B and 21D in the mode shown are configured to compare temperature readings with the limit value of temperature stored in limit register 23.
    [00028] The OR 27A gate in the mode shown is coupled to receive comparison results from comparators 21B and 21D. If a comparison result of both comparators 21B or 21D indicates that a correspondingly received temperature reading is above the temperature limit stored in the limit register 23, the OR 27A port can output logic 1. Otherwise, if none of the comparators 21B or 21D indicates that the temperature readings respectively received exceed the temperature limit stored in the limit register 23, from the OR 27B gate, a logic 0 can be output. The OR 27B port in the shown mode is coupled to receive comparison results from comparators 21A and 21C. If one of comparators 21A or 21C indicates that a received temperature reading exceeds the temperature limit stored in limit register 22, logic OR 27A can output logic 1. If none of comparators 21A or 21C indicates that received temperature readings exceed the temperature limit stored in limit register 22, then from logic OR 27A, logic 0 can be output.
    [00029] The counter / selector 24A in the mode shown is coupled to the output of the OR 27A port. Similarly, counter / selector 24B is coupled to the output of the OR 27B gate. Each of the counters / selectors in the mode shown can initiate a count that responds to a transition from the output of its OR gate respectively coupled. In addition, each counter / selector can also generate selection codes used to define a performance level for a given functional unit. Although not shown explicitly in Fig. 2, each of them can also be coupled to receive information from each of the 21A - 21D comparisons, in order to determine which of the temperature sensors 11A and / or 11B are reporting temperatures that are exceeding one of the temperature limit values. This can, in turn, allow the thermal control circuit 15 to control the respective performance levels of the correspondingly coupled functional units independently of one another.
    [00030] In the mode shown, the counter / selector unit 24A is configured to operate based on comparisons of temperature readings received with the temperature limit stored in the limit register 23), the counter / selector 24A can start a count. Counting can continue until a predefined count value is reached or until the OR 27A gate output changes again, whichever comes first. The predefined count value can correspond to a predetermined time. Thus, if the predefined count is reached, the counter / selector 24A can change an exit code in order to cause a change to a performance level of one or more functional units. If the predefined count is not reached before the OR 27A gate output changes state again, then the counter / selector 24A can keep its current output code (s), thus allowing the functional units of IC 10 maintain their present performance levels. The counter / selector 24B can operate in a similar manner with respect to the OR 27B port. Changing performance levels may include reducing a performance level (for example, by reducing the frequency of a respectively received clock signal) or increasing a performance level (for example, by increasing the frequency of a respectively received). Reductions in performance levels may occur in response to the determination that a temperature reading is exceeding one of the limit values. Increases in performance levels may occur in response to the determination that a temperature reading has fallen below a previously exceeded temperature threshold value.
    [00031] The exit codes provided by the counter / selectors 24A and 24B can be received at inputs selected by multiplexers 31A and 31B. In one embodiment, multiplexers 31A and 31B can be controlled independently. In other embodiments, multiplexers 31A and 31B can operate in harmony with one another. Each of the multiplexers 31A and 31B is coupled to receive divider values as inputs. The divider value selected by the multiplexer 31A can be received by the clock divider 32B. Each of the multiplexers 31A and 31B in the mode shown is coupled to receive three divider inputs: total frequency (ie, divide by 1), divisor 1 and divisor 2. The last two dividers can cause a receipt of one of the dividers 32A and 32B to divide its input clock signal respectively received in order to produce an output clock signal having a lower frequency. For example, if divisor 1 = 2, then, when received by divisor 32A, output signal C LK 1 will have a frequency that is half that of the input clock signal, CPU Clk 1.
    [00032] Thereby, the thermal control circuit 15 in this particular example can control the performance level of a processor core and a graphics unit by controlling the clock signal frequencies provided therein. Switching the total frequency to divisor 1 can reduce the frequency of a split of the clock signals by a first amount. Switching to divider 2 can reduce the clock signal frequency divided by a second quantity. By changing the dividers received by the dividers 32A and 32B, the corresponding clock frequencies and performance levels of the IC 10 functional units can be controlled according to the received temperature readings. Although performance levels are controlled via clock frequencies in the modality shown, it is noted that modalities that control performance levels using different methods are possible and considered. For example, supply voltages, workloads, bandwidth and other parameters can be changed to control performance in various ways. In addition, modalities in which multiple parameters are adjustable to control performance according to received temperature readings are possible and considered.
    [00033] Figs. 3A and 3B are synchronization diagrams illustrating hysteresis in the operation of a modality of a hardware-based thermal control device. It is noted that these examples are given for only a single limit and two levels of performance, although as noted above, modalities are possible and considered for multiple limits with multiple levels of performance.
    [00034] Fig. 3A illustrates hysteresis in changing performance levels in response to temperature readings across a temperature threshold. The example shown in Fig. 3A starts with a received temperature being below a threshold value. In (A), the temperature level is determined to have exceeded the limit. For a T1 time, then performance is maintained at its current level. When T1 has elapsed (for example, indicated by a counter / selector, such as the one discussed above with reference to Fig. 2), the temperature remains above the limit and the performance of a functional unit drops from its normal level to a reduced level.
    [00035] In (B), the temperature once again fell below the limit level. For a time T2 then the performance level of the functional unit is kept at a low level. When the T2 time has elapsed, the temperature remains below the limit and, thus, the performance level of the functional unit is restored to its normal level. It is noted that in this particular mode, times T1 and T2 are different. However, the modalities in which these values are the same are also possible. In addition, these values can be programmable in some modalities.
    [00036] In Fig. 3B, the temperature once again starts at a level that is below the limit. In (C), the temperature is determined to be above the limit. An accountant can then start counting to tell the time. However, in that case, the temperature drops back below the threshold before time T1 has elapsed. Since the limit is no longer exceeded after T1 has elapsed, the performance level is thus maintained.
    [00037] By using hysteresis in the hardware-based thermal control mechanism, a balance between thermal control and performance can be achieved. More particularly, the addition of hysteresis to the operation of the hardware-based thermal control mechanism can be useful in preventing the performance level from changing to short-term temperature changes that exceed or fall below a limit, while allowing enough time to determine if a change in performance level is desirable.
    [00038] Fig. 4 is a flow chart illustrating the combined operation of a modality of a hardware-based thermal control mechanism in conjunction with a modality of a software-based thermal control mechanism. Method 400 in the modality shown can be performed using various combinations of hardware and software modalities discussed above or can be implemented using other modalities not explicitly discussed here. The method described here is aimed at a single temperature sensor. However, as noted above, the method can be performed simultaneously for any number of sensors with both hardware and software based thermal control mechanisms.
    [00039] Method 400 begins with monitoring the temperature reading received from a temperature sensor in an IC or within a system (block 405). Monitoring can be carried out simultaneously by a hardware-based thermal control mechanism and a software-based thermal control mechanism. The hardware-based thermal control mechanism can monitor temperatures in first length intervals, while the software-based thermal control mechanism can monitor temperatures in second length intervals. The hardware-based thermal control mechanism can monitor temperature readings more frequently than the software-based thermal control mechanism.
    [00040] During the monitoring of the temperature readings of the temperature sensors, comparisons of the temperature reading with a first temperature limit can be performed. If the temperature reading does not exceed the first limit (block 435, no), then the operation of a corresponding functional unit or other controlled subsystem can be maintained at a standard performance level (for example, complete). If the temperature reading exceeds the first temperature limit (block 410, yes), but does not exceed a second temperature limit (block 415, no), then the performance of the functional unit can be established at a reduced first level (block 420). In one embodiment, operation at a reduced first level may include reducing a clock signal frequency from that of the full frequency during normal mode of operation. Other methods of reducing the performance of a functional unit are also possible and considered, including those that change two or more operating parameters.
    [00041] As noted above, the monitoring of temperature readings can be carried out by the thermal control mechanisms based on hardware and software. In this mode, the software-based thermal control mechanism can ignore comparisons of temperature readings with the second limit. The second limit in this modality is greater than the first limit. Thus, if a comparison determines that a temperature reading is greater than the second limit (block 415, yes), the subsequent actions performed depend on whether the comparison information is used by the hardware-based thermal control mechanism or by the mechanism software-based thermal control. When the hardware-based thermal control mechanism determines that a temperature reading exceeds the second limit (block 425, HW), the performance of the functional unit can be established at a reduced second level.
    [00042] If the software-based thermal control mechanism determines that the temperature reading exceeds the second limit (block 425, SW), then at least the functional unit (if not the IC / system itself) can be switched off (block 440). Since the hardware-based thermal control mechanism monitors temperature readings against temperature limits more often than the software-based thermal control mechanism, a determination of a reading exceeding the second limit by the latter may indicate that the hardware mechanism is unable to bring the temperature of the functional unit (or the IC / system as a whole) under control. As a result, shutdown can be performed to prevent the possibility of damage to the system. In addition, since the hardware-based mechanism monitors temperature readings against temperature limits, more often than the software-based thermal control mechanism, the probability of a temperature reading exceeding the second limit is reduced, how is the probability that this result will be detected by the software-based mechanism.
    [00043] When operating at one of the reduced performance levels, the hardware-based mechanism can continue to monitor temperature readings against the 405 block limits. When operating at the second reduced performance level, the detected temperature readings below the second limit, eventually, the hardware-based engine may result in increasing the performance level back to the first reduced performance level. If subsequent temperature readings indicate that the temperature has dropped below the first limit, the hardware-based mechanism can further increase the performance level back to the normal performance level. In reducing and increasing performance levels, hysteresis can be employed so that performance levels are not reduced or increased due to brief changes in temperature that are not otherwise part of a tendency to increase or decrease the temperature. This, in turn, can allow for longer term optimization of the performance level based on the global trend of temperature changes.
    [00044] Going back to Fig. 5, a block diagram of a modality of a system 150 is shown. In the illustrated embodiment, system 150 includes at least one example of an IC 5 (for example, which implements processor 10 in Fig. 1) coupled to one or more peripherals 154 and an external memory 158. A power supply 156 is provided , which supplies the supply voltages for IC 10, as well as one or more supply voltages for memory 158 and / or peripherals 154. In some embodiments, more than one example of IC 10 can be included (and more than an external memory 158 can also be included).
    [00045] Peripherals 154 can include any desired circuit, depending on the type of system 150. For example, in one embodiment, system 150 can be a mobile device (for example, personal digital assistant (PDA), smartphone, etc.) and peripherals 154 may include devices for various types of wireless communication, such as wi-fi, Bluetooth, mobile, global positioning system, etc. The peripherals 154 may also include additional storage, including RAM storage, solid state storage or disk storage. Peripherals 154 may include user interface devices, such as a display screen, including touch display screens or multi-touch display screens, keyboard or other input devices, microphones, speakers, etc. In other embodiments, system 150 can be any type of computing system (for example, desktop personal computer, laptop, workstation, net top, etc.).
    [00046] External memory 158 can include any type of memory. For example, external memory 158 can be dynamic SRAM, RAM (DRAM), such as synchronous DRAM (SDRAM), dual data rate (DDR, DDR2, DDR3, LPDDR1, LPDDR2, etc.) SDRAM, RAMBUS DRAM, etc. External memory 158 may include one or more memory modules on which memory devices are mounted, such as single-line memory modules (SIMMs), double-line memory modules (DIMMs), etc.
    [00047] Numerous variations and modifications will become evident to those skilled in the art once the above exposure is fully appreciated. The following claims are intended to be interpreted to involve all such variations and modifications.
    权利要求:
    Claims (14)
    [0001]
    1. Apparatus comprising: - one or more thermal sensors (11); - a thermal trip point circuit (13) coupled to one or more thermal sensors and configured to detect that one or more thermal limits (22, 23) have been exceeded by the respective outputs of one or more thermal sensors; and - a thermal control circuit (15) configured to respond to the thermal trip point circuit which indicates that one or more thermal limits have been exceeded by reducing a performance level of one or more subsystems controlled in the apparatus (12, 14, 16); characterized by the fact that a processor (12) is configured to execute instructions from a thermal control software program (19) that operates in parallel with the thermal control circuit and the thermal trip point circuit, in which the control program thermal control software is configured to shut down at least one of the controlled subsystems in response to the determination that one second of one or more thermal limits has been exceeded; where the thermal control software program is configured to acquire the respective temperature readings from the thermal sensors (11) at a first frequency and where the thermal trip point circuit (13) is configured to acquire the respective readings temperature from the thermal sensors at a second frequency that is higher than the first frequency.
    [0002]
    2. Apparatus, according to claim 1, characterized by the fact that the thermal control circuit is configured to reduce the performance of one or more controlled subsystems (12, 14, 16) in the apparatus by reducing a frequency of a signal of clock (Clk 1, Clk 2, Clk 3) provided for one or more controlled subsystems.
    [0003]
    3. Apparatus according to claim 1, characterized by the fact that the thermal control circuit (15) is configured to reduce the performance of one or more controlled subsystems (12, 14, 16) in the apparatus by reducing a voltage of power supplied to one or more controlled subsystems.
    [0004]
    4. Apparatus according to claim 1, characterized by the fact that the thermal control circuit (15) is configured to respond to the thermal trip point circuit (13) which indicates that one or more thermal limits have been exceeded in one predetermined time subsequent to the thermal trip point circuit which indicates that one or more thermal limits have been exceeded.
    [0005]
    5. Apparatus according to claim 1, characterized by the fact that the thermal control circuit (15) is configured to discontinue the performance reduction of one or more controlled subsystems (12, 14, 16) in a subsequent predetermined time to the thermal trip point circuit which indicates that one or more thermal limits are no longer exceeded by the output of one or more thermal sensors (11).
    [0006]
    6. Method comprising the steps of: - determining, using the thermal trip point circuit (13), whether one or more thermal limits (22, 23) have been exceeded by the respective outputs received from one or more thermal sensors (11) ; - reduce a performance level of one or more controlled subsystems (12, 14, 16) of an integrated circuit (1) that responds to the thermal trip point circuit which indicates that one or more thermal limits have been exceeded, in which said reduction is carried out by the thermal control circuit (15); characterized by the fact that - processing circuit (12) is executing instructions from a thermal control software program that operates in parallel with the processing circuit, in which the thermal control software program is configured to monitor whether one or more thermal limits have been exceeded by the respective outputs received from one or more thermal sensors, in which the intervals in which the outputs from one or more thermal sensors are monitored by the thermal control software program are less frequent than the intervals in which the thermal trip point circuit monitors outputs from one or more thermal sensors.
    [0007]
    7. Method according to claim 6, characterized by the fact that the reduction in the level of performance comprises reducing, by the thermal control circuit (15), a clock signal frequency (Clk 1, Clk 2, Clk 3 ) provided for at least one or more controlled subsystems.
    [0008]
    8. Method, according to claim 6, characterized by the fact that it still comprises reducing the level of performance, by the thermal control circuit (15), of at least one of the controlled subsystems (12, 14, 16) in response to determining that one or more thermal limits have been exceeded for at least a predetermined first time.
    [0009]
    9. Method, according to claim 8, characterized by the fact that it still comprises, after a reduction in the performance level of at least one of the controlled subsystems, increasing the performance of at least one of the controlled subsystems (12, 14, 16 ) in response to the determination that the outputs of at least one of the thermal sensors is below at least one of the thermal limits for at least a second predetermined time.
    [0010]
    10. Method, according to claim 6, characterized by the fact that it still comprises the step of: - shutting down at least one of the controlled subsystems (12, 14, 16) in response to the determination, by the thermal control software program, that one or more thermal limits have been exceeded.
    [0011]
    11. Integrated circuit comprising: - first and second temperature sensors (11) associated with the first and second functional units (14, 16) of the integrated circuit, respectively; - a comparison circuit (13) configured to determine whether a temperature reading from at least one of the first and second temperature sensors exceeds a first limit; and - a thermal control circuit (15) configured to reduce, in a first quantity, a frequency of a clock signal supplied to at least one of the first and second functional units in response to the detection, by the comparison circuit, of a reading temperature that exceeds the first limit; characterized by the fact that: a processor (12) configured to execute instructions for a software-based temperature control routine (19), in which the software-based temperature control routine is configured to acquire the respective temperature readings temperature from the first and second temperature sensors at a first frequency and where the comparison circuit is configured to acquire the respective temperature readings from the first and second temperature sensors at a second frequency that is higher than the first frequency.
    [0012]
    12. Integrated circuit, according to claim 11, characterized by the fact that the thermal control circuit (15) is configured to reduce, in a second quantity, the clock signal frequency in response to the temperature reading that exceeds a second limit.
    [0013]
    13. Integrated circuit, according to claim 11, characterized by the fact that the thermal control circuit (15) is configured to reduce the clock signal frequency in response to the determination, by the comparison circuit (13), that the first limit was exceeded in a first duration.
    [0014]
    14. Integrated circuit, according to claim 13, characterized by the fact that the thermal control circuit (15) is configured to increase the clock signal frequency after the comparison circuit (13) determines that the temperature readings coming from of the first and second temperature sensors were below the first limit for a second duration.
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    JP5638110B2|2014-12-10|
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    法律状态:
    2015-06-23| B03A| Publication of a patent application or of a certificate of addition of invention [chapter 3.1 patent gazette]|
    2018-12-04| B06F| Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]|
    2019-11-19| B06U| Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]|
    2020-08-11| B09A| Decision: intention to grant [chapter 9.1 patent gazette]|
    2020-12-08| B16A| Patent or certificate of addition of invention granted|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 19/06/2013, OBSERVADAS AS CONDICOES LEGAIS. |
    优先权:
    申请号 | 申请日 | 专利标题
    US13/529,202|2012-06-21|
    US13/529,202|US9383789B2|2012-06-21|2012-06-21|Thermal control apparatus and methodology|
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